1 //===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Parent TargetRegisterInfo class common to all hw codegen targets.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPURegisterInfo.h"
16 #include "AMDGPUTargetMachine.h"
17 #include "SIRegisterInfo.h"
18 
19 using namespace llvm;
20 
21 AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {}
22 
23 //===----------------------------------------------------------------------===//
24 // Function handling callbacks - Functions are a seldom used feature of GPUS, so
25 // they are not supported at this time.
26 //===----------------------------------------------------------------------===//
27 
28 unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
29   static const unsigned SubRegs[] = {
30     AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, AMDGPU::sub4,
31     AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, AMDGPU::sub8, AMDGPU::sub9,
32     AMDGPU::sub10, AMDGPU::sub11, AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14,
33     AMDGPU::sub15
34   };
35 
36   assert(Channel < array_lengthof(SubRegs));
37   return SubRegs[Channel];
38 }
39 
40 #define GET_REGINFO_TARGET_DESC
41 #include "AMDGPUGenRegisterInfo.inc"
42 
43 // Forced to be here by one .inc
44 const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs(
45   const MachineFunction *MF) const {
46   CallingConv::ID CC = MF->getFunction()->getCallingConv();
47   switch (CC) {
48   case CallingConv::C:
49   case CallingConv::Fast:
50     return CSR_AMDGPU_HighRegs_SaveList;
51   default: {
52     // Dummy to not crash RegisterClassInfo.
53     static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
54     return &NoCalleeSavedReg;
55   }
56   }
57 }
58 
59 const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
60                                                      CallingConv::ID CC) const {
61   switch (CC) {
62   case CallingConv::C:
63   case CallingConv::Fast:
64     return CSR_AMDGPU_HighRegs_RegMask;
65   default:
66     return nullptr;
67   }
68 }
69 
70 unsigned SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
71   return AMDGPU::NoRegister;
72 }
73