1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains DAG node defintions for the AMDGPU target.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// AMDGPU DAG Profiles
16//===----------------------------------------------------------------------===//
17
18def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
19  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
20]>;
21
22def AMDGPUTrigPreOp : SDTypeProfile<1, 2,
23  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
24>;
25
26def AMDGPULdExpOp : SDTypeProfile<1, 2,
27  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
28>;
29
30def AMDGPUFPClassOp : SDTypeProfile<1, 2,
31  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
32>;
33
34def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
35  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
36>;
37
38// float, float, float, vcc
39def AMDGPUFmasOp : SDTypeProfile<1, 4,
40  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
41>;
42
43def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
44
45//===----------------------------------------------------------------------===//
46// AMDGPU DAG Nodes
47//
48
49def AMDGPUconstdata_ptr : SDNode<
50  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
51                                                     SDTCisVT<0, iPTR>]>
52>;
53
54// This argument to this node is a dword address.
55def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
56
57// Force dependencies for vector trunc stores
58def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
59
60def AMDGPUcos : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
61def AMDGPUsin : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
62
63// out = a - floor(a)
64def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
65
66// out = 1.0 / a
67def AMDGPUrcp : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
68
69// out = 1.0 / sqrt(a)
70def AMDGPUrsq : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
71
72// out = 1.0 / sqrt(a)
73def AMDGPUrcp_legacy : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
74def AMDGPUrsq_legacy : SDNode<"AMDGPUISD::RSQ_LEGACY", SDTFPUnaryOp>;
75
76// out = 1.0 / sqrt(a) result clamped to +/- max_float.
77def AMDGPUrsq_clamp : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
78
79def AMDGPUldexp : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
80
81def AMDGPUfp_class : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
82
83// out = max(a, b) a and b are floats, where a nan comparison fails.
84// This is not commutative because this gives the second operand:
85//   x < nan ? x : nan -> nan
86//   nan < x ? nan : x -> x
87def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
88  []
89>;
90
91def AMDGPUfmul_legacy : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
92  [SDNPCommutative, SDNPAssociative]
93>;
94
95def AMDGPUclamp : SDNode<"AMDGPUISD::CLAMP", SDTFPTernaryOp, []>;
96
97// out = max(a, b) a and b are signed ints
98def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
99  [SDNPCommutative, SDNPAssociative]
100>;
101
102// out = max(a, b) a and b are unsigned ints
103def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
104  [SDNPCommutative, SDNPAssociative]
105>;
106
107// out = min(a, b) a and b are floats, where a nan comparison fails.
108def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
109  []
110>;
111
112// FIXME: TableGen doesn't like commutative instructions with more
113// than 2 operands.
114// out = max(a, b, c) a, b and c are floats
115def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
116  [/*SDNPCommutative, SDNPAssociative*/]
117>;
118
119// out = max(a, b, c) a, b, and c are signed ints
120def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
121  [/*SDNPCommutative, SDNPAssociative*/]
122>;
123
124// out = max(a, b, c) a, b and c are unsigned ints
125def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
126  [/*SDNPCommutative, SDNPAssociative*/]
127>;
128
129// out = min(a, b, c) a, b and c are floats
130def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
131  [/*SDNPCommutative, SDNPAssociative*/]
132>;
133
134// out = min(a, b, c) a, b and c are signed ints
135def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
136  [/*SDNPCommutative, SDNPAssociative*/]
137>;
138
139// out = min(a, b) a and b are unsigned ints
140def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
141  [/*SDNPCommutative, SDNPAssociative*/]
142>;
143
144// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
145def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
146
147// out = (src1 > src0) ? 1 : 0
148def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
149
150def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
151  SDTCisVT<0, i64>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
152]>;
153
154def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
155
156def AMDGPUSetRegOp :  SDTypeProfile<0, 2, [
157  SDTCisInt<0>, SDTCisInt<1>
158]>;
159
160def AMDGPUsetreg : SDNode<"AMDGPUISD::SETREG", AMDGPUSetRegOp, [
161  SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, SDNPOutGlue]>;
162
163def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
164   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
165
166def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
167  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
168
169def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
170  SDTIntToFPOp, []>;
171def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
172  SDTIntToFPOp, []>;
173def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
174  SDTIntToFPOp, []>;
175def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
176  SDTIntToFPOp, []>;
177
178
179// urecip - This operation is a helper for integer division, it returns the
180// result of 1 / a as a fractional unsigned integer.
181// out = (2^32 / a) + e
182// e is rounding error
183def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
184
185// Special case divide preop and flags.
186def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
187
188//  Special case divide FMA with scale and flags (src0 = Quotient,
189//  src1 = Denominator, src2 = Numerator).
190def AMDGPUdiv_fmas : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp>;
191
192// Single or double precision division fixup.
193// Special case divide fixup and flags(src0 = Quotient, src1 =
194// Denominator, src2 = Numerator).
195def AMDGPUdiv_fixup : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
196
197// Look Up 2.0 / pi src0 with segment select src1[4:0]
198def AMDGPUtrig_preop : SDNode<"AMDGPUISD::TRIG_PREOP", AMDGPUTrigPreOp>;
199
200def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
201                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
202                          [SDNPHasChain, SDNPMayLoad]>;
203
204def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
205                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
206                           [SDNPHasChain, SDNPMayStore]>;
207
208// MSKOR instructions are atomic memory instructions used mainly for storing
209// 8-bit and 16-bit values.  The definition is:
210//
211// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
212//
213// src0: vec4(src, 0, 0, mask)
214// src1: dst - rat offset (aka pointer) in dwords
215def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
216                        SDTypeProfile<0, 2, []>,
217                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
218
219def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
220                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
221                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
222                             SDNPMemOperand]>;
223
224def AMDGPUround : SDNode<"ISD::FROUND",
225                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
226
227def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
228def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
229def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
230def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
231
232def AMDGPUffbh_u32 : SDNode<"AMDGPUISD::FFBH_U32", SDTIntUnaryOp>;
233def AMDGPUffbh_i32 : SDNode<"AMDGPUISD::FFBH_I32", SDTIntUnaryOp>;
234
235// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
236// when performing the mulitply. The result is a 32-bit value.
237def AMDGPUmul_u24 : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
238  [SDNPCommutative, SDNPAssociative]
239>;
240def AMDGPUmul_i24 : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
241  [SDNPCommutative, SDNPAssociative]
242>;
243
244def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
245  [SDNPCommutative, SDNPAssociative]
246>;
247def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
248  [SDNPCommutative, SDNPAssociative]
249>;
250
251def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
252  []
253>;
254def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
255  []
256>;
257
258def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
259  []
260>;
261
262def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
263  []
264>;
265
266def AMDGPUfmed3 : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
267
268def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG",
269                    SDTypeProfile<0, 1, [SDTCisInt<0>]>,
270                    [SDNPHasChain, SDNPInGlue]>;
271
272def AMDGPUsendmsghalt : SDNode<"AMDGPUISD::SENDMSGHALT",
273                    SDTypeProfile<0, 1, [SDTCisInt<0>]>,
274                    [SDNPHasChain, SDNPInGlue]>;
275
276def AMDGPUinterp_mov : SDNode<"AMDGPUISD::INTERP_MOV",
277                        SDTypeProfile<1, 3, [SDTCisFP<0>]>,
278                        [SDNPInGlue]>;
279
280def AMDGPUinterp_p1 : SDNode<"AMDGPUISD::INTERP_P1",
281                      SDTypeProfile<1, 3, [SDTCisFP<0>]>,
282                      [SDNPInGlue, SDNPOutGlue]>;
283
284def AMDGPUinterp_p2 : SDNode<"AMDGPUISD::INTERP_P2",
285                      SDTypeProfile<1, 4, [SDTCisFP<0>]>,
286                      [SDNPInGlue]>;
287
288
289def AMDGPUkill : SDNode<"AMDGPUISD::KILL", AMDGPUKillSDT,
290  [SDNPHasChain, SDNPSideEffect]>;
291
292// SI+ export
293def AMDGPUExportOp : SDTypeProfile<0, 8, [
294  SDTCisInt<0>, // i8 en
295  SDTCisInt<1>, // i1 vm
296  // skip done
297  SDTCisInt<2>, // i8 tgt
298  SDTCisSameAs<3, 1>, // i1 compr
299  SDTCisFP<4>,        // f32 src0
300  SDTCisSameAs<5, 4>, // f32 src1
301  SDTCisSameAs<6, 4>, // f32 src2
302  SDTCisSameAs<7, 4>  // f32 src3
303]>;
304
305def AMDGPUexport: SDNode<"AMDGPUISD::EXPORT", AMDGPUExportOp,
306  [SDNPHasChain, SDNPMayStore]>;
307
308def AMDGPUexport_done: SDNode<"AMDGPUISD::EXPORT_DONE", AMDGPUExportOp,
309  [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
310
311
312def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
313
314def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
315  [SDNPHasChain, SDNPSideEffect]>;
316
317//===----------------------------------------------------------------------===//
318// Flow Control Profile Types
319//===----------------------------------------------------------------------===//
320// Branch instruction where second and third are basic blocks
321def SDTIL_BRCond : SDTypeProfile<0, 2, [
322    SDTCisVT<0, OtherVT>
323    ]>;
324
325//===----------------------------------------------------------------------===//
326// Flow Control DAG Nodes
327//===----------------------------------------------------------------------===//
328def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
329
330//===----------------------------------------------------------------------===//
331// Call/Return DAG Nodes
332//===----------------------------------------------------------------------===//
333def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
334    [SDNPHasChain, SDNPOptInGlue]>;
335
336def AMDGPUreturn : SDNode<"AMDGPUISD::RETURN", SDTNone,
337    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
338