1//===- AMDGPUGenRegisterBankInfo.def -----------------------------*- C++ -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file defines all the static objects used by AMDGPURegisterBankInfo.
11/// \todo This should be generated by TableGen.
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_BUILD_GLOBAL_ISEL
15#error "You shouldn't build this"
16#endif
17
18namespace llvm {
19namespace AMDGPU {
20
21enum PartialMappingIdx {
22  None = - 1,
23  PM_SGPR32 = 0,
24  PM_SGPR64 = 1,
25  PM_VGPR32 = 2,
26  PM_VGPR64 = 3
27};
28
29const RegisterBankInfo::PartialMapping PartMappings[] {
30  // StartIdx, Length, RegBank
31  {0, 32, SGPRRegBank},
32  {0, 64, SGPRRegBank},
33  {0, 32, VGPRRegBank},
34  {0, 64, VGPRRegBank}
35};
36
37const RegisterBankInfo::ValueMapping ValMappings[] {
38  // SGPR 32-bit
39  {&PartMappings[0], 1},
40  // SGPR 64-bit
41  {&PartMappings[1], 1},
42  // VGPR 32-bit
43  {&PartMappings[2], 1},
44  // VGPR 64-bit
45  {&PartMappings[3], 1}
46};
47
48enum ValueMappingIdx {
49  SGPRStartIdx = 0,
50  VGPRStartIdx = 2
51};
52
53const RegisterBankInfo::ValueMapping *getValueMapping(unsigned BankID,
54                                                      unsigned Size) {
55  assert(Size % 32 == 0);
56  unsigned Idx = BankID == AMDGPU::SGPRRegBankID ? SGPRStartIdx : VGPRStartIdx;
57  Idx += (Size / 32) - 1;
58  return &ValMappings[Idx];
59}
60
61} // End AMDGPU namespace.
62} // End llvm namespace.
63