1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/Target/Target.td"
11
12//===------------------------------------------------------------===//
13// Subtarget Features (device properties)
14//===------------------------------------------------------------===//
15
16def FeatureFP64 : SubtargetFeature<"fp64",
17  "FP64",
18  "true",
19  "Enable double precision operations"
20>;
21
22def FeatureFMA : SubtargetFeature<"fmaf",
23  "FMA",
24  "true",
25  "Enable single precision FMA (not as fast as mul+add, but fused)"
26>;
27
28def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
29  "FastFMAF32",
30  "true",
31  "Assuming f32 fma is at least as fast as mul + add"
32>;
33
34def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
35  "HalfRate64Ops",
36  "true",
37  "Most fp64 instructions are half rate instead of quarter"
38>;
39
40def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
41  "R600ALUInst",
42  "false",
43  "Older version of ALU instructions encoding"
44>;
45
46def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
47  "HasVertexCache",
48  "true",
49  "Specify use of dedicated vertex cache"
50>;
51
52def FeatureCaymanISA : SubtargetFeature<"caymanISA",
53  "CaymanISA",
54  "true",
55  "Use Cayman ISA"
56>;
57
58def FeatureCFALUBug : SubtargetFeature<"cfalubug",
59  "CFALUBug",
60  "true",
61  "GPU has CF_ALU bug"
62>;
63
64def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
65  "FlatAddressSpace",
66  "true",
67  "Support flat address space"
68>;
69
70def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
71  "FlatInstOffsets",
72  "true",
73  "Flat instructions have immediate offset addressing mode"
74>;
75
76def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
77  "FlatGlobalInsts",
78  "true",
79  "Have global_* flat memory instructions"
80>;
81
82def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
83  "FlatScratchInsts",
84  "true",
85  "Have scratch_* flat memory instructions"
86>;
87
88def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
89  "AddNoCarryInsts",
90  "true",
91  "Have VALU add/sub instructions without carry out"
92>;
93
94def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
95  "UnalignedBufferAccess",
96  "true",
97  "Support unaligned global loads and stores"
98>;
99
100def FeatureTrapHandler: SubtargetFeature<"trap-handler",
101  "TrapHandler",
102  "true",
103  "Trap handler support"
104>;
105
106def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
107  "UnalignedScratchAccess",
108  "true",
109  "Support unaligned scratch loads and stores"
110>;
111
112def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
113  "HasApertureRegs",
114  "true",
115  "Has Memory Aperture Base and Size Registers"
116>;
117
118def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
119  "HasMadMixInsts",
120  "true",
121  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
122>;
123
124// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
125// XNACK. The current default kernel driver setting is:
126// - graphics ring: XNACK disabled
127// - compute ring: XNACK enabled
128//
129// If XNACK is enabled, the VMEM latency can be worse.
130// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
131def FeatureXNACK : SubtargetFeature<"xnack",
132  "EnableXNACK",
133  "true",
134  "Enable XNACK support"
135>;
136
137def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
138  "SGPRInitBug",
139  "true",
140  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
141>;
142
143class SubtargetFeatureFetchLimit <string Value> :
144                          SubtargetFeature <"fetch"#Value,
145  "TexVTXClauseSize",
146  Value,
147  "Limit the maximum number of fetches in a clause to "#Value
148>;
149
150def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
151def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
152
153class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
154  "wavefrontsize"#Value,
155  "WavefrontSize",
156  !cast<string>(Value),
157  "The number of threads per wavefront"
158>;
159
160def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
161def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
162def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
163
164class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
165  "ldsbankcount"#Value,
166  "LDSBankCount",
167  !cast<string>(Value),
168  "The number of LDS banks per compute unit."
169>;
170
171def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
172def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
173
174class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
175  "localmemorysize"#Value,
176  "LocalMemorySize",
177  !cast<string>(Value),
178  "The size of local memory in bytes"
179>;
180
181def FeatureGCN : SubtargetFeature<"gcn",
182  "IsGCN",
183  "true",
184  "GCN or newer GPU"
185>;
186
187def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
188  "GCN3Encoding",
189  "true",
190  "Encoding format for VI"
191>;
192
193def FeatureCIInsts : SubtargetFeature<"ci-insts",
194  "CIInsts",
195  "true",
196  "Additional instructions for CI+"
197>;
198
199def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
200  "GFX9Insts",
201  "true",
202  "Additional instructions for GFX9+"
203>;
204
205def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
206  "HasSMemRealTime",
207  "true",
208  "Has s_memrealtime instruction"
209>;
210
211def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
212  "HasInv2PiInlineImm",
213  "true",
214  "Has 1 / (2 * pi) as inline immediate"
215>;
216
217def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
218  "Has16BitInsts",
219  "true",
220  "Has i16/f16 instructions"
221>;
222
223def FeatureVOP3P : SubtargetFeature<"vop3p",
224  "HasVOP3PInsts",
225  "true",
226  "Has VOP3P packed instructions"
227>;
228
229def FeatureMovrel : SubtargetFeature<"movrel",
230  "HasMovrel",
231  "true",
232  "Has v_movrel*_b32 instructions"
233>;
234
235def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
236  "HasVGPRIndexMode",
237  "true",
238  "Has VGPR mode register indexing"
239>;
240
241def FeatureScalarStores : SubtargetFeature<"scalar-stores",
242  "HasScalarStores",
243  "true",
244  "Has store scalar memory instructions"
245>;
246
247def FeatureSDWA : SubtargetFeature<"sdwa",
248  "HasSDWA",
249  "true",
250  "Support SDWA (Sub-DWORD Addressing) extension"
251>;
252
253def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
254  "HasSDWAOmod",
255  "true",
256  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
257>;
258
259def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
260  "HasSDWAScalar",
261  "true",
262  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
263>;
264
265def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
266  "HasSDWASdst",
267  "true",
268  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
269>;
270
271def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
272  "HasSDWAMac",
273  "true",
274  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
275>;
276
277def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
278  "HasSDWAOutModsVOPC",
279  "true",
280  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
281>;
282
283def FeatureDPP : SubtargetFeature<"dpp",
284  "HasDPP",
285  "true",
286  "Support DPP (Data Parallel Primitives) extension"
287>;
288
289def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
290  "HasIntClamp",
291  "true",
292  "Support clamp for integer destination"
293>;
294
295//===------------------------------------------------------------===//
296// Subtarget Features (options and debugging)
297//===------------------------------------------------------------===//
298
299// Some instructions do not support denormals despite this flag. Using
300// fp32 denormals also causes instructions to run at the double
301// precision rate for the device.
302def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
303  "FP32Denormals",
304  "true",
305  "Enable single precision denormal handling"
306>;
307
308// Denormal handling for fp64 and fp16 is controlled by the same
309// config register when fp16 supported.
310// TODO: Do we need a separate f16 setting when not legal?
311def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
312  "FP64FP16Denormals",
313  "true",
314  "Enable double and half precision denormal handling",
315  [FeatureFP64]
316>;
317
318def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
319  "FP64FP16Denormals",
320  "true",
321  "Enable double and half precision denormal handling",
322  [FeatureFP64, FeatureFP64FP16Denormals]
323>;
324
325def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
326  "FP64FP16Denormals",
327  "true",
328  "Enable half precision denormal handling",
329  [FeatureFP64FP16Denormals]
330>;
331
332def FeatureDX10Clamp : SubtargetFeature<"dx10-clamp",
333  "DX10Clamp",
334  "true",
335  "clamp modifier clamps NaNs to 0.0"
336>;
337
338def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
339  "FPExceptions",
340  "true",
341  "Enable floating point exceptions"
342>;
343
344class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
345  "max-private-element-size-"#size,
346  "MaxPrivateElementSize",
347  !cast<string>(size),
348  "Maximum private access size may be "#size
349>;
350
351def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
352def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
353def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
354
355def FeatureEnableHugePrivateBuffer : SubtargetFeature<
356  "huge-private-buffer",
357  "EnableHugePrivateBuffer",
358  "true",
359  "Enable private/scratch buffer sizes greater than 128 GB"
360>;
361
362def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
363  "EnableVGPRSpilling",
364  "true",
365  "Enable spilling of VGPRs to scratch memory"
366>;
367
368def FeatureDumpCode : SubtargetFeature <"DumpCode",
369  "DumpCode",
370  "true",
371  "Dump MachineInstrs in the CodeEmitter"
372>;
373
374def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
375  "DumpCode",
376  "true",
377  "Dump MachineInstrs in the CodeEmitter"
378>;
379
380def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
381  "EnablePromoteAlloca",
382  "true",
383  "Enable promote alloca pass"
384>;
385
386// XXX - This should probably be removed once enabled by default
387def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
388  "EnableLoadStoreOpt",
389  "true",
390  "Enable SI load/store optimizer pass"
391>;
392
393// Performance debugging feature. Allow using DS instruction immediate
394// offsets even if the base pointer can't be proven to be base. On SI,
395// base pointer values that won't give the same result as a 16-bit add
396// are not safe to fold, but this will override the conservative test
397// for the base pointer.
398def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
399  "unsafe-ds-offset-folding",
400  "EnableUnsafeDSOffsetFolding",
401  "true",
402  "Force using DS instruction immediate offsets on SI"
403>;
404
405def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
406  "EnableSIScheduler",
407  "true",
408  "Enable SI Machine Scheduler"
409>;
410
411// Unless +-flat-for-global is specified, turn on FlatForGlobal for
412// all OS-es on VI and newer hardware to avoid assertion failures due
413// to missing ADDR64 variants of MUBUF instructions.
414// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
415// instructions.
416
417def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
418  "FlatForGlobal",
419  "true",
420  "Force to generate flat instruction for global"
421>;
422
423def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
424  "auto-waitcnt-before-barrier",
425  "AutoWaitcntBeforeBarrier",
426  "true",
427  "Hardware automatically inserts waitcnt before barrier"
428>;
429
430def FeatureCodeObjectV3 : SubtargetFeature <
431  "code-object-v3",
432  "CodeObjectV3",
433  "true",
434  "Generate code object version 3"
435>;
436
437// Dummy feature used to disable assembler instructions.
438def FeatureDisable : SubtargetFeature<"",
439  "FeatureDisable","true",
440  "Dummy feature to disable assembler instructions"
441>;
442
443class SubtargetFeatureGeneration <string Value,
444                                  list<SubtargetFeature> Implies> :
445        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
446                          Value#" GPU generation", Implies>;
447
448def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
449def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
450def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
451
452def FeatureR600 : SubtargetFeatureGeneration<"R600",
453  [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
454>;
455
456def FeatureR700 : SubtargetFeatureGeneration<"R700",
457  [FeatureFetchLimit16, FeatureLocalMemorySize0]
458>;
459
460def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
461  [FeatureFetchLimit16, FeatureLocalMemorySize32768]
462>;
463
464def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
465  [FeatureFetchLimit16, FeatureWavefrontSize64,
466   FeatureLocalMemorySize32768]
467>;
468
469def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
470  [FeatureFP64, FeatureLocalMemorySize32768,
471  FeatureWavefrontSize64, FeatureGCN,
472  FeatureLDSBankCount32, FeatureMovrel]
473>;
474
475def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
476  [FeatureFP64, FeatureLocalMemorySize65536,
477  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
478  FeatureCIInsts, FeatureMovrel]
479>;
480
481def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
482  [FeatureFP64, FeatureLocalMemorySize65536,
483   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
484   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
485   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
486   FeatureScalarStores, FeatureInv2PiInlineImm,
487   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
488   FeatureIntClamp
489  ]
490>;
491
492def FeatureGFX9 : SubtargetFeatureGeneration<"GFX9",
493  [FeatureFP64, FeatureLocalMemorySize65536,
494   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
495   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
496   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
497   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
498   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
499   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
500   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
501   FeatureAddNoCarryInsts
502  ]
503>;
504
505class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
506                                  list<SubtargetFeature> Implies>
507                                 : SubtargetFeature <
508  "isaver"#Major#"."#Minor#"."#Stepping,
509  "IsaVersion",
510  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
511  "Instruction set version number",
512  Implies
513>;
514
515def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
516  [FeatureSouthernIslands,
517   FeatureFastFMAF32,
518   HalfRate64Ops,
519   FeatureLDSBankCount32]>;
520
521def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
522  [FeatureSouthernIslands,
523   FeatureLDSBankCount32]>;
524
525def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
526  [FeatureSeaIslands,
527   FeatureLDSBankCount32]>;
528
529def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
530  [FeatureSeaIslands,
531   HalfRate64Ops,
532   FeatureLDSBankCount32,
533   FeatureFastFMAF32]>;
534
535def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
536  [FeatureSeaIslands,
537   FeatureLDSBankCount16]>;
538
539def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
540  [FeatureSeaIslands,
541   FeatureLDSBankCount16]>;
542
543def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
544  [FeatureSeaIslands,
545   FeatureLDSBankCount32]>;
546
547def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0,
548  [FeatureVolcanicIslands,
549   FeatureLDSBankCount32,
550   FeatureSGPRInitBug]>;
551
552def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
553  [FeatureVolcanicIslands,
554   FeatureFastFMAF32,
555   HalfRate64Ops,
556   FeatureLDSBankCount32,
557   FeatureXNACK]>;
558
559def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
560  [FeatureVolcanicIslands,
561   FeatureLDSBankCount32,
562   FeatureSGPRInitBug]>;
563
564def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
565  [FeatureVolcanicIslands,
566   FeatureLDSBankCount32]>;
567
568def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
569  [FeatureVolcanicIslands,
570   FeatureLDSBankCount16,
571   FeatureXNACK]>;
572
573def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
574  [FeatureGFX9,
575   FeatureMadMixInsts,
576   FeatureLDSBankCount32
577   ]>;
578
579def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
580  [FeatureGFX9,
581   FeatureMadMixInsts,
582   FeatureLDSBankCount32
583   ]>;
584
585//===----------------------------------------------------------------------===//
586// Debugger related subtarget features.
587//===----------------------------------------------------------------------===//
588
589def FeatureDebuggerInsertNops : SubtargetFeature<
590  "amdgpu-debugger-insert-nops",
591  "DebuggerInsertNops",
592  "true",
593  "Insert one nop instruction for each high level source statement"
594>;
595
596def FeatureDebuggerReserveRegs : SubtargetFeature<
597  "amdgpu-debugger-reserve-regs",
598  "DebuggerReserveRegs",
599  "true",
600  "Reserve registers for debugger usage"
601>;
602
603def FeatureDebuggerEmitPrologue : SubtargetFeature<
604  "amdgpu-debugger-emit-prologue",
605  "DebuggerEmitPrologue",
606  "true",
607  "Emit debugger prologue"
608>;
609
610//===----------------------------------------------------------------------===//
611
612def AMDGPUInstrInfo : InstrInfo {
613  let guessInstructionProperties = 1;
614  let noNamedPositionallyEncodedOperands = 1;
615}
616
617def AMDGPUAsmParser : AsmParser {
618  // Some of the R600 registers have the same name, so this crashes.
619  // For example T0_XYZW and T0_XY both have the asm name T0.
620  let ShouldEmitMatchRegisterName = 0;
621}
622
623def AMDGPUAsmWriter : AsmWriter {
624  int PassSubtarget = 1;
625}
626
627def AMDGPUAsmVariants {
628  string Default = "Default";
629  int Default_ID = 0;
630  string VOP3 = "VOP3";
631  int VOP3_ID = 1;
632  string SDWA = "SDWA";
633  int SDWA_ID = 2;
634  string SDWA9 = "SDWA9";
635  int SDWA9_ID = 3;
636  string DPP = "DPP";
637  int DPP_ID = 4;
638  string Disable = "Disable";
639  int Disable_ID = 5;
640}
641
642def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
643  let Variant = AMDGPUAsmVariants.Default_ID;
644  let Name = AMDGPUAsmVariants.Default;
645}
646
647def VOP3AsmParserVariant : AsmParserVariant {
648  let Variant = AMDGPUAsmVariants.VOP3_ID;
649  let Name = AMDGPUAsmVariants.VOP3;
650}
651
652def SDWAAsmParserVariant : AsmParserVariant {
653  let Variant = AMDGPUAsmVariants.SDWA_ID;
654  let Name = AMDGPUAsmVariants.SDWA;
655}
656
657def SDWA9AsmParserVariant : AsmParserVariant {
658  let Variant = AMDGPUAsmVariants.SDWA9_ID;
659  let Name = AMDGPUAsmVariants.SDWA9;
660}
661
662
663def DPPAsmParserVariant : AsmParserVariant {
664  let Variant = AMDGPUAsmVariants.DPP_ID;
665  let Name = AMDGPUAsmVariants.DPP;
666}
667
668def AMDGPU : Target {
669  // Pull in Instruction Info:
670  let InstructionSet = AMDGPUInstrInfo;
671  let AssemblyParsers = [AMDGPUAsmParser];
672  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
673                                VOP3AsmParserVariant,
674                                SDWAAsmParserVariant,
675                                SDWA9AsmParserVariant,
676                                DPPAsmParserVariant];
677  let AssemblyWriters = [AMDGPUAsmWriter];
678}
679
680// Dummy Instruction itineraries for pseudo instructions
681def ALU_NULL : FuncUnit;
682def NullALU : InstrItinClass;
683
684//===----------------------------------------------------------------------===//
685// Predicate helper class
686//===----------------------------------------------------------------------===//
687
688def TruePredicate : Predicate<"true">;
689
690def isSICI : Predicate<
691  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
692  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
693>, AssemblerPredicate<"!FeatureGCN3Encoding">;
694
695def isVI : Predicate <
696  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
697  AssemblerPredicate<"FeatureGCN3Encoding">;
698
699def isGFX9 : Predicate <
700  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
701  AssemblerPredicate<"FeatureGFX9Insts">;
702
703// TODO: Either the name to be changed or we simply use IsCI!
704def isCIVI : Predicate <
705  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
706  AssemblerPredicate<"FeatureCIInsts">;
707
708def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
709  AssemblerPredicate<"FeatureFlatAddressSpace">;
710
711def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
712  AssemblerPredicate<"FeatureFlatGlobalInsts">;
713def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
714  AssemblerPredicate<"FeatureFlatScratchInsts">;
715def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
716  AssemblerPredicate<"FeatureGFX9Insts">;
717
718
719def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
720def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
721
722def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
723  AssemblerPredicate<"FeatureGFX9Insts">;
724
725def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarryInsts()">,
726  AssemblerPredicate<"FeatureAddNoCarryInsts">;
727
728def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarryInsts()">,
729  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
730
731def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
732  AssemblerPredicate<"Feature16BitInsts">;
733def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
734  AssemblerPredicate<"FeatureVOP3P">;
735
736def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
737  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
738
739def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
740  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
741
742def HasDPP : Predicate<"Subtarget->hasDPP()">,
743  AssemblerPredicate<"FeatureDPP">;
744
745def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
746  AssemblerPredicate<"FeatureIntClamp">;
747
748def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
749  AssemblerPredicate<"FeatureMadMixInsts">;
750
751def EnableLateCFGStructurize : Predicate<
752  "EnableLateStructurizeCFG">;
753
754// Exists to help track down where SubtargetPredicate isn't set rather
755// than letting tablegen crash with an unhelpful error.
756def InvalidPred : Predicate<"predicate not set on instruction or pattern">;
757
758class PredicateControl {
759  Predicate SubtargetPredicate = InvalidPred;
760  Predicate SIAssemblerPredicate = isSICI;
761  Predicate VIAssemblerPredicate = isVI;
762  list<Predicate> AssemblerPredicates = [];
763  Predicate AssemblerPredicate = TruePredicate;
764  list<Predicate> OtherPredicates = [];
765  list<Predicate> Predicates = !listconcat([SubtargetPredicate,
766                                            AssemblerPredicate],
767                                            AssemblerPredicates,
768                                            OtherPredicates);
769}
770
771class AMDGPUPat<dag pattern, dag result> : Pat<pattern, result>,
772  PredicateControl;
773
774
775// Include AMDGPU TD files
776include "R600Schedule.td"
777include "R600Processors.td"
778include "SISchedule.td"
779include "GCNProcessors.td"
780include "AMDGPUInstrInfo.td"
781include "AMDGPUIntrinsics.td"
782include "AMDGPURegisterInfo.td"
783include "AMDGPURegisterBanks.td"
784include "AMDGPUInstructions.td"
785include "AMDGPUCallingConv.td"
786