1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "llvm/Support/TargetRegistry.h" 15 #include "llvm/Target/TargetMachine.h" 16 17 namespace llvm { 18 19 class AMDGPUInstrPrinter; 20 class AMDGPUSubtarget; 21 class AMDGPUTargetMachine; 22 class FunctionPass; 23 class GCNTargetMachine; 24 struct MachineSchedContext; 25 class MCAsmInfo; 26 class raw_ostream; 27 class ScheduleDAGInstrs; 28 class Target; 29 class TargetMachine; 30 31 // R600 Passes 32 FunctionPass *createR600VectorRegMerger(TargetMachine &tm); 33 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm); 34 FunctionPass *createR600EmitClauseMarkers(); 35 FunctionPass *createR600ClauseMergePass(TargetMachine &tm); 36 FunctionPass *createR600Packetizer(TargetMachine &tm); 37 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm); 38 FunctionPass *createAMDGPUCFGStructurizerPass(); 39 40 // SI Passes 41 FunctionPass *createSITypeRewriter(); 42 FunctionPass *createSIAnnotateControlFlowPass(); 43 FunctionPass *createSIFoldOperandsPass(); 44 FunctionPass *createSILowerI1CopiesPass(); 45 FunctionPass *createSIShrinkInstructionsPass(); 46 FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm); 47 FunctionPass *createSIWholeQuadModePass(); 48 FunctionPass *createSILowerControlFlowPass(); 49 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 50 FunctionPass *createSIFixSGPRCopiesPass(); 51 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); 52 FunctionPass *createSIDebuggerInsertNopsPass(); 53 FunctionPass *createSIInsertWaitsPass(); 54 FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr); 55 56 ScheduleDAGInstrs *createSIMachineScheduler(MachineSchedContext *C); 57 58 ModulePass *createAMDGPUAnnotateKernelFeaturesPass(); 59 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 60 extern char &AMDGPUAnnotateKernelFeaturesID; 61 62 void initializeSIFoldOperandsPass(PassRegistry &); 63 extern char &SIFoldOperandsID; 64 65 void initializeSIShrinkInstructionsPass(PassRegistry&); 66 extern char &SIShrinkInstructionsID; 67 68 void initializeSIFixSGPRCopiesPass(PassRegistry &); 69 extern char &SIFixSGPRCopiesID; 70 71 void initializeSILowerI1CopiesPass(PassRegistry &); 72 extern char &SILowerI1CopiesID; 73 74 void initializeSILoadStoreOptimizerPass(PassRegistry &); 75 extern char &SILoadStoreOptimizerID; 76 77 void initializeSIWholeQuadModePass(PassRegistry &); 78 extern char &SIWholeQuadModeID; 79 80 void initializeSILowerControlFlowPass(PassRegistry &); 81 extern char &SILowerControlFlowPassID; 82 83 84 // Passes common to R600 and SI 85 FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr); 86 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 87 extern char &AMDGPUPromoteAllocaID; 88 89 FunctionPass *createAMDGPUAddDivergenceMetadata(const AMDGPUSubtarget &ST); 90 Pass *createAMDGPUStructurizeCFGPass(); 91 FunctionPass *createAMDGPUISelDag(TargetMachine &tm); 92 ModulePass *createAMDGPUAlwaysInlinePass(); 93 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass(); 94 FunctionPass *createAMDGPUAnnotateUniformValues(); 95 96 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&); 97 extern char &SIFixControlFlowLiveIntervalsID; 98 99 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 100 extern char &AMDGPUAnnotateUniformValuesPassID; 101 102 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 103 extern char &AMDGPUCodeGenPrepareID; 104 105 void initializeSIAnnotateControlFlowPass(PassRegistry&); 106 extern char &SIAnnotateControlFlowPassID; 107 108 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 109 extern char &SIDebuggerInsertNopsID; 110 111 void initializeSIInsertWaitsPass(PassRegistry&); 112 extern char &SIInsertWaitsID; 113 114 extern Target TheAMDGPUTarget; 115 extern Target TheGCNTarget; 116 117 namespace AMDGPU { 118 enum TargetIndex { 119 TI_CONSTDATA_START, 120 TI_SCRATCH_RSRC_DWORD0, 121 TI_SCRATCH_RSRC_DWORD1, 122 TI_SCRATCH_RSRC_DWORD2, 123 TI_SCRATCH_RSRC_DWORD3 124 }; 125 } 126 127 } // End namespace llvm 128 129 /// OpenCL uses address spaces to differentiate between 130 /// various memory regions on the hardware. On the CPU 131 /// all of the address spaces point to the same memory, 132 /// however on the GPU, each address space points to 133 /// a separate piece of memory that is unique from other 134 /// memory locations. 135 namespace AMDGPUAS { 136 enum AddressSpaces : unsigned { 137 PRIVATE_ADDRESS = 0, ///< Address space for private memory. 138 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 139 CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2) 140 LOCAL_ADDRESS = 3, ///< Address space for local memory. 141 FLAT_ADDRESS = 4, ///< Address space for flat memory. 142 REGION_ADDRESS = 5, ///< Address space for region memory. 143 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0) 144 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1) 145 146 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this 147 // order to be able to dynamically index a constant buffer, for example: 148 // 149 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 150 151 CONSTANT_BUFFER_0 = 8, 152 CONSTANT_BUFFER_1 = 9, 153 CONSTANT_BUFFER_2 = 10, 154 CONSTANT_BUFFER_3 = 11, 155 CONSTANT_BUFFER_4 = 12, 156 CONSTANT_BUFFER_5 = 13, 157 CONSTANT_BUFFER_6 = 14, 158 CONSTANT_BUFFER_7 = 15, 159 CONSTANT_BUFFER_8 = 16, 160 CONSTANT_BUFFER_9 = 17, 161 CONSTANT_BUFFER_10 = 18, 162 CONSTANT_BUFFER_11 = 19, 163 CONSTANT_BUFFER_12 = 20, 164 CONSTANT_BUFFER_13 = 21, 165 CONSTANT_BUFFER_14 = 22, 166 CONSTANT_BUFFER_15 = 23, 167 168 // Some places use this if the address space can't be determined. 169 UNKNOWN_ADDRESS_SPACE = ~0u 170 }; 171 172 } // namespace AMDGPUAS 173 174 #endif 175