1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 12 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H 13 14 #include "llvm/Target/TargetMachine.h" 15 16 namespace llvm { 17 18 class AMDGPUTargetMachine; 19 class FunctionPass; 20 class GCNTargetMachine; 21 class ModulePass; 22 class Pass; 23 class Target; 24 class TargetMachine; 25 class TargetOptions; 26 class PassRegistry; 27 class Module; 28 29 // R600 Passes 30 FunctionPass *createR600VectorRegMerger(); 31 FunctionPass *createR600ExpandSpecialInstrsPass(); 32 FunctionPass *createR600EmitClauseMarkers(); 33 FunctionPass *createR600ClauseMergePass(); 34 FunctionPass *createR600Packetizer(); 35 FunctionPass *createR600ControlFlowFinalizer(); 36 FunctionPass *createAMDGPUCFGStructurizerPass(); 37 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel); 38 39 // SI Passes 40 FunctionPass *createGCNDPPCombinePass(); 41 FunctionPass *createSIAnnotateControlFlowPass(); 42 FunctionPass *createSIFoldOperandsPass(); 43 FunctionPass *createSIPeepholeSDWAPass(); 44 FunctionPass *createSILowerI1CopiesPass(); 45 FunctionPass *createSIFixupVectorISelPass(); 46 FunctionPass *createSIAddIMGInitPass(); 47 FunctionPass *createSIShrinkInstructionsPass(); 48 FunctionPass *createSILoadStoreOptimizerPass(); 49 FunctionPass *createSIWholeQuadModePass(); 50 FunctionPass *createSIFixControlFlowLiveIntervalsPass(); 51 FunctionPass *createSIOptimizeExecMaskingPreRAPass(); 52 FunctionPass *createSIFixSGPRCopiesPass(); 53 FunctionPass *createSIMemoryLegalizerPass(); 54 FunctionPass *createSIDebuggerInsertNopsPass(); 55 FunctionPass *createSIInsertWaitcntsPass(); 56 FunctionPass *createSIFixWWMLivenessPass(); 57 FunctionPass *createSIFormMemoryClausesPass(); 58 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &); 59 FunctionPass *createAMDGPUUseNativeCallsPass(); 60 FunctionPass *createAMDGPUCodeGenPreparePass(); 61 FunctionPass *createAMDGPUMachineCFGStructurizerPass(); 62 FunctionPass *createAMDGPURewriteOutArgumentsPass(); 63 FunctionPass *createSIModeRegisterPass(); 64 65 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&); 66 67 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&); 68 extern char &AMDGPUMachineCFGStructurizerID; 69 70 void initializeAMDGPUAlwaysInlinePass(PassRegistry&); 71 72 Pass *createAMDGPUAnnotateKernelFeaturesPass(); 73 void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &); 74 extern char &AMDGPUAnnotateKernelFeaturesID; 75 76 FunctionPass *createAMDGPUAtomicOptimizerPass(); 77 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &); 78 extern char &AMDGPUAtomicOptimizerID; 79 80 ModulePass *createAMDGPULowerIntrinsicsPass(); 81 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &); 82 extern char &AMDGPULowerIntrinsicsID; 83 84 ModulePass *createAMDGPUFixFunctionBitcastsPass(); 85 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &); 86 extern char &AMDGPUFixFunctionBitcastsID; 87 88 FunctionPass *createAMDGPULowerKernelArgumentsPass(); 89 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &); 90 extern char &AMDGPULowerKernelArgumentsID; 91 92 ModulePass *createAMDGPULowerKernelAttributesPass(); 93 void initializeAMDGPULowerKernelAttributesPass(PassRegistry &); 94 extern char &AMDGPULowerKernelAttributesID; 95 96 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &); 97 extern char &AMDGPURewriteOutArgumentsID; 98 99 void initializeGCNDPPCombinePass(PassRegistry &); 100 extern char &GCNDPPCombineID; 101 102 void initializeR600ClauseMergePassPass(PassRegistry &); 103 extern char &R600ClauseMergePassID; 104 105 void initializeR600ControlFlowFinalizerPass(PassRegistry &); 106 extern char &R600ControlFlowFinalizerID; 107 108 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &); 109 extern char &R600ExpandSpecialInstrsPassID; 110 111 void initializeR600VectorRegMergerPass(PassRegistry &); 112 extern char &R600VectorRegMergerID; 113 114 void initializeR600PacketizerPass(PassRegistry &); 115 extern char &R600PacketizerID; 116 117 void initializeSIFoldOperandsPass(PassRegistry &); 118 extern char &SIFoldOperandsID; 119 120 void initializeSIPeepholeSDWAPass(PassRegistry &); 121 extern char &SIPeepholeSDWAID; 122 123 void initializeSIShrinkInstructionsPass(PassRegistry&); 124 extern char &SIShrinkInstructionsID; 125 126 void initializeSIFixSGPRCopiesPass(PassRegistry &); 127 extern char &SIFixSGPRCopiesID; 128 129 void initializeSIFixVGPRCopiesPass(PassRegistry &); 130 extern char &SIFixVGPRCopiesID; 131 132 void initializeSIFixupVectorISelPass(PassRegistry &); 133 extern char &SIFixupVectorISelID; 134 135 void initializeSILowerI1CopiesPass(PassRegistry &); 136 extern char &SILowerI1CopiesID; 137 138 void initializeSILoadStoreOptimizerPass(PassRegistry &); 139 extern char &SILoadStoreOptimizerID; 140 141 void initializeSIWholeQuadModePass(PassRegistry &); 142 extern char &SIWholeQuadModeID; 143 144 void initializeSILowerControlFlowPass(PassRegistry &); 145 extern char &SILowerControlFlowID; 146 147 void initializeSIInsertSkipsPass(PassRegistry &); 148 extern char &SIInsertSkipsPassID; 149 150 void initializeSIOptimizeExecMaskingPass(PassRegistry &); 151 extern char &SIOptimizeExecMaskingID; 152 153 void initializeSIFixWWMLivenessPass(PassRegistry &); 154 extern char &SIFixWWMLivenessID; 155 156 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &); 157 extern char &AMDGPUSimplifyLibCallsID; 158 159 void initializeAMDGPUUseNativeCallsPass(PassRegistry &); 160 extern char &AMDGPUUseNativeCallsID; 161 162 void initializeSIAddIMGInitPass(PassRegistry &); 163 extern char &SIAddIMGInitID; 164 165 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &); 166 extern char &AMDGPUPerfHintAnalysisID; 167 168 // Passes common to R600 and SI 169 FunctionPass *createAMDGPUPromoteAlloca(); 170 void initializeAMDGPUPromoteAllocaPass(PassRegistry&); 171 extern char &AMDGPUPromoteAllocaID; 172 173 Pass *createAMDGPUStructurizeCFGPass(); 174 FunctionPass *createAMDGPUISelDag( 175 TargetMachine *TM = nullptr, 176 CodeGenOpt::Level OptLevel = CodeGenOpt::Default); 177 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true); 178 ModulePass *createR600OpenCLImageTypeLoweringPass(); 179 FunctionPass *createAMDGPUAnnotateUniformValues(); 180 181 ModulePass* createAMDGPUUnifyMetadataPass(); 182 void initializeAMDGPUUnifyMetadataPass(PassRegistry&); 183 extern char &AMDGPUUnifyMetadataID; 184 185 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&); 186 extern char &SIOptimizeExecMaskingPreRAID; 187 188 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&); 189 extern char &AMDGPUAnnotateUniformValuesPassID; 190 191 void initializeAMDGPUCodeGenPreparePass(PassRegistry&); 192 extern char &AMDGPUCodeGenPrepareID; 193 194 void initializeSIAnnotateControlFlowPass(PassRegistry&); 195 extern char &SIAnnotateControlFlowPassID; 196 197 void initializeSIMemoryLegalizerPass(PassRegistry&); 198 extern char &SIMemoryLegalizerID; 199 200 void initializeSIDebuggerInsertNopsPass(PassRegistry&); 201 extern char &SIDebuggerInsertNopsID; 202 203 void initializeSIModeRegisterPass(PassRegistry&); 204 extern char &SIModeRegisterID; 205 206 void initializeSIInsertWaitcntsPass(PassRegistry&); 207 extern char &SIInsertWaitcntsID; 208 209 void initializeSIFormMemoryClausesPass(PassRegistry&); 210 extern char &SIFormMemoryClausesID; 211 212 void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&); 213 extern char &AMDGPUUnifyDivergentExitNodesID; 214 215 ImmutablePass *createAMDGPUAAWrapperPass(); 216 void initializeAMDGPUAAWrapperPassPass(PassRegistry&); 217 ImmutablePass *createAMDGPUExternalAAWrapperPass(); 218 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&); 219 220 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &); 221 222 Pass *createAMDGPUFunctionInliningPass(); 223 void initializeAMDGPUInlinerPass(PassRegistry&); 224 225 ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass(); 226 void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &); 227 extern char &AMDGPUOpenCLEnqueuedBlockLoweringID; 228 229 Target &getTheAMDGPUTarget(); 230 Target &getTheGCNTarget(); 231 232 namespace AMDGPU { 233 enum TargetIndex { 234 TI_CONSTDATA_START, 235 TI_SCRATCH_RSRC_DWORD0, 236 TI_SCRATCH_RSRC_DWORD1, 237 TI_SCRATCH_RSRC_DWORD2, 238 TI_SCRATCH_RSRC_DWORD3 239 }; 240 } 241 242 } // End namespace llvm 243 244 /// OpenCL uses address spaces to differentiate between 245 /// various memory regions on the hardware. On the CPU 246 /// all of the address spaces point to the same memory, 247 /// however on the GPU, each address space points to 248 /// a separate piece of memory that is unique from other 249 /// memory locations. 250 namespace AMDGPUAS { 251 enum : unsigned { 252 // The maximum value for flat, generic, local, private, constant and region. 253 MAX_AMDGPU_ADDRESS = 6, 254 255 FLAT_ADDRESS = 0, ///< Address space for flat memory. 256 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). 257 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS) 258 259 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2) 260 LOCAL_ADDRESS = 3, ///< Address space for local memory. 261 PRIVATE_ADDRESS = 5, ///< Address space for private memory. 262 263 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory 264 265 /// Address space for direct addressible parameter memory (CONST0) 266 PARAM_D_ADDRESS = 6, 267 /// Address space for indirect addressible parameter memory (VTX1) 268 PARAM_I_ADDRESS = 7, 269 270 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on 271 // this order to be able to dynamically index a constant buffer, for 272 // example: 273 // 274 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx 275 276 CONSTANT_BUFFER_0 = 8, 277 CONSTANT_BUFFER_1 = 9, 278 CONSTANT_BUFFER_2 = 10, 279 CONSTANT_BUFFER_3 = 11, 280 CONSTANT_BUFFER_4 = 12, 281 CONSTANT_BUFFER_5 = 13, 282 CONSTANT_BUFFER_6 = 14, 283 CONSTANT_BUFFER_7 = 15, 284 CONSTANT_BUFFER_8 = 16, 285 CONSTANT_BUFFER_9 = 17, 286 CONSTANT_BUFFER_10 = 18, 287 CONSTANT_BUFFER_11 = 19, 288 CONSTANT_BUFFER_12 = 20, 289 CONSTANT_BUFFER_13 = 21, 290 CONSTANT_BUFFER_14 = 22, 291 CONSTANT_BUFFER_15 = 23, 292 293 // Some places use this if the address space can't be determined. 294 UNKNOWN_ADDRESS_SPACE = ~0u, 295 }; 296 } 297 298 #endif 299