1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides basic encoding and assembly information for AArch64.
11 //
12 //===----------------------------------------------------------------------===//
13 #include "AArch64BaseInfo.h"
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/Support/Regex.h"
18 
19 using namespace llvm;
20 
21 namespace llvm {
22   namespace AArch64AT {
23 #define GET_AT_IMPL
24 #include "AArch64GenSystemOperands.inc"
25   }
26 }
27 
28 
29 namespace llvm {
30   namespace AArch64DB {
31 #define GET_DB_IMPL
32 #include "AArch64GenSystemOperands.inc"
33   }
34 }
35 
36 namespace llvm {
37   namespace AArch64DC {
38 #define GET_DC_IMPL
39 #include "AArch64GenSystemOperands.inc"
40   }
41 }
42 
43 namespace llvm {
44   namespace AArch64IC {
45 #define GET_IC_IMPL
46 #include "AArch64GenSystemOperands.inc"
47   }
48 }
49 
50 namespace llvm {
51   namespace AArch64ISB {
52 #define GET_ISB_IMPL
53 #include "AArch64GenSystemOperands.inc"
54   }
55 }
56 
57 namespace llvm {
58   namespace AArch64TSB {
59 #define GET_TSB_IMPL
60 #include "AArch64GenSystemOperands.inc"
61   }
62 }
63 
64 namespace llvm {
65   namespace AArch64PRFM {
66 #define GET_PRFM_IMPL
67 #include "AArch64GenSystemOperands.inc"
68   }
69 }
70 
71 namespace llvm {
72   namespace AArch64SVEPRFM {
73 #define GET_SVEPRFM_IMPL
74 #include "AArch64GenSystemOperands.inc"
75   }
76 }
77 
78 namespace llvm {
79   namespace AArch64SVEPredPattern {
80 #define GET_SVEPREDPAT_IMPL
81 #include "AArch64GenSystemOperands.inc"
82   }
83 }
84 
85 namespace llvm {
86   namespace AArch64ExactFPImm {
87 #define GET_EXACTFPIMM_IMPL
88 #include "AArch64GenSystemOperands.inc"
89   }
90 }
91 
92 namespace llvm {
93   namespace AArch64PState {
94 #define GET_PSTATE_IMPL
95 #include "AArch64GenSystemOperands.inc"
96   }
97 }
98 
99 namespace llvm {
100   namespace AArch64PSBHint {
101 #define GET_PSB_IMPL
102 #include "AArch64GenSystemOperands.inc"
103   }
104 }
105 
106 namespace llvm {
107   namespace AArch64SysReg {
108 #define GET_SYSREG_IMPL
109 #include "AArch64GenSystemOperands.inc"
110   }
111 }
112 
113 uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) {
114   // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
115   Regex GenericRegPattern("^S([0-3])_([0-7])_C([0-9]|1[0-5])_C([0-9]|1[0-5])_([0-7])$");
116 
117   std::string UpperName = Name.upper();
118   SmallVector<StringRef, 5> Ops;
119   if (!GenericRegPattern.match(UpperName, &Ops))
120     return -1;
121 
122   uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
123   uint32_t Bits;
124   Ops[1].getAsInteger(10, Op0);
125   Ops[2].getAsInteger(10, Op1);
126   Ops[3].getAsInteger(10, CRn);
127   Ops[4].getAsInteger(10, CRm);
128   Ops[5].getAsInteger(10, Op2);
129   Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
130 
131   return Bits;
132 }
133 
134 std::string AArch64SysReg::genericRegisterString(uint32_t Bits) {
135   assert(Bits < 0x10000);
136   uint32_t Op0 = (Bits >> 14) & 0x3;
137   uint32_t Op1 = (Bits >> 11) & 0x7;
138   uint32_t CRn = (Bits >> 7) & 0xf;
139   uint32_t CRm = (Bits >> 3) & 0xf;
140   uint32_t Op2 = Bits & 0x7;
141 
142   return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" +
143          utostr(CRm) + "_" + utostr(Op2);
144 }
145 
146 namespace llvm {
147   namespace AArch64TLBI {
148 #define GET_TLBI_IMPL
149 #include "AArch64GenSystemOperands.inc"
150   }
151 }
152