1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "AArch64.h" 11 #include "AArch64RegisterInfo.h" 12 #include "MCTargetDesc/AArch64FixupKinds.h" 13 #include "llvm/ADT/Triple.h" 14 #include "llvm/BinaryFormat/MachO.h" 15 #include "llvm/MC/MCAsmBackend.h" 16 #include "llvm/MC/MCAssembler.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCDirectives.h" 19 #include "llvm/MC/MCELFObjectWriter.h" 20 #include "llvm/MC/MCFixupKindInfo.h" 21 #include "llvm/MC/MCObjectWriter.h" 22 #include "llvm/MC/MCSectionELF.h" 23 #include "llvm/MC/MCSectionMachO.h" 24 #include "llvm/MC/MCValue.h" 25 #include "llvm/Support/ErrorHandling.h" 26 using namespace llvm; 27 28 namespace { 29 30 class AArch64AsmBackend : public MCAsmBackend { 31 static const unsigned PCRelFlagVal = 32 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel; 33 public: 34 bool IsLittleEndian; 35 36 public: 37 AArch64AsmBackend(const Target &T, bool IsLittleEndian) 38 : MCAsmBackend(), IsLittleEndian(IsLittleEndian) {} 39 40 unsigned getNumFixupKinds() const override { 41 return AArch64::NumTargetFixupKinds; 42 } 43 44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 45 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = { 46 // This table *must* be in the order that the fixup_* kinds are defined 47 // in AArch64FixupKinds.h. 48 // 49 // Name Offset (bits) Size (bits) Flags 50 {"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal}, 51 {"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal}, 52 {"fixup_aarch64_add_imm12", 10, 12, 0}, 53 {"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0}, 54 {"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0}, 55 {"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0}, 56 {"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0}, 57 {"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0}, 58 {"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal}, 59 {"fixup_aarch64_movw", 5, 16, 0}, 60 {"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal}, 61 {"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal}, 62 {"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal}, 63 {"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal}, 64 {"fixup_aarch64_tlsdesc_call", 0, 0, 0}}; 65 66 if (Kind < FirstTargetFixupKind) 67 return MCAsmBackend::getFixupKindInfo(Kind); 68 69 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 70 "Invalid kind!"); 71 return Infos[Kind - FirstTargetFixupKind]; 72 } 73 74 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 75 const MCValue &Target, MutableArrayRef<char> Data, 76 uint64_t Value, bool IsResolved) const override; 77 78 bool mayNeedRelaxation(const MCInst &Inst) const override; 79 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 80 const MCRelaxableFragment *DF, 81 const MCAsmLayout &Layout) const override; 82 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 83 MCInst &Res) const override; 84 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; 85 86 void HandleAssemblerFlag(MCAssemblerFlag Flag) {} 87 88 unsigned getPointerSize() const { return 8; } 89 90 unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const; 91 }; 92 93 } // end anonymous namespace 94 95 /// \brief The number of bytes the fixup may change. 96 static unsigned getFixupKindNumBytes(unsigned Kind) { 97 switch (Kind) { 98 default: 99 llvm_unreachable("Unknown fixup kind!"); 100 101 case AArch64::fixup_aarch64_tlsdesc_call: 102 return 0; 103 104 case FK_Data_1: 105 return 1; 106 107 case AArch64::fixup_aarch64_movw: 108 case FK_Data_2: 109 case FK_SecRel_2: 110 return 2; 111 112 case AArch64::fixup_aarch64_pcrel_branch14: 113 case AArch64::fixup_aarch64_add_imm12: 114 case AArch64::fixup_aarch64_ldst_imm12_scale1: 115 case AArch64::fixup_aarch64_ldst_imm12_scale2: 116 case AArch64::fixup_aarch64_ldst_imm12_scale4: 117 case AArch64::fixup_aarch64_ldst_imm12_scale8: 118 case AArch64::fixup_aarch64_ldst_imm12_scale16: 119 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 120 case AArch64::fixup_aarch64_pcrel_branch19: 121 return 3; 122 123 case AArch64::fixup_aarch64_pcrel_adr_imm21: 124 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 125 case AArch64::fixup_aarch64_pcrel_branch26: 126 case AArch64::fixup_aarch64_pcrel_call26: 127 case FK_Data_4: 128 case FK_SecRel_4: 129 return 4; 130 131 case FK_Data_8: 132 return 8; 133 } 134 } 135 136 static unsigned AdrImmBits(unsigned Value) { 137 unsigned lo2 = Value & 0x3; 138 unsigned hi19 = (Value & 0x1ffffc) >> 2; 139 return (hi19 << 5) | (lo2 << 29); 140 } 141 142 static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, 143 MCContext &Ctx) { 144 unsigned Kind = Fixup.getKind(); 145 int64_t SignedValue = static_cast<int64_t>(Value); 146 switch (Kind) { 147 default: 148 llvm_unreachable("Unknown fixup kind!"); 149 case AArch64::fixup_aarch64_pcrel_adr_imm21: 150 if (SignedValue > 2097151 || SignedValue < -2097152) 151 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 152 return AdrImmBits(Value & 0x1fffffULL); 153 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 154 return AdrImmBits((Value & 0x1fffff000ULL) >> 12); 155 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 156 case AArch64::fixup_aarch64_pcrel_branch19: 157 // Signed 21-bit immediate 158 if (SignedValue > 2097151 || SignedValue < -2097152) 159 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 160 if (Value & 0x3) 161 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 162 // Low two bits are not encoded. 163 return (Value >> 2) & 0x7ffff; 164 case AArch64::fixup_aarch64_add_imm12: 165 case AArch64::fixup_aarch64_ldst_imm12_scale1: 166 // Unsigned 12-bit immediate 167 if (Value >= 0x1000) 168 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 169 return Value; 170 case AArch64::fixup_aarch64_ldst_imm12_scale2: 171 // Unsigned 12-bit immediate which gets multiplied by 2 172 if (Value >= 0x2000) 173 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 174 if (Value & 0x1) 175 Ctx.reportError(Fixup.getLoc(), "fixup must be 2-byte aligned"); 176 return Value >> 1; 177 case AArch64::fixup_aarch64_ldst_imm12_scale4: 178 // Unsigned 12-bit immediate which gets multiplied by 4 179 if (Value >= 0x4000) 180 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 181 if (Value & 0x3) 182 Ctx.reportError(Fixup.getLoc(), "fixup must be 4-byte aligned"); 183 return Value >> 2; 184 case AArch64::fixup_aarch64_ldst_imm12_scale8: 185 // Unsigned 12-bit immediate which gets multiplied by 8 186 if (Value >= 0x8000) 187 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 188 if (Value & 0x7) 189 Ctx.reportError(Fixup.getLoc(), "fixup must be 8-byte aligned"); 190 return Value >> 3; 191 case AArch64::fixup_aarch64_ldst_imm12_scale16: 192 // Unsigned 12-bit immediate which gets multiplied by 16 193 if (Value >= 0x10000) 194 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 195 if (Value & 0xf) 196 Ctx.reportError(Fixup.getLoc(), "fixup must be 16-byte aligned"); 197 return Value >> 4; 198 case AArch64::fixup_aarch64_movw: 199 Ctx.reportError(Fixup.getLoc(), 200 "no resolvable MOVZ/MOVK fixups supported yet"); 201 return Value; 202 case AArch64::fixup_aarch64_pcrel_branch14: 203 // Signed 16-bit immediate 204 if (SignedValue > 32767 || SignedValue < -32768) 205 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 206 // Low two bits are not encoded (4-byte alignment assumed). 207 if (Value & 0x3) 208 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 209 return (Value >> 2) & 0x3fff; 210 case AArch64::fixup_aarch64_pcrel_branch26: 211 case AArch64::fixup_aarch64_pcrel_call26: 212 // Signed 28-bit immediate 213 if (SignedValue > 134217727 || SignedValue < -134217728) 214 Ctx.reportError(Fixup.getLoc(), "fixup value out of range"); 215 // Low two bits are not encoded (4-byte alignment assumed). 216 if (Value & 0x3) 217 Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned"); 218 return (Value >> 2) & 0x3ffffff; 219 case FK_Data_1: 220 case FK_Data_2: 221 case FK_Data_4: 222 case FK_Data_8: 223 case FK_SecRel_2: 224 case FK_SecRel_4: 225 return Value; 226 } 227 } 228 229 /// getFixupKindContainereSizeInBytes - The number of bytes of the 230 /// container involved in big endian or 0 if the item is little endian 231 unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const { 232 if (IsLittleEndian) 233 return 0; 234 235 switch (Kind) { 236 default: 237 llvm_unreachable("Unknown fixup kind!"); 238 239 case FK_Data_1: 240 return 1; 241 case FK_Data_2: 242 return 2; 243 case FK_Data_4: 244 return 4; 245 case FK_Data_8: 246 return 8; 247 248 case AArch64::fixup_aarch64_tlsdesc_call: 249 case AArch64::fixup_aarch64_movw: 250 case AArch64::fixup_aarch64_pcrel_branch14: 251 case AArch64::fixup_aarch64_add_imm12: 252 case AArch64::fixup_aarch64_ldst_imm12_scale1: 253 case AArch64::fixup_aarch64_ldst_imm12_scale2: 254 case AArch64::fixup_aarch64_ldst_imm12_scale4: 255 case AArch64::fixup_aarch64_ldst_imm12_scale8: 256 case AArch64::fixup_aarch64_ldst_imm12_scale16: 257 case AArch64::fixup_aarch64_ldr_pcrel_imm19: 258 case AArch64::fixup_aarch64_pcrel_branch19: 259 case AArch64::fixup_aarch64_pcrel_adr_imm21: 260 case AArch64::fixup_aarch64_pcrel_adrp_imm21: 261 case AArch64::fixup_aarch64_pcrel_branch26: 262 case AArch64::fixup_aarch64_pcrel_call26: 263 // Instructions are always little endian 264 return 0; 265 } 266 } 267 268 void AArch64AsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 269 const MCValue &Target, 270 MutableArrayRef<char> Data, uint64_t Value, 271 bool IsResolved) const { 272 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 273 if (!Value) 274 return; // Doesn't change encoding. 275 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); 276 MCContext &Ctx = Asm.getContext(); 277 // Apply any target-specific value adjustments. 278 Value = adjustFixupValue(Fixup, Value, Ctx); 279 280 // Shift the value into position. 281 Value <<= Info.TargetOffset; 282 283 unsigned Offset = Fixup.getOffset(); 284 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); 285 286 // Used to point to big endian bytes. 287 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind()); 288 289 // For each byte of the fragment that the fixup touches, mask in the 290 // bits from the fixup value. 291 if (FulleSizeInBytes == 0) { 292 // Handle as little-endian 293 for (unsigned i = 0; i != NumBytes; ++i) { 294 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 295 } 296 } else { 297 // Handle as big-endian 298 assert((Offset + FulleSizeInBytes) <= Data.size() && "Invalid fixup size!"); 299 assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!"); 300 for (unsigned i = 0; i != NumBytes; ++i) { 301 unsigned Idx = FulleSizeInBytes - 1 - i; 302 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 303 } 304 } 305 } 306 307 bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 308 return false; 309 } 310 311 bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 312 uint64_t Value, 313 const MCRelaxableFragment *DF, 314 const MCAsmLayout &Layout) const { 315 // FIXME: This isn't correct for AArch64. Just moving the "generic" logic 316 // into the targets for now. 317 // 318 // Relax if the value is too big for a (signed) i8. 319 return int64_t(Value) != int64_t(int8_t(Value)); 320 } 321 322 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst, 323 const MCSubtargetInfo &STI, 324 MCInst &Res) const { 325 llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented"); 326 } 327 328 bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 329 // If the count is not 4-byte aligned, we must be writing data into the text 330 // section (otherwise we have unaligned instructions, and thus have far 331 // bigger problems), so just write zeros instead. 332 OW->WriteZeros(Count % 4); 333 334 // We are properly aligned, so write NOPs as requested. 335 Count /= 4; 336 for (uint64_t i = 0; i != Count; ++i) 337 OW->write32(0xd503201f); 338 return true; 339 } 340 341 namespace { 342 343 namespace CU { 344 345 /// \brief Compact unwind encoding values. 346 enum CompactUnwindEncodings { 347 /// \brief A "frameless" leaf function, where no non-volatile registers are 348 /// saved. The return remains in LR throughout the function. 349 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000, 350 351 /// \brief No compact unwind encoding available. Instead the low 23-bits of 352 /// the compact unwind encoding is the offset of the DWARF FDE in the 353 /// __eh_frame section. This mode is never used in object files. It is only 354 /// generated by the linker in final linked images, which have only DWARF info 355 /// for a function. 356 UNWIND_ARM64_MODE_DWARF = 0x03000000, 357 358 /// \brief This is a standard arm64 prologue where FP/LR are immediately 359 /// pushed on the stack, then SP is copied to FP. If there are any 360 /// non-volatile register saved, they are copied into the stack fame in pairs 361 /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the 362 /// five X pairs and four D pairs can be saved, but the memory layout must be 363 /// in register number order. 364 UNWIND_ARM64_MODE_FRAME = 0x04000000, 365 366 /// \brief Frame register pair encodings. 367 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001, 368 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002, 369 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004, 370 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008, 371 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010, 372 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100, 373 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200, 374 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400, 375 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800 376 }; 377 378 } // end CU namespace 379 380 // FIXME: This should be in a separate file. 381 class DarwinAArch64AsmBackend : public AArch64AsmBackend { 382 const MCRegisterInfo &MRI; 383 384 /// \brief Encode compact unwind stack adjustment for frameless functions. 385 /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h. 386 /// The stack size always needs to be 16 byte aligned. 387 uint32_t encodeStackAdjustment(uint32_t StackSize) const { 388 return (StackSize / 16) << 12; 389 } 390 391 public: 392 DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI) 393 : AArch64AsmBackend(T, /*IsLittleEndian*/true), MRI(MRI) {} 394 395 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 396 return createAArch64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64, 397 MachO::CPU_SUBTYPE_ARM64_ALL); 398 } 399 400 /// \brief Generate the compact unwind encoding from the CFI directives. 401 uint32_t generateCompactUnwindEncoding( 402 ArrayRef<MCCFIInstruction> Instrs) const override { 403 if (Instrs.empty()) 404 return CU::UNWIND_ARM64_MODE_FRAMELESS; 405 406 bool HasFP = false; 407 unsigned StackSize = 0; 408 409 uint32_t CompactUnwindEncoding = 0; 410 for (size_t i = 0, e = Instrs.size(); i != e; ++i) { 411 const MCCFIInstruction &Inst = Instrs[i]; 412 413 switch (Inst.getOperation()) { 414 default: 415 // Cannot handle this directive: bail out. 416 return CU::UNWIND_ARM64_MODE_DWARF; 417 case MCCFIInstruction::OpDefCfa: { 418 // Defines a frame pointer. 419 assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) == 420 AArch64::FP && 421 "Invalid frame pointer!"); 422 assert(i + 2 < e && "Insufficient CFI instructions to define a frame!"); 423 424 const MCCFIInstruction &LRPush = Instrs[++i]; 425 assert(LRPush.getOperation() == MCCFIInstruction::OpOffset && 426 "Link register not pushed!"); 427 const MCCFIInstruction &FPPush = Instrs[++i]; 428 assert(FPPush.getOperation() == MCCFIInstruction::OpOffset && 429 "Frame pointer not pushed!"); 430 431 unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true); 432 unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true); 433 434 LRReg = getXRegFromWReg(LRReg); 435 FPReg = getXRegFromWReg(FPReg); 436 437 assert(LRReg == AArch64::LR && FPReg == AArch64::FP && 438 "Pushing invalid registers for frame!"); 439 440 // Indicate that the function has a frame. 441 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME; 442 HasFP = true; 443 break; 444 } 445 case MCCFIInstruction::OpDefCfaOffset: { 446 assert(StackSize == 0 && "We already have the CFA offset!"); 447 StackSize = std::abs(Inst.getOffset()); 448 break; 449 } 450 case MCCFIInstruction::OpOffset: { 451 // Registers are saved in pairs. We expect there to be two consecutive 452 // `.cfi_offset' instructions with the appropriate registers specified. 453 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); 454 if (i + 1 == e) 455 return CU::UNWIND_ARM64_MODE_DWARF; 456 457 const MCCFIInstruction &Inst2 = Instrs[++i]; 458 if (Inst2.getOperation() != MCCFIInstruction::OpOffset) 459 return CU::UNWIND_ARM64_MODE_DWARF; 460 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); 461 462 // N.B. The encodings must be in register number order, and the X 463 // registers before the D registers. 464 465 // X19/X20 pair = 0x00000001, 466 // X21/X22 pair = 0x00000002, 467 // X23/X24 pair = 0x00000004, 468 // X25/X26 pair = 0x00000008, 469 // X27/X28 pair = 0x00000010 470 Reg1 = getXRegFromWReg(Reg1); 471 Reg2 = getXRegFromWReg(Reg2); 472 473 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 && 474 (CompactUnwindEncoding & 0xF1E) == 0) 475 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR; 476 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 && 477 (CompactUnwindEncoding & 0xF1C) == 0) 478 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR; 479 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 && 480 (CompactUnwindEncoding & 0xF18) == 0) 481 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR; 482 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 && 483 (CompactUnwindEncoding & 0xF10) == 0) 484 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR; 485 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 && 486 (CompactUnwindEncoding & 0xF00) == 0) 487 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR; 488 else { 489 Reg1 = getDRegFromBReg(Reg1); 490 Reg2 = getDRegFromBReg(Reg2); 491 492 // D8/D9 pair = 0x00000100, 493 // D10/D11 pair = 0x00000200, 494 // D12/D13 pair = 0x00000400, 495 // D14/D15 pair = 0x00000800 496 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 && 497 (CompactUnwindEncoding & 0xE00) == 0) 498 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR; 499 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 && 500 (CompactUnwindEncoding & 0xC00) == 0) 501 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR; 502 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 && 503 (CompactUnwindEncoding & 0x800) == 0) 504 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR; 505 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15) 506 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR; 507 else 508 // A pair was pushed which we cannot handle. 509 return CU::UNWIND_ARM64_MODE_DWARF; 510 } 511 512 break; 513 } 514 } 515 } 516 517 if (!HasFP) { 518 // With compact unwind info we can only represent stack adjustments of up 519 // to 65520 bytes. 520 if (StackSize > 65520) 521 return CU::UNWIND_ARM64_MODE_DWARF; 522 523 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS; 524 CompactUnwindEncoding |= encodeStackAdjustment(StackSize); 525 } 526 527 return CompactUnwindEncoding; 528 } 529 }; 530 531 } // end anonymous namespace 532 533 namespace { 534 535 class ELFAArch64AsmBackend : public AArch64AsmBackend { 536 public: 537 uint8_t OSABI; 538 bool IsILP32; 539 540 ELFAArch64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian, 541 bool IsILP32) 542 : AArch64AsmBackend(T, IsLittleEndian), OSABI(OSABI), IsILP32(IsILP32) {} 543 544 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 545 return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian, IsILP32); 546 } 547 548 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 549 const MCValue &Target) override; 550 }; 551 552 bool ELFAArch64AsmBackend::shouldForceRelocation(const MCAssembler &Asm, 553 const MCFixup &Fixup, 554 const MCValue &Target) { 555 // The ADRP instruction adds some multiple of 0x1000 to the current PC & 556 // ~0xfff. This means that the required offset to reach a symbol can vary by 557 // up to one step depending on where the ADRP is in memory. For example: 558 // 559 // ADRP x0, there 560 // there: 561 // 562 // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and 563 // we'll need that as an offset. At any other address "there" will be in the 564 // same page as the ADRP and the instruction should encode 0x0. Assuming the 565 // section isn't 0x1000-aligned, we therefore need to delegate this decision 566 // to the linker -- a relocation! 567 if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21) 568 return true; 569 return false; 570 } 571 572 } 573 574 namespace { 575 class COFFAArch64AsmBackend : public AArch64AsmBackend { 576 public: 577 COFFAArch64AsmBackend(const Target &T, const Triple &TheTriple) 578 : AArch64AsmBackend(T, /*IsLittleEndian*/true) {} 579 580 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 581 return createAArch64WinCOFFObjectWriter(OS); 582 } 583 }; 584 } 585 586 MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, 587 const MCRegisterInfo &MRI, 588 const Triple &TheTriple, 589 StringRef CPU, 590 const MCTargetOptions &Options) { 591 if (TheTriple.isOSBinFormatMachO()) 592 return new DarwinAArch64AsmBackend(T, MRI); 593 594 if (TheTriple.isOSBinFormatCOFF()) 595 return new COFFAArch64AsmBackend(T, TheTriple); 596 597 assert(TheTriple.isOSBinFormatELF() && "Invalid target"); 598 599 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 600 bool IsILP32 = Options.getABIName() == "ilp32"; 601 return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true, IsILP32); 602 } 603 604 MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, 605 const MCRegisterInfo &MRI, 606 const Triple &TheTriple, 607 StringRef CPU, 608 const MCTargetOptions &Options) { 609 assert(TheTriple.isOSBinFormatELF() && 610 "Big endian is only supported for ELF targets!"); 611 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 612 bool IsILP32 = Options.getABIName() == "ilp32"; 613 return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/false, IsILP32); 614 } 615