1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This class prints an AArch64 MCInst to a .s file. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AArch64InstPrinter.h" 15 #include "MCTargetDesc/AArch64AddressingModes.h" 16 #include "Utils/AArch64BaseInfo.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/StringExtras.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCInst.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCSubtargetInfo.h" 23 #include "llvm/Support/Format.h" 24 #include "llvm/Support/raw_ostream.h" 25 using namespace llvm; 26 27 #define DEBUG_TYPE "asm-printer" 28 29 #define GET_INSTRUCTION_NAME 30 #define PRINT_ALIAS_INSTR 31 #include "AArch64GenAsmWriter.inc" 32 #define GET_INSTRUCTION_NAME 33 #define PRINT_ALIAS_INSTR 34 #include "AArch64GenAsmWriter1.inc" 35 36 AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI, 37 const MCInstrInfo &MII, 38 const MCRegisterInfo &MRI) 39 : MCInstPrinter(MAI, MII, MRI) {} 40 41 AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI, 42 const MCInstrInfo &MII, 43 const MCRegisterInfo &MRI) 44 : AArch64InstPrinter(MAI, MII, MRI) {} 45 46 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 47 // This is for .cfi directives. 48 OS << getRegisterName(RegNo); 49 } 50 51 void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O, 52 StringRef Annot, 53 const MCSubtargetInfo &STI) { 54 // Check for special encodings and print the canonical alias instead. 55 56 unsigned Opcode = MI->getOpcode(); 57 58 if (Opcode == AArch64::SYSxt) 59 if (printSysAlias(MI, STI, O)) { 60 printAnnotation(O, Annot); 61 return; 62 } 63 64 // SBFM/UBFM should print to a nicer aliased form if possible. 65 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || 66 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { 67 const MCOperand &Op0 = MI->getOperand(0); 68 const MCOperand &Op1 = MI->getOperand(1); 69 const MCOperand &Op2 = MI->getOperand(2); 70 const MCOperand &Op3 = MI->getOperand(3); 71 72 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); 73 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); 74 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 75 const char *AsmMnemonic = nullptr; 76 77 switch (Op3.getImm()) { 78 default: 79 break; 80 case 7: 81 if (IsSigned) 82 AsmMnemonic = "sxtb"; 83 else if (!Is64Bit) 84 AsmMnemonic = "uxtb"; 85 break; 86 case 15: 87 if (IsSigned) 88 AsmMnemonic = "sxth"; 89 else if (!Is64Bit) 90 AsmMnemonic = "uxth"; 91 break; 92 case 31: 93 // *xtw is only valid for signed 64-bit operations. 94 if (Is64Bit && IsSigned) 95 AsmMnemonic = "sxtw"; 96 break; 97 } 98 99 if (AsmMnemonic) { 100 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 101 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg())); 102 printAnnotation(O, Annot); 103 return; 104 } 105 } 106 107 // All immediate shifts are aliases, implemented using the Bitfield 108 // instruction. In all cases the immediate shift amount shift must be in 109 // the range 0 to (reg.size -1). 110 if (Op2.isImm() && Op3.isImm()) { 111 const char *AsmMnemonic = nullptr; 112 int shift = 0; 113 int64_t immr = Op2.getImm(); 114 int64_t imms = Op3.getImm(); 115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { 116 AsmMnemonic = "lsl"; 117 shift = 31 - imms; 118 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && 119 ((imms + 1 == immr))) { 120 AsmMnemonic = "lsl"; 121 shift = 63 - imms; 122 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { 123 AsmMnemonic = "lsr"; 124 shift = immr; 125 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { 126 AsmMnemonic = "lsr"; 127 shift = immr; 128 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { 129 AsmMnemonic = "asr"; 130 shift = immr; 131 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { 132 AsmMnemonic = "asr"; 133 shift = immr; 134 } 135 if (AsmMnemonic) { 136 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 137 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift; 138 printAnnotation(O, Annot); 139 return; 140 } 141 } 142 143 // SBFIZ/UBFIZ aliases 144 if (Op2.getImm() > Op3.getImm()) { 145 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t' 146 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 147 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; 148 printAnnotation(O, Annot); 149 return; 150 } 151 152 // Otherwise SBFX/UBFX is the preferred form 153 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t' 154 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 155 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; 156 printAnnotation(O, Annot); 157 return; 158 } 159 160 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) { 161 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 162 const MCOperand &Op2 = MI->getOperand(2); 163 int ImmR = MI->getOperand(3).getImm(); 164 int ImmS = MI->getOperand(4).getImm(); 165 166 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) && 167 (ImmR == 0 || ImmS < ImmR)) { 168 // BFC takes precedence over its entire range, sligtly differently to BFI. 169 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; 170 int LSB = (BitWidth - ImmR) % BitWidth; 171 int Width = ImmS + 1; 172 173 O << "\tbfc\t" << getRegisterName(Op0.getReg()) 174 << ", #" << LSB << ", #" << Width; 175 printAnnotation(O, Annot); 176 return; 177 } else if (ImmS < ImmR) { 178 // BFI alias 179 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; 180 int LSB = (BitWidth - ImmR) % BitWidth; 181 int Width = ImmS + 1; 182 183 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", " 184 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; 185 printAnnotation(O, Annot); 186 return; 187 } 188 189 int LSB = ImmR; 190 int Width = ImmS - ImmR + 1; 191 // Otherwise BFXIL the preferred form 192 O << "\tbfxil\t" 193 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg()) 194 << ", #" << LSB << ", #" << Width; 195 printAnnotation(O, Annot); 196 return; 197 } 198 199 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift 200 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be 201 // printed. 202 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi || 203 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) && 204 MI->getOperand(1).isExpr()) { 205 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) 206 O << "\tmovz\t"; 207 else 208 O << "\tmovn\t"; 209 210 O << getRegisterName(MI->getOperand(0).getReg()) << ", #"; 211 MI->getOperand(1).getExpr()->print(O, &MAI); 212 return; 213 } 214 215 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) && 216 MI->getOperand(2).isExpr()) { 217 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"; 218 MI->getOperand(2).getExpr()->print(O, &MAI); 219 return; 220 } 221 222 if (!printAliasInstr(MI, STI, O)) 223 printInstruction(MI, STI, O); 224 225 printAnnotation(O, Annot); 226 } 227 228 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, 229 bool &IsTbx) { 230 switch (Opcode) { 231 case AArch64::TBXv8i8One: 232 case AArch64::TBXv8i8Two: 233 case AArch64::TBXv8i8Three: 234 case AArch64::TBXv8i8Four: 235 IsTbx = true; 236 Layout = ".8b"; 237 return true; 238 case AArch64::TBLv8i8One: 239 case AArch64::TBLv8i8Two: 240 case AArch64::TBLv8i8Three: 241 case AArch64::TBLv8i8Four: 242 IsTbx = false; 243 Layout = ".8b"; 244 return true; 245 case AArch64::TBXv16i8One: 246 case AArch64::TBXv16i8Two: 247 case AArch64::TBXv16i8Three: 248 case AArch64::TBXv16i8Four: 249 IsTbx = true; 250 Layout = ".16b"; 251 return true; 252 case AArch64::TBLv16i8One: 253 case AArch64::TBLv16i8Two: 254 case AArch64::TBLv16i8Three: 255 case AArch64::TBLv16i8Four: 256 IsTbx = false; 257 Layout = ".16b"; 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 struct LdStNInstrDesc { 265 unsigned Opcode; 266 const char *Mnemonic; 267 const char *Layout; 268 int ListOperand; 269 bool HasLane; 270 int NaturalOffset; 271 }; 272 273 static const LdStNInstrDesc LdStNInstInfo[] = { 274 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 }, 275 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 }, 276 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 }, 277 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 }, 278 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 }, 279 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 }, 280 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 }, 281 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 }, 282 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 }, 283 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 }, 284 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 }, 285 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 }, 286 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 }, 287 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 }, 288 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 }, 289 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 }, 290 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 }, 291 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 }, 292 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 }, 293 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 }, 294 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 }, 295 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 }, 296 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 }, 297 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 }, 298 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 }, 299 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 }, 300 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 }, 301 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 }, 302 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 }, 303 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 }, 304 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 }, 305 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 }, 306 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 }, 307 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 }, 308 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 }, 309 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 }, 310 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 }, 311 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 }, 312 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 }, 313 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 }, 314 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 }, 315 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 }, 316 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 }, 317 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 }, 318 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 }, 319 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 }, 320 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 }, 321 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 }, 322 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 }, 323 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 }, 324 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 }, 325 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 }, 326 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 }, 327 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 }, 328 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 }, 329 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 }, 330 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 }, 331 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 }, 332 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 }, 333 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 }, 334 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 }, 335 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 }, 336 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 }, 337 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 }, 338 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 }, 339 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 }, 340 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 }, 341 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 }, 342 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 }, 343 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 }, 344 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 }, 345 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 }, 346 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 }, 347 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 }, 348 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 }, 349 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 }, 350 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 }, 351 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 }, 352 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 }, 353 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 }, 354 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 }, 355 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 }, 356 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 }, 357 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 }, 358 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 }, 359 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 }, 360 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 }, 361 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 }, 362 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 }, 363 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 }, 364 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 }, 365 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 }, 366 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 }, 367 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 }, 368 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 }, 369 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 }, 370 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 }, 371 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 }, 372 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 }, 373 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 }, 374 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 }, 375 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 }, 376 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 }, 377 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 }, 378 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 }, 379 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 }, 380 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 }, 381 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 }, 382 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 }, 383 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 }, 384 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 }, 385 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 }, 386 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 }, 387 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 }, 388 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 }, 389 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 }, 390 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 }, 391 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 }, 392 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 }, 393 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 }, 394 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 }, 395 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 }, 396 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 }, 397 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 }, 398 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 }, 399 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 }, 400 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 }, 401 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 }, 402 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 }, 403 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 }, 404 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 }, 405 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 }, 406 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 }, 407 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 }, 408 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 }, 409 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 }, 410 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 }, 411 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 }, 412 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 }, 413 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 }, 414 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 }, 415 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 }, 416 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 }, 417 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 }, 418 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 }, 419 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 }, 420 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 }, 421 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 }, 422 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 }, 423 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 }, 424 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 }, 425 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 }, 426 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 }, 427 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 }, 428 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 }, 429 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 }, 430 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 }, 431 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 }, 432 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 }, 433 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 }, 434 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 }, 435 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 }, 436 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 }, 437 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 }, 438 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 }, 439 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 }, 440 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 }, 441 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 }, 442 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 }, 443 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 }, 444 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 }, 445 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 }, 446 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 }, 447 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 }, 448 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 }, 449 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 }, 450 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 }, 451 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 }, 452 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 }, 453 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 }, 454 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 }, 455 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 }, 456 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 }, 457 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 }, 458 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 }, 459 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 }, 460 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 }, 461 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 }, 462 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 }, 463 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 }, 464 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 }, 465 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 }, 466 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 }, 467 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 }, 468 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 }, 469 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 }, 470 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 }, 471 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 }, 472 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 }, 473 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 }, 474 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 }, 475 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 }, 476 { AArch64::ST1i8, "st1", ".b", 0, true, 0 }, 477 { AArch64::ST1i16, "st1", ".h", 0, true, 0 }, 478 { AArch64::ST1i32, "st1", ".s", 0, true, 0 }, 479 { AArch64::ST1i64, "st1", ".d", 0, true, 0 }, 480 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 }, 481 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 }, 482 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 }, 483 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 }, 484 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 }, 485 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 }, 486 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 }, 487 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 }, 488 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 }, 489 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 }, 490 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 }, 491 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 }, 492 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 }, 493 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 }, 494 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 }, 495 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 }, 496 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 }, 497 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 }, 498 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 }, 499 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 }, 500 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 }, 501 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 }, 502 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 }, 503 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 }, 504 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 }, 505 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 }, 506 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 }, 507 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 }, 508 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 }, 509 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 }, 510 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 }, 511 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 }, 512 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 }, 513 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 }, 514 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 }, 515 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 }, 516 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 }, 517 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 }, 518 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 }, 519 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 }, 520 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 }, 521 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 }, 522 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 }, 523 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 }, 524 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 }, 525 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 }, 526 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 }, 527 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 }, 528 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 }, 529 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 }, 530 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 }, 531 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 }, 532 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 }, 533 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 }, 534 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 }, 535 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 }, 536 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 }, 537 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 }, 538 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 }, 539 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 }, 540 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 }, 541 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 }, 542 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 }, 543 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 }, 544 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 }, 545 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 }, 546 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 }, 547 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 }, 548 { AArch64::ST2i8, "st2", ".b", 0, true, 0 }, 549 { AArch64::ST2i16, "st2", ".h", 0, true, 0 }, 550 { AArch64::ST2i32, "st2", ".s", 0, true, 0 }, 551 { AArch64::ST2i64, "st2", ".d", 0, true, 0 }, 552 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 }, 553 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 }, 554 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 }, 555 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 }, 556 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 }, 557 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 }, 558 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 }, 559 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 }, 560 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 }, 561 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 }, 562 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 }, 563 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 }, 564 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 }, 565 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 }, 566 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 }, 567 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 }, 568 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 }, 569 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 }, 570 { AArch64::ST3i8, "st3", ".b", 0, true, 0 }, 571 { AArch64::ST3i16, "st3", ".h", 0, true, 0 }, 572 { AArch64::ST3i32, "st3", ".s", 0, true, 0 }, 573 { AArch64::ST3i64, "st3", ".d", 0, true, 0 }, 574 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 }, 575 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 }, 576 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 }, 577 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 }, 578 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 }, 579 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 }, 580 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 }, 581 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 }, 582 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 }, 583 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 }, 584 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 }, 585 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 }, 586 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 }, 587 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 }, 588 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 }, 589 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 }, 590 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 }, 591 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 }, 592 { AArch64::ST4i8, "st4", ".b", 0, true, 0 }, 593 { AArch64::ST4i16, "st4", ".h", 0, true, 0 }, 594 { AArch64::ST4i32, "st4", ".s", 0, true, 0 }, 595 { AArch64::ST4i64, "st4", ".d", 0, true, 0 }, 596 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 }, 597 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 }, 598 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 }, 599 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 }, 600 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 }, 601 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 }, 602 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 }, 603 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 }, 604 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 }, 605 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 }, 606 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 }, 607 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 }, 608 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 }, 609 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 }, 610 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 }, 611 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 }, 612 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 }, 613 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 }, 614 }; 615 616 static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) { 617 unsigned Idx; 618 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx) 619 if (LdStNInstInfo[Idx].Opcode == Opcode) 620 return &LdStNInstInfo[Idx]; 621 622 return nullptr; 623 } 624 625 void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 626 StringRef Annot, 627 const MCSubtargetInfo &STI) { 628 unsigned Opcode = MI->getOpcode(); 629 StringRef Layout, Mnemonic; 630 631 bool IsTbx; 632 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) { 633 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t' 634 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", "; 635 636 unsigned ListOpNum = IsTbx ? 2 : 1; 637 printVectorList(MI, ListOpNum, STI, O, ""); 638 639 O << ", " 640 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg); 641 printAnnotation(O, Annot); 642 return; 643 } 644 645 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) { 646 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t'; 647 648 // Now onto the operands: first a vector list with possible lane 649 // specifier. E.g. { v0 }[2] 650 int OpNum = LdStDesc->ListOperand; 651 printVectorList(MI, OpNum++, STI, O, ""); 652 653 if (LdStDesc->HasLane) 654 O << '[' << MI->getOperand(OpNum++).getImm() << ']'; 655 656 // Next the address: [xN] 657 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); 658 O << ", [" << getRegisterName(AddrReg) << ']'; 659 660 // Finally, there might be a post-indexed offset. 661 if (LdStDesc->NaturalOffset != 0) { 662 unsigned Reg = MI->getOperand(OpNum++).getReg(); 663 if (Reg != AArch64::XZR) 664 O << ", " << getRegisterName(Reg); 665 else { 666 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?"); 667 O << ", #" << LdStDesc->NaturalOffset; 668 } 669 } 670 671 printAnnotation(O, Annot); 672 return; 673 } 674 675 AArch64InstPrinter::printInst(MI, O, Annot, STI); 676 } 677 678 bool AArch64InstPrinter::printSysAlias(const MCInst *MI, 679 const MCSubtargetInfo &STI, 680 raw_ostream &O) { 681 #ifndef NDEBUG 682 unsigned Opcode = MI->getOpcode(); 683 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!"); 684 #endif 685 686 const char *Asm = nullptr; 687 const MCOperand &Op1 = MI->getOperand(0); 688 const MCOperand &Cn = MI->getOperand(1); 689 const MCOperand &Cm = MI->getOperand(2); 690 const MCOperand &Op2 = MI->getOperand(3); 691 692 unsigned Op1Val = Op1.getImm(); 693 unsigned CnVal = Cn.getImm(); 694 unsigned CmVal = Cm.getImm(); 695 unsigned Op2Val = Op2.getImm(); 696 697 if (CnVal == 7) { 698 switch (CmVal) { 699 default: 700 break; 701 702 // IC aliases 703 case 1: 704 if (Op1Val == 0 && Op2Val == 0) 705 Asm = "ic\tialluis"; 706 break; 707 case 5: 708 if (Op1Val == 0 && Op2Val == 0) 709 Asm = "ic\tiallu"; 710 else if (Op1Val == 3 && Op2Val == 1) 711 Asm = "ic\tivau"; 712 break; 713 714 // DC aliases 715 case 4: 716 if (Op1Val == 3 && Op2Val == 1) 717 Asm = "dc\tzva"; 718 break; 719 case 6: 720 if (Op1Val == 0 && Op2Val == 1) 721 Asm = "dc\tivac"; 722 if (Op1Val == 0 && Op2Val == 2) 723 Asm = "dc\tisw"; 724 break; 725 case 10: 726 if (Op1Val == 3 && Op2Val == 1) 727 Asm = "dc\tcvac"; 728 else if (Op1Val == 0 && Op2Val == 2) 729 Asm = "dc\tcsw"; 730 break; 731 case 11: 732 if (Op1Val == 3 && Op2Val == 1) 733 Asm = "dc\tcvau"; 734 break; 735 case 12: 736 if (Op1Val == 3 && Op2Val == 1 && 737 (STI.getFeatureBits()[AArch64::HasV8_2aOps])) 738 Asm = "dc\tcvap"; 739 break; 740 case 14: 741 if (Op1Val == 3 && Op2Val == 1) 742 Asm = "dc\tcivac"; 743 else if (Op1Val == 0 && Op2Val == 2) 744 Asm = "dc\tcisw"; 745 break; 746 747 // AT aliases 748 case 8: 749 switch (Op1Val) { 750 default: 751 break; 752 case 0: 753 switch (Op2Val) { 754 default: 755 break; 756 case 0: Asm = "at\ts1e1r"; break; 757 case 1: Asm = "at\ts1e1w"; break; 758 case 2: Asm = "at\ts1e0r"; break; 759 case 3: Asm = "at\ts1e0w"; break; 760 } 761 break; 762 case 4: 763 switch (Op2Val) { 764 default: 765 break; 766 case 0: Asm = "at\ts1e2r"; break; 767 case 1: Asm = "at\ts1e2w"; break; 768 case 4: Asm = "at\ts12e1r"; break; 769 case 5: Asm = "at\ts12e1w"; break; 770 case 6: Asm = "at\ts12e0r"; break; 771 case 7: Asm = "at\ts12e0w"; break; 772 } 773 break; 774 case 6: 775 switch (Op2Val) { 776 default: 777 break; 778 case 0: Asm = "at\ts1e3r"; break; 779 case 1: Asm = "at\ts1e3w"; break; 780 } 781 break; 782 } 783 break; 784 case 9: 785 switch (Op1Val) { 786 default: 787 break; 788 case 0: 789 if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) { 790 switch (Op2Val) { 791 default: 792 break; 793 case 0: Asm = "at\ts1e1rp"; break; 794 case 1: Asm = "at\ts1e1wp"; break; 795 } 796 } 797 break; 798 } 799 } 800 } else if (CnVal == 8) { 801 // TLBI aliases 802 switch (CmVal) { 803 default: 804 break; 805 case 3: 806 switch (Op1Val) { 807 default: 808 break; 809 case 0: 810 switch (Op2Val) { 811 default: 812 break; 813 case 0: Asm = "tlbi\tvmalle1is"; break; 814 case 1: Asm = "tlbi\tvae1is"; break; 815 case 2: Asm = "tlbi\taside1is"; break; 816 case 3: Asm = "tlbi\tvaae1is"; break; 817 case 5: Asm = "tlbi\tvale1is"; break; 818 case 7: Asm = "tlbi\tvaale1is"; break; 819 } 820 break; 821 case 4: 822 switch (Op2Val) { 823 default: 824 break; 825 case 0: Asm = "tlbi\talle2is"; break; 826 case 1: Asm = "tlbi\tvae2is"; break; 827 case 4: Asm = "tlbi\talle1is"; break; 828 case 5: Asm = "tlbi\tvale2is"; break; 829 case 6: Asm = "tlbi\tvmalls12e1is"; break; 830 } 831 break; 832 case 6: 833 switch (Op2Val) { 834 default: 835 break; 836 case 0: Asm = "tlbi\talle3is"; break; 837 case 1: Asm = "tlbi\tvae3is"; break; 838 case 5: Asm = "tlbi\tvale3is"; break; 839 } 840 break; 841 } 842 break; 843 case 0: 844 switch (Op1Val) { 845 default: 846 break; 847 case 4: 848 switch (Op2Val) { 849 default: 850 break; 851 case 1: Asm = "tlbi\tipas2e1is"; break; 852 case 5: Asm = "tlbi\tipas2le1is"; break; 853 } 854 break; 855 } 856 break; 857 case 4: 858 switch (Op1Val) { 859 default: 860 break; 861 case 4: 862 switch (Op2Val) { 863 default: 864 break; 865 case 1: Asm = "tlbi\tipas2e1"; break; 866 case 5: Asm = "tlbi\tipas2le1"; break; 867 } 868 break; 869 } 870 break; 871 case 7: 872 switch (Op1Val) { 873 default: 874 break; 875 case 0: 876 switch (Op2Val) { 877 default: 878 break; 879 case 0: Asm = "tlbi\tvmalle1"; break; 880 case 1: Asm = "tlbi\tvae1"; break; 881 case 2: Asm = "tlbi\taside1"; break; 882 case 3: Asm = "tlbi\tvaae1"; break; 883 case 5: Asm = "tlbi\tvale1"; break; 884 case 7: Asm = "tlbi\tvaale1"; break; 885 } 886 break; 887 case 4: 888 switch (Op2Val) { 889 default: 890 break; 891 case 0: Asm = "tlbi\talle2"; break; 892 case 1: Asm = "tlbi\tvae2"; break; 893 case 4: Asm = "tlbi\talle1"; break; 894 case 5: Asm = "tlbi\tvale2"; break; 895 case 6: Asm = "tlbi\tvmalls12e1"; break; 896 } 897 break; 898 case 6: 899 switch (Op2Val) { 900 default: 901 break; 902 case 0: Asm = "tlbi\talle3"; break; 903 case 1: Asm = "tlbi\tvae3"; break; 904 case 5: Asm = "tlbi\tvale3"; break; 905 } 906 break; 907 } 908 break; 909 } 910 } 911 912 if (Asm) { 913 unsigned Reg = MI->getOperand(4).getReg(); 914 915 O << '\t' << Asm; 916 if (StringRef(Asm).lower().find("all") == StringRef::npos) 917 O << ", " << getRegisterName(Reg); 918 } 919 920 return Asm != nullptr; 921 } 922 923 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 924 const MCSubtargetInfo &STI, 925 raw_ostream &O) { 926 const MCOperand &Op = MI->getOperand(OpNo); 927 if (Op.isReg()) { 928 unsigned Reg = Op.getReg(); 929 O << getRegisterName(Reg); 930 } else if (Op.isImm()) { 931 O << '#' << Op.getImm(); 932 } else { 933 assert(Op.isExpr() && "unknown operand kind in printOperand"); 934 Op.getExpr()->print(O, &MAI); 935 } 936 } 937 938 void AArch64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo, 939 const MCSubtargetInfo &STI, 940 raw_ostream &O) { 941 const MCOperand &Op = MI->getOperand(OpNo); 942 O << format("#%#llx", Op.getImm()); 943 } 944 945 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo, 946 unsigned Imm, raw_ostream &O) { 947 const MCOperand &Op = MI->getOperand(OpNo); 948 if (Op.isReg()) { 949 unsigned Reg = Op.getReg(); 950 if (Reg == AArch64::XZR) 951 O << "#" << Imm; 952 else 953 O << getRegisterName(Reg); 954 } else 955 llvm_unreachable("unknown operand kind in printPostIncOperand64"); 956 } 957 958 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo, 959 const MCSubtargetInfo &STI, 960 raw_ostream &O) { 961 const MCOperand &Op = MI->getOperand(OpNo); 962 assert(Op.isReg() && "Non-register vreg operand!"); 963 unsigned Reg = Op.getReg(); 964 O << getRegisterName(Reg, AArch64::vreg); 965 } 966 967 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo, 968 const MCSubtargetInfo &STI, 969 raw_ostream &O) { 970 const MCOperand &Op = MI->getOperand(OpNo); 971 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); 972 O << "c" << Op.getImm(); 973 } 974 975 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum, 976 const MCSubtargetInfo &STI, 977 raw_ostream &O) { 978 const MCOperand &MO = MI->getOperand(OpNum); 979 if (MO.isImm()) { 980 unsigned Val = (MO.getImm() & 0xfff); 981 assert(Val == MO.getImm() && "Add/sub immediate out of range!"); 982 unsigned Shift = 983 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); 984 O << '#' << Val; 985 if (Shift != 0) 986 printShifter(MI, OpNum + 1, STI, O); 987 988 if (CommentStream) 989 *CommentStream << '=' << (Val << Shift) << '\n'; 990 } else { 991 assert(MO.isExpr() && "Unexpected operand type!"); 992 MO.getExpr()->print(O, &MAI); 993 printShifter(MI, OpNum + 1, STI, O); 994 } 995 } 996 997 void AArch64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum, 998 const MCSubtargetInfo &STI, 999 raw_ostream &O) { 1000 uint64_t Val = MI->getOperand(OpNum).getImm(); 1001 O << "#0x"; 1002 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 32)); 1003 } 1004 1005 void AArch64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum, 1006 const MCSubtargetInfo &STI, 1007 raw_ostream &O) { 1008 uint64_t Val = MI->getOperand(OpNum).getImm(); 1009 O << "#0x"; 1010 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 64)); 1011 } 1012 1013 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum, 1014 const MCSubtargetInfo &STI, 1015 raw_ostream &O) { 1016 unsigned Val = MI->getOperand(OpNum).getImm(); 1017 // LSL #0 should not be printed. 1018 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL && 1019 AArch64_AM::getShiftValue(Val) == 0) 1020 return; 1021 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val)) 1022 << " #" << AArch64_AM::getShiftValue(Val); 1023 } 1024 1025 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum, 1026 const MCSubtargetInfo &STI, 1027 raw_ostream &O) { 1028 O << getRegisterName(MI->getOperand(OpNum).getReg()); 1029 printShifter(MI, OpNum + 1, STI, O); 1030 } 1031 1032 void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum, 1033 const MCSubtargetInfo &STI, 1034 raw_ostream &O) { 1035 O << getRegisterName(MI->getOperand(OpNum).getReg()); 1036 printArithExtend(MI, OpNum + 1, STI, O); 1037 } 1038 1039 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum, 1040 const MCSubtargetInfo &STI, 1041 raw_ostream &O) { 1042 unsigned Val = MI->getOperand(OpNum).getImm(); 1043 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); 1044 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); 1045 1046 // If the destination or first source register operand is [W]SP, print 1047 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at 1048 // all. 1049 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { 1050 unsigned Dest = MI->getOperand(0).getReg(); 1051 unsigned Src1 = MI->getOperand(1).getReg(); 1052 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) && 1053 ExtType == AArch64_AM::UXTX) || 1054 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) && 1055 ExtType == AArch64_AM::UXTW) ) { 1056 if (ShiftVal != 0) 1057 O << ", lsl #" << ShiftVal; 1058 return; 1059 } 1060 } 1061 O << ", " << AArch64_AM::getShiftExtendName(ExtType); 1062 if (ShiftVal != 0) 1063 O << " #" << ShiftVal; 1064 } 1065 1066 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum, 1067 raw_ostream &O, char SrcRegKind, 1068 unsigned Width) { 1069 unsigned SignExtend = MI->getOperand(OpNum).getImm(); 1070 unsigned DoShift = MI->getOperand(OpNum + 1).getImm(); 1071 1072 // sxtw, sxtx, uxtw or lsl (== uxtx) 1073 bool IsLSL = !SignExtend && SrcRegKind == 'x'; 1074 if (IsLSL) 1075 O << "lsl"; 1076 else 1077 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind; 1078 1079 if (DoShift || IsLSL) 1080 O << " #" << Log2_32(Width / 8); 1081 } 1082 1083 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum, 1084 const MCSubtargetInfo &STI, 1085 raw_ostream &O) { 1086 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1087 O << AArch64CC::getCondCodeName(CC); 1088 } 1089 1090 void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum, 1091 const MCSubtargetInfo &STI, 1092 raw_ostream &O) { 1093 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1094 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC)); 1095 } 1096 1097 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum, 1098 const MCSubtargetInfo &STI, 1099 raw_ostream &O) { 1100 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']'; 1101 } 1102 1103 template<int Scale> 1104 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum, 1105 const MCSubtargetInfo &STI, 1106 raw_ostream &O) { 1107 O << '#' << Scale * MI->getOperand(OpNum).getImm(); 1108 } 1109 1110 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum, 1111 unsigned Scale, raw_ostream &O) { 1112 const MCOperand MO = MI->getOperand(OpNum); 1113 if (MO.isImm()) { 1114 O << "#" << (MO.getImm() * Scale); 1115 } else { 1116 assert(MO.isExpr() && "Unexpected operand type!"); 1117 MO.getExpr()->print(O, &MAI); 1118 } 1119 } 1120 1121 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum, 1122 unsigned Scale, raw_ostream &O) { 1123 const MCOperand MO1 = MI->getOperand(OpNum + 1); 1124 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()); 1125 if (MO1.isImm()) { 1126 O << ", #" << (MO1.getImm() * Scale); 1127 } else { 1128 assert(MO1.isExpr() && "Unexpected operand type!"); 1129 O << ", "; 1130 MO1.getExpr()->print(O, &MAI); 1131 } 1132 O << ']'; 1133 } 1134 1135 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum, 1136 const MCSubtargetInfo &STI, 1137 raw_ostream &O) { 1138 unsigned prfop = MI->getOperand(OpNum).getImm(); 1139 bool Valid; 1140 StringRef Name = 1141 AArch64PRFM::PRFMMapper().toString(prfop, STI.getFeatureBits(), Valid); 1142 if (Valid) 1143 O << Name; 1144 else 1145 O << '#' << prfop; 1146 } 1147 1148 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum, 1149 const MCSubtargetInfo &STI, 1150 raw_ostream &O) { 1151 unsigned psbhintop = MI->getOperand(OpNum).getImm(); 1152 bool Valid; 1153 StringRef Name = 1154 AArch64PSBHint::PSBHintMapper().toString(psbhintop, STI.getFeatureBits(), Valid); 1155 if (Valid) 1156 O << Name; 1157 else 1158 O << '#' << psbhintop; 1159 } 1160 1161 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 1162 const MCSubtargetInfo &STI, 1163 raw_ostream &O) { 1164 const MCOperand &MO = MI->getOperand(OpNum); 1165 float FPImm = 1166 MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm()); 1167 1168 // 8 decimal places are enough to perfectly represent permitted floats. 1169 O << format("#%.8f", FPImm); 1170 } 1171 1172 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) { 1173 while (Stride--) { 1174 switch (Reg) { 1175 default: 1176 llvm_unreachable("Vector register expected!"); 1177 case AArch64::Q0: Reg = AArch64::Q1; break; 1178 case AArch64::Q1: Reg = AArch64::Q2; break; 1179 case AArch64::Q2: Reg = AArch64::Q3; break; 1180 case AArch64::Q3: Reg = AArch64::Q4; break; 1181 case AArch64::Q4: Reg = AArch64::Q5; break; 1182 case AArch64::Q5: Reg = AArch64::Q6; break; 1183 case AArch64::Q6: Reg = AArch64::Q7; break; 1184 case AArch64::Q7: Reg = AArch64::Q8; break; 1185 case AArch64::Q8: Reg = AArch64::Q9; break; 1186 case AArch64::Q9: Reg = AArch64::Q10; break; 1187 case AArch64::Q10: Reg = AArch64::Q11; break; 1188 case AArch64::Q11: Reg = AArch64::Q12; break; 1189 case AArch64::Q12: Reg = AArch64::Q13; break; 1190 case AArch64::Q13: Reg = AArch64::Q14; break; 1191 case AArch64::Q14: Reg = AArch64::Q15; break; 1192 case AArch64::Q15: Reg = AArch64::Q16; break; 1193 case AArch64::Q16: Reg = AArch64::Q17; break; 1194 case AArch64::Q17: Reg = AArch64::Q18; break; 1195 case AArch64::Q18: Reg = AArch64::Q19; break; 1196 case AArch64::Q19: Reg = AArch64::Q20; break; 1197 case AArch64::Q20: Reg = AArch64::Q21; break; 1198 case AArch64::Q21: Reg = AArch64::Q22; break; 1199 case AArch64::Q22: Reg = AArch64::Q23; break; 1200 case AArch64::Q23: Reg = AArch64::Q24; break; 1201 case AArch64::Q24: Reg = AArch64::Q25; break; 1202 case AArch64::Q25: Reg = AArch64::Q26; break; 1203 case AArch64::Q26: Reg = AArch64::Q27; break; 1204 case AArch64::Q27: Reg = AArch64::Q28; break; 1205 case AArch64::Q28: Reg = AArch64::Q29; break; 1206 case AArch64::Q29: Reg = AArch64::Q30; break; 1207 case AArch64::Q30: Reg = AArch64::Q31; break; 1208 // Vector lists can wrap around. 1209 case AArch64::Q31: 1210 Reg = AArch64::Q0; 1211 break; 1212 } 1213 } 1214 return Reg; 1215 } 1216 1217 template<unsigned size> 1218 void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI, 1219 unsigned OpNum, 1220 const MCSubtargetInfo &STI, 1221 raw_ostream &O) { 1222 static_assert(size == 64 || size == 32, 1223 "Template parameter must be either 32 or 64"); 1224 unsigned Reg = MI->getOperand(OpNum).getReg(); 1225 1226 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64; 1227 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64; 1228 1229 unsigned Even = MRI.getSubReg(Reg, Sube); 1230 unsigned Odd = MRI.getSubReg(Reg, Subo); 1231 O << getRegisterName(Even) << ", " << getRegisterName(Odd); 1232 } 1233 1234 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum, 1235 const MCSubtargetInfo &STI, 1236 raw_ostream &O, 1237 StringRef LayoutSuffix) { 1238 unsigned Reg = MI->getOperand(OpNum).getReg(); 1239 1240 O << "{ "; 1241 1242 // Work out how many registers there are in the list (if there is an actual 1243 // list). 1244 unsigned NumRegs = 1; 1245 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || 1246 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) 1247 NumRegs = 2; 1248 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || 1249 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) 1250 NumRegs = 3; 1251 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || 1252 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg)) 1253 NumRegs = 4; 1254 1255 // Now forget about the list and find out what the first register is. 1256 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) 1257 Reg = FirstReg; 1258 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) 1259 Reg = FirstReg; 1260 1261 // If it's a D-reg, we need to promote it to the equivalent Q-reg before 1262 // printing (otherwise getRegisterName fails). 1263 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { 1264 const MCRegisterClass &FPR128RC = 1265 MRI.getRegClass(AArch64::FPR128RegClassID); 1266 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); 1267 } 1268 1269 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) { 1270 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix; 1271 if (i + 1 != NumRegs) 1272 O << ", "; 1273 } 1274 1275 O << " }"; 1276 } 1277 1278 void 1279 AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI, 1280 unsigned OpNum, 1281 const MCSubtargetInfo &STI, 1282 raw_ostream &O) { 1283 printVectorList(MI, OpNum, STI, O, ""); 1284 } 1285 1286 template <unsigned NumLanes, char LaneKind> 1287 void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum, 1288 const MCSubtargetInfo &STI, 1289 raw_ostream &O) { 1290 std::string Suffix("."); 1291 if (NumLanes) 1292 Suffix += itostr(NumLanes) + LaneKind; 1293 else 1294 Suffix += LaneKind; 1295 1296 printVectorList(MI, OpNum, STI, O, Suffix); 1297 } 1298 1299 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 1300 const MCSubtargetInfo &STI, 1301 raw_ostream &O) { 1302 O << "[" << MI->getOperand(OpNum).getImm() << "]"; 1303 } 1304 1305 void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum, 1306 const MCSubtargetInfo &STI, 1307 raw_ostream &O) { 1308 const MCOperand &Op = MI->getOperand(OpNum); 1309 1310 // If the label has already been resolved to an immediate offset (say, when 1311 // we're running the disassembler), just print the immediate. 1312 if (Op.isImm()) { 1313 O << "#" << (Op.getImm() * 4); 1314 return; 1315 } 1316 1317 // If the branch target is simply an address then print it in hex. 1318 const MCConstantExpr *BranchTarget = 1319 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr()); 1320 int64_t Address; 1321 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { 1322 O << "0x"; 1323 O.write_hex(Address); 1324 } else { 1325 // Otherwise, just print the expression. 1326 MI->getOperand(OpNum).getExpr()->print(O, &MAI); 1327 } 1328 } 1329 1330 void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum, 1331 const MCSubtargetInfo &STI, 1332 raw_ostream &O) { 1333 const MCOperand &Op = MI->getOperand(OpNum); 1334 1335 // If the label has already been resolved to an immediate offset (say, when 1336 // we're running the disassembler), just print the immediate. 1337 if (Op.isImm()) { 1338 O << "#" << (Op.getImm() * (1 << 12)); 1339 return; 1340 } 1341 1342 // Otherwise, just print the expression. 1343 MI->getOperand(OpNum).getExpr()->print(O, &MAI); 1344 } 1345 1346 void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo, 1347 const MCSubtargetInfo &STI, 1348 raw_ostream &O) { 1349 unsigned Val = MI->getOperand(OpNo).getImm(); 1350 unsigned Opcode = MI->getOpcode(); 1351 1352 bool Valid; 1353 StringRef Name; 1354 if (Opcode == AArch64::ISB) 1355 Name = AArch64ISB::ISBMapper().toString(Val, STI.getFeatureBits(), 1356 Valid); 1357 else 1358 Name = AArch64DB::DBarrierMapper().toString(Val, STI.getFeatureBits(), 1359 Valid); 1360 if (Valid) 1361 O << Name; 1362 else 1363 O << "#" << Val; 1364 } 1365 1366 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo, 1367 const MCSubtargetInfo &STI, 1368 raw_ostream &O) { 1369 unsigned Val = MI->getOperand(OpNo).getImm(); 1370 1371 auto Mapper = AArch64SysReg::MRSMapper(); 1372 std::string Name = Mapper.toString(Val, STI.getFeatureBits()); 1373 1374 O << StringRef(Name).upper(); 1375 } 1376 1377 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo, 1378 const MCSubtargetInfo &STI, 1379 raw_ostream &O) { 1380 unsigned Val = MI->getOperand(OpNo).getImm(); 1381 1382 auto Mapper = AArch64SysReg::MSRMapper(); 1383 std::string Name = Mapper.toString(Val, STI.getFeatureBits()); 1384 1385 O << StringRef(Name).upper(); 1386 } 1387 1388 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo, 1389 const MCSubtargetInfo &STI, 1390 raw_ostream &O) { 1391 unsigned Val = MI->getOperand(OpNo).getImm(); 1392 1393 bool Valid; 1394 StringRef Name = 1395 AArch64PState::PStateMapper().toString(Val, STI.getFeatureBits(), Valid); 1396 if (Valid) 1397 O << Name.upper(); 1398 else 1399 O << "#" << Val; 1400 } 1401 1402 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo, 1403 const MCSubtargetInfo &STI, 1404 raw_ostream &O) { 1405 unsigned RawVal = MI->getOperand(OpNo).getImm(); 1406 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal); 1407 O << format("#%#016llx", Val); 1408 } 1409