1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AArch64Disassembler.h" 14 #include "AArch64ExternalSymbolizer.h" 15 #include "AArch64Subtarget.h" 16 #include "MCTargetDesc/AArch64AddressingModes.h" 17 #include "MCTargetDesc/AArch64MCTargetDesc.h" 18 #include "Utils/AArch64BaseInfo.h" 19 #include "llvm-c/Disassembler.h" 20 #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" 21 #include "llvm/MC/MCFixedLenDisassembler.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/Support/Compiler.h" 24 #include "llvm/Support/Debug.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/TargetRegistry.h" 27 #include <algorithm> 28 #include <memory> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "aarch64-disassembler" 33 34 // Pull DecodeStatus and its enum values into the global namespace. 35 using DecodeStatus = MCDisassembler::DecodeStatus; 36 37 // Forward declare these because the autogenerated code will reference them. 38 // Definitions are further down. 39 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, 40 unsigned RegNo, uint64_t Address, 41 const void *Decoder); 42 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, 43 unsigned RegNo, 44 uint64_t Address, 45 const void *Decoder); 46 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 47 uint64_t Address, 48 const void *Decoder); 49 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 50 uint64_t Address, 51 const void *Decoder); 52 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, 54 const void *Decoder); 55 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 56 uint64_t Address, 57 const void *Decoder); 58 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 59 uint64_t Address, 60 const void *Decoder); 61 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, 62 unsigned RegNo, uint64_t Address, 63 const void *Decoder); 64 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 65 uint64_t Address, 66 const void *Decoder); 67 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, 68 unsigned RegNo, uint64_t Address, 69 const void *Decoder); 70 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 71 uint64_t Address, 72 const void *Decoder); 73 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 74 uint64_t Address, 75 const void *Decoder); 76 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 77 uint64_t Address, 78 const void *Decoder); 79 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t Address, 81 const void *Decoder); 82 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 83 uint64_t Address, 84 const void *Decoder); 85 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 86 uint64_t Address, 87 const void *Decoder); 88 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 89 uint64_t Address, 90 const void *Decode); 91 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 92 uint64_t Address, 93 const void *Decode); 94 95 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 96 uint64_t Address, 97 const void *Decoder); 98 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 99 uint64_t Address, 100 const void *Decoder); 101 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 102 uint64_t Address, const void *Decoder); 103 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 104 uint64_t Address, const void *Decoder); 105 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 106 uint64_t Address, const void *Decoder); 107 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 108 uint64_t Address, const void *Decoder); 109 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 110 uint64_t Address, 111 const void *Decoder); 112 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 113 uint64_t Address, 114 const void *Decoder); 115 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 116 uint64_t Address, 117 const void *Decoder); 118 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 119 uint64_t Address, 120 const void *Decoder); 121 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 122 uint64_t Address, 123 const void *Decoder); 124 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 125 uint64_t Address, 126 const void *Decoder); 127 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 128 uint64_t Address, 129 const void *Decoder); 130 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 131 uint64_t Address, 132 const void *Decoder); 133 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 134 uint64_t Address, 135 const void *Decoder); 136 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 137 uint64_t Address, 138 const void *Decoder); 139 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 140 uint64_t Address, const void *Decoder); 141 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 144 uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 147 uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 150 uint64_t Address, const void *Decoder); 151 152 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 153 uint64_t Address, 154 const void *Decoder); 155 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 156 uint64_t Addr, const void *Decoder); 157 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 158 uint64_t Addr, 159 const void *Decoder); 160 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 161 uint64_t Addr, const void *Decoder); 162 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 163 uint64_t Addr, 164 const void *Decoder); 165 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 166 uint64_t Addr, const void *Decoder); 167 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 168 uint64_t Addr, 169 const void *Decoder); 170 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, const void *Decoder); 172 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 173 uint64_t Addr, const void *Decoder); 174 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 175 uint64_t Addr, const void *Decoder); 176 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 177 uint64_t Addr, const void *Decoder); 178 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 179 uint64_t Addr, const void *Decoder); 180 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 181 unsigned RegNo, 182 uint64_t Addr, 183 const void *Decoder); 184 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 185 unsigned RegNo, 186 uint64_t Addr, 187 const void *Decoder); 188 template<int Bits> 189 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 190 uint64_t Address, const void *Decoder); 191 192 static bool Check(DecodeStatus &Out, DecodeStatus In) { 193 switch (In) { 194 case MCDisassembler::Success: 195 // Out stays the same. 196 return true; 197 case MCDisassembler::SoftFail: 198 Out = In; 199 return true; 200 case MCDisassembler::Fail: 201 Out = In; 202 return false; 203 } 204 llvm_unreachable("Invalid DecodeStatus!"); 205 } 206 207 #include "AArch64GenDisassemblerTables.inc" 208 #include "AArch64GenInstrInfo.inc" 209 210 #define Success MCDisassembler::Success 211 #define Fail MCDisassembler::Fail 212 #define SoftFail MCDisassembler::SoftFail 213 214 static MCDisassembler *createAArch64Disassembler(const Target &T, 215 const MCSubtargetInfo &STI, 216 MCContext &Ctx) { 217 return new AArch64Disassembler(STI, Ctx); 218 } 219 220 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size, 221 ArrayRef<uint8_t> Bytes, 222 uint64_t Address, 223 raw_ostream &OS, 224 raw_ostream &CS) const { 225 CommentStream = &CS; 226 227 Size = 0; 228 // We want to read exactly 4 bytes of data. 229 if (Bytes.size() < 4) 230 return Fail; 231 Size = 4; 232 233 // Encoded as a small-endian 32-bit word in the stream. 234 uint32_t Insn = 235 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 236 237 // Calling the auto-generated decoder function. 238 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI); 239 } 240 241 static MCSymbolizer * 242 createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo, 243 LLVMSymbolLookupCallback SymbolLookUp, 244 void *DisInfo, MCContext *Ctx, 245 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 246 return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo, 247 SymbolLookUp, DisInfo); 248 } 249 250 extern "C" void LLVMInitializeAArch64Disassembler() { 251 TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(), 252 createAArch64Disassembler); 253 TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(), 254 createAArch64Disassembler); 255 TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(), 256 createAArch64ExternalSymbolizer); 257 TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(), 258 createAArch64ExternalSymbolizer); 259 260 TargetRegistry::RegisterMCDisassembler(getTheARM64Target(), 261 createAArch64Disassembler); 262 TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(), 263 createAArch64ExternalSymbolizer); 264 } 265 266 static const unsigned FPR128DecoderTable[] = { 267 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 268 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 269 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 270 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 271 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 272 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 273 AArch64::Q30, AArch64::Q31 274 }; 275 276 static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo, 277 uint64_t Addr, 278 const void *Decoder) { 279 if (RegNo > 31) 280 return Fail; 281 282 unsigned Register = FPR128DecoderTable[RegNo]; 283 Inst.addOperand(MCOperand::createReg(Register)); 284 return Success; 285 } 286 287 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, 288 uint64_t Addr, 289 const void *Decoder) { 290 if (RegNo > 15) 291 return Fail; 292 return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder); 293 } 294 295 static const unsigned FPR64DecoderTable[] = { 296 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, 297 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, 298 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, 299 AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, 300 AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, 301 AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, 302 AArch64::D30, AArch64::D31 303 }; 304 305 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo, 306 uint64_t Addr, 307 const void *Decoder) { 308 if (RegNo > 31) 309 return Fail; 310 311 unsigned Register = FPR64DecoderTable[RegNo]; 312 Inst.addOperand(MCOperand::createReg(Register)); 313 return Success; 314 } 315 316 static const unsigned FPR32DecoderTable[] = { 317 AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, 318 AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, 319 AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, 320 AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, 321 AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, 322 AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, 323 AArch64::S30, AArch64::S31 324 }; 325 326 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo, 327 uint64_t Addr, 328 const void *Decoder) { 329 if (RegNo > 31) 330 return Fail; 331 332 unsigned Register = FPR32DecoderTable[RegNo]; 333 Inst.addOperand(MCOperand::createReg(Register)); 334 return Success; 335 } 336 337 static const unsigned FPR16DecoderTable[] = { 338 AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, 339 AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, 340 AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, 341 AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, 342 AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, 343 AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, 344 AArch64::H30, AArch64::H31 345 }; 346 347 static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo, 348 uint64_t Addr, 349 const void *Decoder) { 350 if (RegNo > 31) 351 return Fail; 352 353 unsigned Register = FPR16DecoderTable[RegNo]; 354 Inst.addOperand(MCOperand::createReg(Register)); 355 return Success; 356 } 357 358 static const unsigned FPR8DecoderTable[] = { 359 AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, 360 AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, 361 AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, 362 AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, 363 AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, 364 AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, 365 AArch64::B30, AArch64::B31 366 }; 367 368 static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo, 369 uint64_t Addr, 370 const void *Decoder) { 371 if (RegNo > 31) 372 return Fail; 373 374 unsigned Register = FPR8DecoderTable[RegNo]; 375 Inst.addOperand(MCOperand::createReg(Register)); 376 return Success; 377 } 378 379 static const unsigned GPR64DecoderTable[] = { 380 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, 381 AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, 382 AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, 383 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, 384 AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, 385 AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, 386 AArch64::LR, AArch64::XZR 387 }; 388 389 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo, 390 uint64_t Addr, 391 const void *Decoder) { 392 if (RegNo > 31) 393 return Fail; 394 395 unsigned Register = GPR64DecoderTable[RegNo]; 396 Inst.addOperand(MCOperand::createReg(Register)); 397 return Success; 398 } 399 400 static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo, 401 uint64_t Addr, 402 const void *Decoder) { 403 if (RegNo > 31) 404 return Fail; 405 unsigned Register = GPR64DecoderTable[RegNo]; 406 if (Register == AArch64::XZR) 407 Register = AArch64::SP; 408 Inst.addOperand(MCOperand::createReg(Register)); 409 return Success; 410 } 411 412 static const unsigned GPR32DecoderTable[] = { 413 AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, 414 AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, 415 AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, 416 AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, 417 AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, 418 AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, 419 AArch64::W30, AArch64::WZR 420 }; 421 422 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, 423 uint64_t Addr, 424 const void *Decoder) { 425 if (RegNo > 31) 426 return Fail; 427 428 unsigned Register = GPR32DecoderTable[RegNo]; 429 Inst.addOperand(MCOperand::createReg(Register)); 430 return Success; 431 } 432 433 static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo, 434 uint64_t Addr, 435 const void *Decoder) { 436 if (RegNo > 31) 437 return Fail; 438 439 unsigned Register = GPR32DecoderTable[RegNo]; 440 if (Register == AArch64::WZR) 441 Register = AArch64::WSP; 442 Inst.addOperand(MCOperand::createReg(Register)); 443 return Success; 444 } 445 static const unsigned ZPRDecoderTable[] = { 446 AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, 447 AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, 448 AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, 449 AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, 450 AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, 451 AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, 452 AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, 453 AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31 454 }; 455 456 static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo, 457 uint64_t Address, 458 const void* Decoder) { 459 if (RegNo > 31) 460 return Fail; 461 462 unsigned Register = ZPRDecoderTable[RegNo]; 463 Inst.addOperand(MCOperand::createReg(Register)); 464 return Success; 465 } 466 467 static const unsigned PPRDecoderTable[] = { 468 AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, 469 AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, 470 AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, 471 AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15 472 }; 473 474 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo, 475 uint64_t Addr, const void *Decoder) { 476 if (RegNo > 15) 477 return Fail; 478 479 unsigned Register = PPRDecoderTable[RegNo]; 480 Inst.addOperand(MCOperand::createReg(Register)); 481 return Success; 482 } 483 484 static const unsigned VectorDecoderTable[] = { 485 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, 486 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, 487 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, 488 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, 489 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, 490 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, 491 AArch64::Q30, AArch64::Q31 492 }; 493 494 static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, unsigned RegNo, 495 uint64_t Addr, 496 const void *Decoder) { 497 if (RegNo > 31) 498 return Fail; 499 500 unsigned Register = VectorDecoderTable[RegNo]; 501 Inst.addOperand(MCOperand::createReg(Register)); 502 return Success; 503 } 504 505 static const unsigned QQDecoderTable[] = { 506 AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, 507 AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, 508 AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, 509 AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 510 AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, 511 AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, 512 AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, 513 AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0 514 }; 515 516 static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo, 517 uint64_t Addr, const void *Decoder) { 518 if (RegNo > 31) 519 return Fail; 520 unsigned Register = QQDecoderTable[RegNo]; 521 Inst.addOperand(MCOperand::createReg(Register)); 522 return Success; 523 } 524 525 static const unsigned QQQDecoderTable[] = { 526 AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, 527 AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, 528 AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, 529 AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, 530 AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 531 AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, 532 AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, 533 AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, 534 AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, 535 AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, 536 AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1 537 }; 538 539 static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo, 540 uint64_t Addr, const void *Decoder) { 541 if (RegNo > 31) 542 return Fail; 543 unsigned Register = QQQDecoderTable[RegNo]; 544 Inst.addOperand(MCOperand::createReg(Register)); 545 return Success; 546 } 547 548 static const unsigned QQQQDecoderTable[] = { 549 AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, 550 AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, 551 AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, 552 AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, 553 AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 554 AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, 555 AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, 556 AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, 557 AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, 558 AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, 559 AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2 560 }; 561 562 static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo, 563 uint64_t Addr, 564 const void *Decoder) { 565 if (RegNo > 31) 566 return Fail; 567 unsigned Register = QQQQDecoderTable[RegNo]; 568 Inst.addOperand(MCOperand::createReg(Register)); 569 return Success; 570 } 571 572 static const unsigned DDDecoderTable[] = { 573 AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, 574 AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, 575 AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, 576 AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, 577 AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, 578 AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, 579 AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, 580 AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0 581 }; 582 583 static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo, 584 uint64_t Addr, const void *Decoder) { 585 if (RegNo > 31) 586 return Fail; 587 unsigned Register = DDDecoderTable[RegNo]; 588 Inst.addOperand(MCOperand::createReg(Register)); 589 return Success; 590 } 591 592 static const unsigned DDDDecoderTable[] = { 593 AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, 594 AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, 595 AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, 596 AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, 597 AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, 598 AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, 599 AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, 600 AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, 601 AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, 602 AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, 603 AArch64::D30_D31_D0, AArch64::D31_D0_D1 604 }; 605 606 static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo, 607 uint64_t Addr, const void *Decoder) { 608 if (RegNo > 31) 609 return Fail; 610 unsigned Register = DDDDecoderTable[RegNo]; 611 Inst.addOperand(MCOperand::createReg(Register)); 612 return Success; 613 } 614 615 static const unsigned DDDDDecoderTable[] = { 616 AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, 617 AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, 618 AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, 619 AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, 620 AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, 621 AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, 622 AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, 623 AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, 624 AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, 625 AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, 626 AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2 627 }; 628 629 static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo, 630 uint64_t Addr, 631 const void *Decoder) { 632 if (RegNo > 31) 633 return Fail; 634 unsigned Register = DDDDDecoderTable[RegNo]; 635 Inst.addOperand(MCOperand::createReg(Register)); 636 return Success; 637 } 638 639 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm, 640 uint64_t Addr, 641 const void *Decoder) { 642 // scale{5} is asserted as 1 in tblgen. 643 Imm |= 0x20; 644 Inst.addOperand(MCOperand::createImm(64 - Imm)); 645 return Success; 646 } 647 648 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm, 649 uint64_t Addr, 650 const void *Decoder) { 651 Inst.addOperand(MCOperand::createImm(64 - Imm)); 652 return Success; 653 } 654 655 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm, 656 uint64_t Addr, const void *Decoder) { 657 int64_t ImmVal = Imm; 658 const AArch64Disassembler *Dis = 659 static_cast<const AArch64Disassembler *>(Decoder); 660 661 // Sign-extend 19-bit immediate. 662 if (ImmVal & (1 << (19 - 1))) 663 ImmVal |= ~((1LL << 19) - 1); 664 665 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr, 666 Inst.getOpcode() != AArch64::LDRXl, 0, 4)) 667 Inst.addOperand(MCOperand::createImm(ImmVal)); 668 return Success; 669 } 670 671 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm, 672 uint64_t Address, const void *Decoder) { 673 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1)); 674 Inst.addOperand(MCOperand::createImm(Imm & 1)); 675 return Success; 676 } 677 678 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm, 679 uint64_t Address, 680 const void *Decoder) { 681 Inst.addOperand(MCOperand::createImm(Imm)); 682 683 // Every system register in the encoding space is valid with the syntax 684 // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds. 685 return Success; 686 } 687 688 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm, 689 uint64_t Address, 690 const void *Decoder) { 691 Inst.addOperand(MCOperand::createImm(Imm)); 692 693 return Success; 694 } 695 696 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn, 697 uint64_t Address, 698 const void *Decoder) { 699 // This decoder exists to add the dummy Lane operand to the MCInst, which must 700 // be 1 in assembly but has no other real manifestation. 701 unsigned Rd = fieldFromInstruction(Insn, 0, 5); 702 unsigned Rn = fieldFromInstruction(Insn, 5, 5); 703 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); 704 705 if (IsToVec) { 706 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 707 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); 708 } else { 709 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 710 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); 711 } 712 713 // Add the lane 714 Inst.addOperand(MCOperand::createImm(1)); 715 716 return Success; 717 } 718 719 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm, 720 unsigned Add) { 721 Inst.addOperand(MCOperand::createImm(Add - Imm)); 722 return Success; 723 } 724 725 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm, 726 unsigned Add) { 727 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1))); 728 return Success; 729 } 730 731 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm, 732 uint64_t Addr, const void *Decoder) { 733 return DecodeVecShiftRImm(Inst, Imm, 64); 734 } 735 736 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm, 737 uint64_t Addr, 738 const void *Decoder) { 739 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); 740 } 741 742 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm, 743 uint64_t Addr, const void *Decoder) { 744 return DecodeVecShiftRImm(Inst, Imm, 32); 745 } 746 747 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm, 748 uint64_t Addr, 749 const void *Decoder) { 750 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); 751 } 752 753 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm, 754 uint64_t Addr, const void *Decoder) { 755 return DecodeVecShiftRImm(Inst, Imm, 16); 756 } 757 758 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm, 759 uint64_t Addr, 760 const void *Decoder) { 761 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); 762 } 763 764 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm, 765 uint64_t Addr, const void *Decoder) { 766 return DecodeVecShiftRImm(Inst, Imm, 8); 767 } 768 769 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm, 770 uint64_t Addr, const void *Decoder) { 771 return DecodeVecShiftLImm(Inst, Imm, 64); 772 } 773 774 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm, 775 uint64_t Addr, const void *Decoder) { 776 return DecodeVecShiftLImm(Inst, Imm, 32); 777 } 778 779 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm, 780 uint64_t Addr, const void *Decoder) { 781 return DecodeVecShiftLImm(Inst, Imm, 16); 782 } 783 784 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm, 785 uint64_t Addr, const void *Decoder) { 786 return DecodeVecShiftLImm(Inst, Imm, 8); 787 } 788 789 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, 790 uint64_t Addr, 791 const void *Decoder) { 792 unsigned Rd = fieldFromInstruction(insn, 0, 5); 793 unsigned Rn = fieldFromInstruction(insn, 5, 5); 794 unsigned Rm = fieldFromInstruction(insn, 16, 5); 795 unsigned shiftHi = fieldFromInstruction(insn, 22, 2); 796 unsigned shiftLo = fieldFromInstruction(insn, 10, 6); 797 unsigned shift = (shiftHi << 6) | shiftLo; 798 switch (Inst.getOpcode()) { 799 default: 800 return Fail; 801 case AArch64::ADDWrs: 802 case AArch64::ADDSWrs: 803 case AArch64::SUBWrs: 804 case AArch64::SUBSWrs: 805 // if shift == '11' then ReservedValue() 806 if (shiftHi == 0x3) 807 return Fail; 808 LLVM_FALLTHROUGH; 809 case AArch64::ANDWrs: 810 case AArch64::ANDSWrs: 811 case AArch64::BICWrs: 812 case AArch64::BICSWrs: 813 case AArch64::ORRWrs: 814 case AArch64::ORNWrs: 815 case AArch64::EORWrs: 816 case AArch64::EONWrs: { 817 // if sf == '0' and imm6<5> == '1' then ReservedValue() 818 if (shiftLo >> 5 == 1) 819 return Fail; 820 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 821 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 822 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 823 break; 824 } 825 case AArch64::ADDXrs: 826 case AArch64::ADDSXrs: 827 case AArch64::SUBXrs: 828 case AArch64::SUBSXrs: 829 // if shift == '11' then ReservedValue() 830 if (shiftHi == 0x3) 831 return Fail; 832 LLVM_FALLTHROUGH; 833 case AArch64::ANDXrs: 834 case AArch64::ANDSXrs: 835 case AArch64::BICXrs: 836 case AArch64::BICSXrs: 837 case AArch64::ORRXrs: 838 case AArch64::ORNXrs: 839 case AArch64::EORXrs: 840 case AArch64::EONXrs: 841 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 842 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 843 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 844 break; 845 } 846 847 Inst.addOperand(MCOperand::createImm(shift)); 848 return Success; 849 } 850 851 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn, 852 uint64_t Addr, 853 const void *Decoder) { 854 unsigned Rd = fieldFromInstruction(insn, 0, 5); 855 unsigned imm = fieldFromInstruction(insn, 5, 16); 856 unsigned shift = fieldFromInstruction(insn, 21, 2); 857 shift <<= 4; 858 switch (Inst.getOpcode()) { 859 default: 860 return Fail; 861 case AArch64::MOVZWi: 862 case AArch64::MOVNWi: 863 case AArch64::MOVKWi: 864 if (shift & (1U << 5)) 865 return Fail; 866 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 867 break; 868 case AArch64::MOVZXi: 869 case AArch64::MOVNXi: 870 case AArch64::MOVKXi: 871 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 872 break; 873 } 874 875 if (Inst.getOpcode() == AArch64::MOVKWi || 876 Inst.getOpcode() == AArch64::MOVKXi) 877 Inst.addOperand(Inst.getOperand(0)); 878 879 Inst.addOperand(MCOperand::createImm(imm)); 880 Inst.addOperand(MCOperand::createImm(shift)); 881 return Success; 882 } 883 884 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, 885 uint64_t Addr, 886 const void *Decoder) { 887 unsigned Rt = fieldFromInstruction(insn, 0, 5); 888 unsigned Rn = fieldFromInstruction(insn, 5, 5); 889 unsigned offset = fieldFromInstruction(insn, 10, 12); 890 const AArch64Disassembler *Dis = 891 static_cast<const AArch64Disassembler *>(Decoder); 892 893 switch (Inst.getOpcode()) { 894 default: 895 return Fail; 896 case AArch64::PRFMui: 897 // Rt is an immediate in prefetch. 898 Inst.addOperand(MCOperand::createImm(Rt)); 899 break; 900 case AArch64::STRBBui: 901 case AArch64::LDRBBui: 902 case AArch64::LDRSBWui: 903 case AArch64::STRHHui: 904 case AArch64::LDRHHui: 905 case AArch64::LDRSHWui: 906 case AArch64::STRWui: 907 case AArch64::LDRWui: 908 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 909 break; 910 case AArch64::LDRSBXui: 911 case AArch64::LDRSHXui: 912 case AArch64::LDRSWui: 913 case AArch64::STRXui: 914 case AArch64::LDRXui: 915 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 916 break; 917 case AArch64::LDRQui: 918 case AArch64::STRQui: 919 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 920 break; 921 case AArch64::LDRDui: 922 case AArch64::STRDui: 923 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 924 break; 925 case AArch64::LDRSui: 926 case AArch64::STRSui: 927 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 928 break; 929 case AArch64::LDRHui: 930 case AArch64::STRHui: 931 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 932 break; 933 case AArch64::LDRBui: 934 case AArch64::STRBui: 935 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 936 break; 937 } 938 939 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 940 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) 941 Inst.addOperand(MCOperand::createImm(offset)); 942 return Success; 943 } 944 945 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn, 946 uint64_t Addr, 947 const void *Decoder) { 948 unsigned Rt = fieldFromInstruction(insn, 0, 5); 949 unsigned Rn = fieldFromInstruction(insn, 5, 5); 950 int64_t offset = fieldFromInstruction(insn, 12, 9); 951 952 // offset is a 9-bit signed immediate, so sign extend it to 953 // fill the unsigned. 954 if (offset & (1 << (9 - 1))) 955 offset |= ~((1LL << 9) - 1); 956 957 // First operand is always the writeback to the address register, if needed. 958 switch (Inst.getOpcode()) { 959 default: 960 break; 961 case AArch64::LDRSBWpre: 962 case AArch64::LDRSHWpre: 963 case AArch64::STRBBpre: 964 case AArch64::LDRBBpre: 965 case AArch64::STRHHpre: 966 case AArch64::LDRHHpre: 967 case AArch64::STRWpre: 968 case AArch64::LDRWpre: 969 case AArch64::LDRSBWpost: 970 case AArch64::LDRSHWpost: 971 case AArch64::STRBBpost: 972 case AArch64::LDRBBpost: 973 case AArch64::STRHHpost: 974 case AArch64::LDRHHpost: 975 case AArch64::STRWpost: 976 case AArch64::LDRWpost: 977 case AArch64::LDRSBXpre: 978 case AArch64::LDRSHXpre: 979 case AArch64::STRXpre: 980 case AArch64::LDRSWpre: 981 case AArch64::LDRXpre: 982 case AArch64::LDRSBXpost: 983 case AArch64::LDRSHXpost: 984 case AArch64::STRXpost: 985 case AArch64::LDRSWpost: 986 case AArch64::LDRXpost: 987 case AArch64::LDRQpre: 988 case AArch64::STRQpre: 989 case AArch64::LDRQpost: 990 case AArch64::STRQpost: 991 case AArch64::LDRDpre: 992 case AArch64::STRDpre: 993 case AArch64::LDRDpost: 994 case AArch64::STRDpost: 995 case AArch64::LDRSpre: 996 case AArch64::STRSpre: 997 case AArch64::LDRSpost: 998 case AArch64::STRSpost: 999 case AArch64::LDRHpre: 1000 case AArch64::STRHpre: 1001 case AArch64::LDRHpost: 1002 case AArch64::STRHpost: 1003 case AArch64::LDRBpre: 1004 case AArch64::STRBpre: 1005 case AArch64::LDRBpost: 1006 case AArch64::STRBpost: 1007 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1008 break; 1009 } 1010 1011 switch (Inst.getOpcode()) { 1012 default: 1013 return Fail; 1014 case AArch64::PRFUMi: 1015 // Rt is an immediate in prefetch. 1016 Inst.addOperand(MCOperand::createImm(Rt)); 1017 break; 1018 case AArch64::STURBBi: 1019 case AArch64::LDURBBi: 1020 case AArch64::LDURSBWi: 1021 case AArch64::STURHHi: 1022 case AArch64::LDURHHi: 1023 case AArch64::LDURSHWi: 1024 case AArch64::STURWi: 1025 case AArch64::LDURWi: 1026 case AArch64::LDTRSBWi: 1027 case AArch64::LDTRSHWi: 1028 case AArch64::STTRWi: 1029 case AArch64::LDTRWi: 1030 case AArch64::STTRHi: 1031 case AArch64::LDTRHi: 1032 case AArch64::LDTRBi: 1033 case AArch64::STTRBi: 1034 case AArch64::LDRSBWpre: 1035 case AArch64::LDRSHWpre: 1036 case AArch64::STRBBpre: 1037 case AArch64::LDRBBpre: 1038 case AArch64::STRHHpre: 1039 case AArch64::LDRHHpre: 1040 case AArch64::STRWpre: 1041 case AArch64::LDRWpre: 1042 case AArch64::LDRSBWpost: 1043 case AArch64::LDRSHWpost: 1044 case AArch64::STRBBpost: 1045 case AArch64::LDRBBpost: 1046 case AArch64::STRHHpost: 1047 case AArch64::LDRHHpost: 1048 case AArch64::STRWpost: 1049 case AArch64::LDRWpost: 1050 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1051 break; 1052 case AArch64::LDURSBXi: 1053 case AArch64::LDURSHXi: 1054 case AArch64::LDURSWi: 1055 case AArch64::STURXi: 1056 case AArch64::LDURXi: 1057 case AArch64::LDTRSBXi: 1058 case AArch64::LDTRSHXi: 1059 case AArch64::LDTRSWi: 1060 case AArch64::STTRXi: 1061 case AArch64::LDTRXi: 1062 case AArch64::LDRSBXpre: 1063 case AArch64::LDRSHXpre: 1064 case AArch64::STRXpre: 1065 case AArch64::LDRSWpre: 1066 case AArch64::LDRXpre: 1067 case AArch64::LDRSBXpost: 1068 case AArch64::LDRSHXpost: 1069 case AArch64::STRXpost: 1070 case AArch64::LDRSWpost: 1071 case AArch64::LDRXpost: 1072 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1073 break; 1074 case AArch64::LDURQi: 1075 case AArch64::STURQi: 1076 case AArch64::LDRQpre: 1077 case AArch64::STRQpre: 1078 case AArch64::LDRQpost: 1079 case AArch64::STRQpost: 1080 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1081 break; 1082 case AArch64::LDURDi: 1083 case AArch64::STURDi: 1084 case AArch64::LDRDpre: 1085 case AArch64::STRDpre: 1086 case AArch64::LDRDpost: 1087 case AArch64::STRDpost: 1088 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1089 break; 1090 case AArch64::LDURSi: 1091 case AArch64::STURSi: 1092 case AArch64::LDRSpre: 1093 case AArch64::STRSpre: 1094 case AArch64::LDRSpost: 1095 case AArch64::STRSpost: 1096 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1097 break; 1098 case AArch64::LDURHi: 1099 case AArch64::STURHi: 1100 case AArch64::LDRHpre: 1101 case AArch64::STRHpre: 1102 case AArch64::LDRHpost: 1103 case AArch64::STRHpost: 1104 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); 1105 break; 1106 case AArch64::LDURBi: 1107 case AArch64::STURBi: 1108 case AArch64::LDRBpre: 1109 case AArch64::STRBpre: 1110 case AArch64::LDRBpost: 1111 case AArch64::STRBpost: 1112 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); 1113 break; 1114 } 1115 1116 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1117 Inst.addOperand(MCOperand::createImm(offset)); 1118 1119 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1120 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; 1121 bool IsFP = fieldFromInstruction(insn, 26, 1); 1122 1123 // Cannot write back to a transfer register (but xzr != sp). 1124 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) 1125 return SoftFail; 1126 1127 return Success; 1128 } 1129 1130 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, 1131 uint64_t Addr, 1132 const void *Decoder) { 1133 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1134 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1135 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1136 unsigned Rs = fieldFromInstruction(insn, 16, 5); 1137 1138 unsigned Opcode = Inst.getOpcode(); 1139 switch (Opcode) { 1140 default: 1141 return Fail; 1142 case AArch64::STLXRW: 1143 case AArch64::STLXRB: 1144 case AArch64::STLXRH: 1145 case AArch64::STXRW: 1146 case AArch64::STXRB: 1147 case AArch64::STXRH: 1148 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1149 LLVM_FALLTHROUGH; 1150 case AArch64::LDARW: 1151 case AArch64::LDARB: 1152 case AArch64::LDARH: 1153 case AArch64::LDAXRW: 1154 case AArch64::LDAXRB: 1155 case AArch64::LDAXRH: 1156 case AArch64::LDXRW: 1157 case AArch64::LDXRB: 1158 case AArch64::LDXRH: 1159 case AArch64::STLRW: 1160 case AArch64::STLRB: 1161 case AArch64::STLRH: 1162 case AArch64::STLLRW: 1163 case AArch64::STLLRB: 1164 case AArch64::STLLRH: 1165 case AArch64::LDLARW: 1166 case AArch64::LDLARB: 1167 case AArch64::LDLARH: 1168 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1169 break; 1170 case AArch64::STLXRX: 1171 case AArch64::STXRX: 1172 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1173 LLVM_FALLTHROUGH; 1174 case AArch64::LDARX: 1175 case AArch64::LDAXRX: 1176 case AArch64::LDXRX: 1177 case AArch64::STLRX: 1178 case AArch64::LDLARX: 1179 case AArch64::STLLRX: 1180 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1181 break; 1182 case AArch64::STLXPW: 1183 case AArch64::STXPW: 1184 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1185 LLVM_FALLTHROUGH; 1186 case AArch64::LDAXPW: 1187 case AArch64::LDXPW: 1188 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1189 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1190 break; 1191 case AArch64::STLXPX: 1192 case AArch64::STXPX: 1193 DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); 1194 LLVM_FALLTHROUGH; 1195 case AArch64::LDAXPX: 1196 case AArch64::LDXPX: 1197 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1198 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1199 break; 1200 } 1201 1202 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1203 1204 // You shouldn't load to the same register twice in an instruction... 1205 if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW || 1206 Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) && 1207 Rt == Rt2) 1208 return SoftFail; 1209 1210 return Success; 1211 } 1212 1213 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn, 1214 uint64_t Addr, 1215 const void *Decoder) { 1216 unsigned Rt = fieldFromInstruction(insn, 0, 5); 1217 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1218 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); 1219 int64_t offset = fieldFromInstruction(insn, 15, 7); 1220 bool IsLoad = fieldFromInstruction(insn, 22, 1); 1221 1222 // offset is a 7-bit signed immediate, so sign extend it to 1223 // fill the unsigned. 1224 if (offset & (1 << (7 - 1))) 1225 offset |= ~((1LL << 7) - 1); 1226 1227 unsigned Opcode = Inst.getOpcode(); 1228 bool NeedsDisjointWritebackTransfer = false; 1229 1230 // First operand is always writeback of base register. 1231 switch (Opcode) { 1232 default: 1233 break; 1234 case AArch64::LDPXpost: 1235 case AArch64::STPXpost: 1236 case AArch64::LDPSWpost: 1237 case AArch64::LDPXpre: 1238 case AArch64::STPXpre: 1239 case AArch64::LDPSWpre: 1240 case AArch64::LDPWpost: 1241 case AArch64::STPWpost: 1242 case AArch64::LDPWpre: 1243 case AArch64::STPWpre: 1244 case AArch64::LDPQpost: 1245 case AArch64::STPQpost: 1246 case AArch64::LDPQpre: 1247 case AArch64::STPQpre: 1248 case AArch64::LDPDpost: 1249 case AArch64::STPDpost: 1250 case AArch64::LDPDpre: 1251 case AArch64::STPDpre: 1252 case AArch64::LDPSpost: 1253 case AArch64::STPSpost: 1254 case AArch64::LDPSpre: 1255 case AArch64::STPSpre: 1256 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1257 break; 1258 } 1259 1260 switch (Opcode) { 1261 default: 1262 return Fail; 1263 case AArch64::LDPXpost: 1264 case AArch64::STPXpost: 1265 case AArch64::LDPSWpost: 1266 case AArch64::LDPXpre: 1267 case AArch64::STPXpre: 1268 case AArch64::LDPSWpre: 1269 NeedsDisjointWritebackTransfer = true; 1270 LLVM_FALLTHROUGH; 1271 case AArch64::LDNPXi: 1272 case AArch64::STNPXi: 1273 case AArch64::LDPXi: 1274 case AArch64::STPXi: 1275 case AArch64::LDPSWi: 1276 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1277 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1278 break; 1279 case AArch64::LDPWpost: 1280 case AArch64::STPWpost: 1281 case AArch64::LDPWpre: 1282 case AArch64::STPWpre: 1283 NeedsDisjointWritebackTransfer = true; 1284 LLVM_FALLTHROUGH; 1285 case AArch64::LDNPWi: 1286 case AArch64::STNPWi: 1287 case AArch64::LDPWi: 1288 case AArch64::STPWi: 1289 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1290 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1291 break; 1292 case AArch64::LDNPQi: 1293 case AArch64::STNPQi: 1294 case AArch64::LDPQpost: 1295 case AArch64::STPQpost: 1296 case AArch64::LDPQi: 1297 case AArch64::STPQi: 1298 case AArch64::LDPQpre: 1299 case AArch64::STPQpre: 1300 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); 1301 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); 1302 break; 1303 case AArch64::LDNPDi: 1304 case AArch64::STNPDi: 1305 case AArch64::LDPDpost: 1306 case AArch64::STPDpost: 1307 case AArch64::LDPDi: 1308 case AArch64::STPDi: 1309 case AArch64::LDPDpre: 1310 case AArch64::STPDpre: 1311 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); 1312 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); 1313 break; 1314 case AArch64::LDNPSi: 1315 case AArch64::STNPSi: 1316 case AArch64::LDPSpost: 1317 case AArch64::STPSpost: 1318 case AArch64::LDPSi: 1319 case AArch64::STPSi: 1320 case AArch64::LDPSpre: 1321 case AArch64::STPSpre: 1322 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); 1323 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); 1324 break; 1325 } 1326 1327 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1328 Inst.addOperand(MCOperand::createImm(offset)); 1329 1330 // You shouldn't load to the same register twice in an instruction... 1331 if (IsLoad && Rt == Rt2) 1332 return SoftFail; 1333 1334 // ... or do any operation that writes-back to a transfer register. But note 1335 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different. 1336 if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn)) 1337 return SoftFail; 1338 1339 return Success; 1340 } 1341 1342 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn, 1343 uint64_t Addr, 1344 const void *Decoder) { 1345 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1346 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1347 unsigned Rm = fieldFromInstruction(insn, 16, 5); 1348 unsigned extend = fieldFromInstruction(insn, 10, 6); 1349 1350 unsigned shift = extend & 0x7; 1351 if (shift > 4) 1352 return Fail; 1353 1354 switch (Inst.getOpcode()) { 1355 default: 1356 return Fail; 1357 case AArch64::ADDWrx: 1358 case AArch64::SUBWrx: 1359 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1360 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1361 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1362 break; 1363 case AArch64::ADDSWrx: 1364 case AArch64::SUBSWrx: 1365 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1366 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1367 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1368 break; 1369 case AArch64::ADDXrx: 1370 case AArch64::SUBXrx: 1371 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1372 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1373 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1374 break; 1375 case AArch64::ADDSXrx: 1376 case AArch64::SUBSXrx: 1377 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1378 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1379 DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); 1380 break; 1381 case AArch64::ADDXrx64: 1382 case AArch64::SUBXrx64: 1383 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1384 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1385 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1386 break; 1387 case AArch64::SUBSXrx64: 1388 case AArch64::ADDSXrx64: 1389 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1390 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1391 DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); 1392 break; 1393 } 1394 1395 Inst.addOperand(MCOperand::createImm(extend)); 1396 return Success; 1397 } 1398 1399 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn, 1400 uint64_t Addr, 1401 const void *Decoder) { 1402 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1403 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1404 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1405 unsigned imm; 1406 1407 if (Datasize) { 1408 if (Inst.getOpcode() == AArch64::ANDSXri) 1409 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1410 else 1411 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1412 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); 1413 imm = fieldFromInstruction(insn, 10, 13); 1414 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) 1415 return Fail; 1416 } else { 1417 if (Inst.getOpcode() == AArch64::ANDSWri) 1418 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1419 else 1420 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1421 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); 1422 imm = fieldFromInstruction(insn, 10, 12); 1423 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32)) 1424 return Fail; 1425 } 1426 Inst.addOperand(MCOperand::createImm(imm)); 1427 return Success; 1428 } 1429 1430 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn, 1431 uint64_t Addr, 1432 const void *Decoder) { 1433 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1434 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1435 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1436 imm |= fieldFromInstruction(insn, 5, 5); 1437 1438 if (Inst.getOpcode() == AArch64::MOVID) 1439 DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); 1440 else 1441 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1442 1443 Inst.addOperand(MCOperand::createImm(imm)); 1444 1445 switch (Inst.getOpcode()) { 1446 default: 1447 break; 1448 case AArch64::MOVIv4i16: 1449 case AArch64::MOVIv8i16: 1450 case AArch64::MVNIv4i16: 1451 case AArch64::MVNIv8i16: 1452 case AArch64::MOVIv2i32: 1453 case AArch64::MOVIv4i32: 1454 case AArch64::MVNIv2i32: 1455 case AArch64::MVNIv4i32: 1456 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1457 break; 1458 case AArch64::MOVIv2s_msl: 1459 case AArch64::MOVIv4s_msl: 1460 case AArch64::MVNIv2s_msl: 1461 case AArch64::MVNIv4s_msl: 1462 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108)); 1463 break; 1464 } 1465 1466 return Success; 1467 } 1468 1469 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn, 1470 uint64_t Addr, 1471 const void *Decoder) { 1472 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1473 unsigned cmode = fieldFromInstruction(insn, 12, 4); 1474 unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; 1475 imm |= fieldFromInstruction(insn, 5, 5); 1476 1477 // Tied operands added twice. 1478 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1479 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); 1480 1481 Inst.addOperand(MCOperand::createImm(imm)); 1482 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2)); 1483 1484 return Success; 1485 } 1486 1487 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn, 1488 uint64_t Addr, const void *Decoder) { 1489 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1490 int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; 1491 imm |= fieldFromInstruction(insn, 29, 2); 1492 const AArch64Disassembler *Dis = 1493 static_cast<const AArch64Disassembler *>(Decoder); 1494 1495 // Sign-extend the 21-bit immediate. 1496 if (imm & (1 << (21 - 1))) 1497 imm |= ~((1LL << 21) - 1); 1498 1499 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1500 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4)) 1501 Inst.addOperand(MCOperand::createImm(imm)); 1502 1503 return Success; 1504 } 1505 1506 static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn, 1507 uint64_t Addr, const void *Decoder) { 1508 unsigned Rd = fieldFromInstruction(insn, 0, 5); 1509 unsigned Rn = fieldFromInstruction(insn, 5, 5); 1510 unsigned Imm = fieldFromInstruction(insn, 10, 14); 1511 unsigned S = fieldFromInstruction(insn, 29, 1); 1512 unsigned Datasize = fieldFromInstruction(insn, 31, 1); 1513 1514 unsigned ShifterVal = (Imm >> 12) & 3; 1515 unsigned ImmVal = Imm & 0xFFF; 1516 const AArch64Disassembler *Dis = 1517 static_cast<const AArch64Disassembler *>(Decoder); 1518 1519 if (ShifterVal != 0 && ShifterVal != 1) 1520 return Fail; 1521 1522 if (Datasize) { 1523 if (Rd == 31 && !S) 1524 DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); 1525 else 1526 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1527 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); 1528 } else { 1529 if (Rd == 31 && !S) 1530 DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); 1531 else 1532 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 1533 DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); 1534 } 1535 1536 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) 1537 Inst.addOperand(MCOperand::createImm(ImmVal)); 1538 Inst.addOperand(MCOperand::createImm(12 * ShifterVal)); 1539 return Success; 1540 } 1541 1542 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn, 1543 uint64_t Addr, 1544 const void *Decoder) { 1545 int64_t imm = fieldFromInstruction(insn, 0, 26); 1546 const AArch64Disassembler *Dis = 1547 static_cast<const AArch64Disassembler *>(Decoder); 1548 1549 // Sign-extend the 26-bit immediate. 1550 if (imm & (1 << (26 - 1))) 1551 imm |= ~((1LL << 26) - 1); 1552 1553 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4)) 1554 Inst.addOperand(MCOperand::createImm(imm)); 1555 1556 return Success; 1557 } 1558 1559 static DecodeStatus DecodeSystemPStateInstruction(MCInst &Inst, uint32_t insn, 1560 uint64_t Addr, 1561 const void *Decoder) { 1562 uint64_t op1 = fieldFromInstruction(insn, 16, 3); 1563 uint64_t op2 = fieldFromInstruction(insn, 5, 3); 1564 uint64_t crm = fieldFromInstruction(insn, 8, 4); 1565 1566 uint64_t pstate_field = (op1 << 3) | op2; 1567 1568 if ((pstate_field == AArch64PState::PAN || 1569 pstate_field == AArch64PState::UAO) && crm > 1) 1570 return Fail; 1571 1572 Inst.addOperand(MCOperand::createImm(pstate_field)); 1573 Inst.addOperand(MCOperand::createImm(crm)); 1574 1575 const AArch64Disassembler *Dis = 1576 static_cast<const AArch64Disassembler *>(Decoder); 1577 auto PState = AArch64PState::lookupPStateByEncoding(pstate_field); 1578 if (PState && PState->haveFeatures(Dis->getSubtargetInfo().getFeatureBits())) 1579 return Success; 1580 return Fail; 1581 } 1582 1583 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn, 1584 uint64_t Addr, const void *Decoder) { 1585 uint64_t Rt = fieldFromInstruction(insn, 0, 5); 1586 uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5; 1587 bit |= fieldFromInstruction(insn, 19, 5); 1588 int64_t dst = fieldFromInstruction(insn, 5, 14); 1589 const AArch64Disassembler *Dis = 1590 static_cast<const AArch64Disassembler *>(Decoder); 1591 1592 // Sign-extend 14-bit immediate. 1593 if (dst & (1 << (14 - 1))) 1594 dst |= ~((1LL << 14) - 1); 1595 1596 if (fieldFromInstruction(insn, 31, 1) == 0) 1597 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); 1598 else 1599 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); 1600 Inst.addOperand(MCOperand::createImm(bit)); 1601 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4)) 1602 Inst.addOperand(MCOperand::createImm(dst)); 1603 1604 return Success; 1605 } 1606 1607 static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, 1608 unsigned RegClassID, 1609 unsigned RegNo, 1610 uint64_t Addr, 1611 const void *Decoder) { 1612 // Register number must be even (see CASP instruction) 1613 if (RegNo & 0x1) 1614 return Fail; 1615 1616 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); 1617 Inst.addOperand(MCOperand::createReg(Register)); 1618 return Success; 1619 } 1620 1621 static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst &Inst, 1622 unsigned RegNo, 1623 uint64_t Addr, 1624 const void *Decoder) { 1625 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1626 AArch64::WSeqPairsClassRegClassID, 1627 RegNo, Addr, Decoder); 1628 } 1629 1630 static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, 1631 unsigned RegNo, 1632 uint64_t Addr, 1633 const void *Decoder) { 1634 return DecodeGPRSeqPairsClassRegisterClass(Inst, 1635 AArch64::XSeqPairsClassRegClassID, 1636 RegNo, Addr, Decoder); 1637 } 1638 1639 template<int Bits> 1640 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, 1641 uint64_t Address, const void *Decoder) { 1642 if (Imm & ~((1LL << Bits) - 1)) 1643 return Fail; 1644 1645 // Imm is a signed immediate, so sign extend it. 1646 if (Imm & (1 << (Bits - 1))) 1647 Imm |= ~((1LL << Bits) - 1); 1648 1649 Inst.addOperand(MCOperand::createImm(Imm)); 1650 return Success; 1651 } 1652 1653