1 //===- AArch64LegalizerInfo.cpp ----------------------------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the targeting of the Machinelegalizer class for 11 /// AArch64. 12 /// \todo This should be generated by TableGen. 13 //===----------------------------------------------------------------------===// 14 15 #include "AArch64LegalizerInfo.h" 16 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 17 #include "llvm/CodeGen/MachineInstr.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/CodeGen/ValueTypes.h" 20 #include "llvm/IR/DerivedTypes.h" 21 #include "llvm/IR/Type.h" 22 #include "llvm/Target/TargetOpcodes.h" 23 24 using namespace llvm; 25 26 #ifndef LLVM_BUILD_GLOBAL_ISEL 27 #error "You shouldn't build this" 28 #endif 29 30 AArch64LegalizerInfo::AArch64LegalizerInfo() { 31 using namespace TargetOpcode; 32 const LLT p0 = LLT::pointer(0, 64); 33 const LLT s1 = LLT::scalar(1); 34 const LLT s8 = LLT::scalar(8); 35 const LLT s16 = LLT::scalar(16); 36 const LLT s32 = LLT::scalar(32); 37 const LLT s64 = LLT::scalar(64); 38 const LLT v2s32 = LLT::vector(2, 32); 39 const LLT v4s32 = LLT::vector(4, 32); 40 const LLT v2s64 = LLT::vector(2, 64); 41 42 for (auto Ty : {p0, s1, s8, s16, s32, s64}) 43 setAction({G_IMPLICIT_DEF, Ty}, Legal); 44 45 for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SHL}) { 46 // These operations naturally get the right answer when used on 47 // GPR32, even if the actual type is narrower. 48 for (auto Ty : {s32, s64, v2s32, v4s32, v2s64}) 49 setAction({BinOp, Ty}, Legal); 50 51 for (auto Ty : {s1, s8, s16}) 52 setAction({BinOp, Ty}, WidenScalar); 53 } 54 55 setAction({G_GEP, p0}, Legal); 56 setAction({G_GEP, 1, s64}, Legal); 57 58 for (auto Ty : {s1, s8, s16, s32}) 59 setAction({G_GEP, 1, Ty}, WidenScalar); 60 61 setAction({G_PTR_MASK, p0}, Legal); 62 63 for (unsigned BinOp : {G_LSHR, G_ASHR, G_SDIV, G_UDIV}) { 64 for (auto Ty : {s32, s64}) 65 setAction({BinOp, Ty}, Legal); 66 67 for (auto Ty : {s1, s8, s16}) 68 setAction({BinOp, Ty}, WidenScalar); 69 } 70 71 for (unsigned BinOp : {G_SREM, G_UREM}) 72 for (auto Ty : { s1, s8, s16, s32, s64 }) 73 setAction({BinOp, Ty}, Lower); 74 75 for (unsigned Op : {G_SMULO, G_UMULO}) 76 setAction({Op, s64}, Lower); 77 78 for (unsigned Op : {G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_SMULH, G_UMULH}) { 79 for (auto Ty : { s32, s64 }) 80 setAction({Op, Ty}, Legal); 81 82 setAction({Op, 1, s1}, Legal); 83 } 84 85 for (unsigned BinOp : {G_FADD, G_FSUB, G_FMA, G_FMUL, G_FDIV}) 86 for (auto Ty : {s32, s64}) 87 setAction({BinOp, Ty}, Legal); 88 89 for (unsigned BinOp : {G_FREM, G_FPOW}) { 90 setAction({BinOp, s32}, Libcall); 91 setAction({BinOp, s64}, Libcall); 92 } 93 94 for (auto Ty : {s32, s64, p0}) { 95 setAction({G_INSERT, Ty}, Legal); 96 setAction({G_INSERT, 1, Ty}, Legal); 97 } 98 for (auto Ty : {s1, s8, s16}) { 99 setAction({G_INSERT, Ty}, WidenScalar); 100 setAction({G_INSERT, 1, Ty}, Legal); 101 // FIXME: Can't widen the sources because that violates the constraints on 102 // G_INSERT (It seems entirely reasonable that inputs shouldn't overlap). 103 } 104 105 for (auto Ty : {s1, s8, s16, s32, s64, p0}) 106 setAction({G_EXTRACT, Ty}, Legal); 107 108 for (auto Ty : {s32, s64}) 109 setAction({G_EXTRACT, 1, Ty}, Legal); 110 111 for (unsigned MemOp : {G_LOAD, G_STORE}) { 112 for (auto Ty : {s8, s16, s32, s64, p0, v2s32}) 113 setAction({MemOp, Ty}, Legal); 114 115 setAction({MemOp, s1}, WidenScalar); 116 117 // And everything's fine in addrspace 0. 118 setAction({MemOp, 1, p0}, Legal); 119 } 120 121 // Constants 122 for (auto Ty : {s32, s64}) { 123 setAction({TargetOpcode::G_CONSTANT, Ty}, Legal); 124 setAction({TargetOpcode::G_FCONSTANT, Ty}, Legal); 125 } 126 127 setAction({G_CONSTANT, p0}, Legal); 128 129 for (auto Ty : {s1, s8, s16}) 130 setAction({TargetOpcode::G_CONSTANT, Ty}, WidenScalar); 131 132 setAction({TargetOpcode::G_FCONSTANT, s16}, WidenScalar); 133 134 setAction({G_ICMP, s1}, Legal); 135 setAction({G_ICMP, 1, s32}, Legal); 136 setAction({G_ICMP, 1, s64}, Legal); 137 setAction({G_ICMP, 1, p0}, Legal); 138 139 for (auto Ty : {s1, s8, s16}) { 140 setAction({G_ICMP, 1, Ty}, WidenScalar); 141 } 142 143 setAction({G_FCMP, s1}, Legal); 144 setAction({G_FCMP, 1, s32}, Legal); 145 setAction({G_FCMP, 1, s64}, Legal); 146 147 // Extensions 148 for (auto Ty : { s1, s8, s16, s32, s64 }) { 149 setAction({G_ZEXT, Ty}, Legal); 150 setAction({G_SEXT, Ty}, Legal); 151 setAction({G_ANYEXT, Ty}, Legal); 152 } 153 154 for (auto Ty : { s1, s8, s16, s32 }) { 155 setAction({G_ZEXT, 1, Ty}, Legal); 156 setAction({G_SEXT, 1, Ty}, Legal); 157 setAction({G_ANYEXT, 1, Ty}, Legal); 158 } 159 160 setAction({G_FPEXT, s64}, Legal); 161 setAction({G_FPEXT, 1, s32}, Legal); 162 163 // Truncations 164 for (auto Ty : { s16, s32 }) 165 setAction({G_FPTRUNC, Ty}, Legal); 166 167 for (auto Ty : { s32, s64 }) 168 setAction({G_FPTRUNC, 1, Ty}, Legal); 169 170 for (auto Ty : { s1, s8, s16, s32 }) 171 setAction({G_TRUNC, Ty}, Legal); 172 173 for (auto Ty : { s8, s16, s32, s64 }) 174 setAction({G_TRUNC, 1, Ty}, Legal); 175 176 // Conversions 177 for (auto Ty : { s32, s64 }) { 178 setAction({G_FPTOSI, 0, Ty}, Legal); 179 setAction({G_FPTOUI, 0, Ty}, Legal); 180 setAction({G_SITOFP, 1, Ty}, Legal); 181 setAction({G_UITOFP, 1, Ty}, Legal); 182 } 183 for (auto Ty : { s1, s8, s16 }) { 184 setAction({G_FPTOSI, 0, Ty}, WidenScalar); 185 setAction({G_FPTOUI, 0, Ty}, WidenScalar); 186 setAction({G_SITOFP, 1, Ty}, WidenScalar); 187 setAction({G_UITOFP, 1, Ty}, WidenScalar); 188 } 189 190 for (auto Ty : { s32, s64 }) { 191 setAction({G_FPTOSI, 1, Ty}, Legal); 192 setAction({G_FPTOUI, 1, Ty}, Legal); 193 setAction({G_SITOFP, 0, Ty}, Legal); 194 setAction({G_UITOFP, 0, Ty}, Legal); 195 } 196 197 // Control-flow 198 for (auto Ty : {s1, s8, s16, s32}) 199 setAction({G_BRCOND, Ty}, Legal); 200 setAction({G_BRINDIRECT, p0}, Legal); 201 202 // Select 203 for (auto Ty : {s1, s8, s16}) 204 setAction({G_SELECT, Ty}, WidenScalar); 205 206 for (auto Ty : {s32, s64, p0}) 207 setAction({G_SELECT, Ty}, Legal); 208 209 setAction({G_SELECT, 1, s1}, Legal); 210 211 // Pointer-handling 212 setAction({G_FRAME_INDEX, p0}, Legal); 213 setAction({G_GLOBAL_VALUE, p0}, Legal); 214 215 for (auto Ty : {s1, s8, s16, s32, s64}) 216 setAction({G_PTRTOINT, 0, Ty}, Legal); 217 218 setAction({G_PTRTOINT, 1, p0}, Legal); 219 220 setAction({G_INTTOPTR, 0, p0}, Legal); 221 setAction({G_INTTOPTR, 1, s64}, Legal); 222 223 // Casts for 32 and 64-bit width type are just copies. 224 for (auto Ty : {s1, s8, s16, s32, s64}) { 225 setAction({G_BITCAST, 0, Ty}, Legal); 226 setAction({G_BITCAST, 1, Ty}, Legal); 227 } 228 229 // For the sake of copying bits around, the type does not really 230 // matter as long as it fits a register. 231 for (int EltSize = 8; EltSize <= 64; EltSize *= 2) { 232 setAction({G_BITCAST, 0, LLT::vector(128/EltSize, EltSize)}, Legal); 233 setAction({G_BITCAST, 1, LLT::vector(128/EltSize, EltSize)}, Legal); 234 if (EltSize >= 64) 235 continue; 236 237 setAction({G_BITCAST, 0, LLT::vector(64/EltSize, EltSize)}, Legal); 238 setAction({G_BITCAST, 1, LLT::vector(64/EltSize, EltSize)}, Legal); 239 if (EltSize >= 32) 240 continue; 241 242 setAction({G_BITCAST, 0, LLT::vector(32/EltSize, EltSize)}, Legal); 243 setAction({G_BITCAST, 1, LLT::vector(32/EltSize, EltSize)}, Legal); 244 } 245 246 setAction({G_VASTART, p0}, Legal); 247 248 // va_list must be a pointer, but most sized types are pretty easy to handle 249 // as the destination. 250 setAction({G_VAARG, 1, p0}, Legal); 251 252 for (auto Ty : {s8, s16, s32, s64, p0}) 253 setAction({G_VAARG, Ty}, Custom); 254 255 computeTables(); 256 } 257 258 bool AArch64LegalizerInfo::legalizeCustom(MachineInstr &MI, 259 MachineRegisterInfo &MRI, 260 MachineIRBuilder &MIRBuilder) const { 261 switch (MI.getOpcode()) { 262 default: 263 // No idea what to do. 264 return false; 265 case TargetOpcode::G_VAARG: 266 return legalizeVaArg(MI, MRI, MIRBuilder); 267 } 268 269 llvm_unreachable("expected switch to return"); 270 } 271 272 bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI, 273 MachineRegisterInfo &MRI, 274 MachineIRBuilder &MIRBuilder) const { 275 MIRBuilder.setInstr(MI); 276 MachineFunction &MF = MIRBuilder.getMF(); 277 unsigned Align = MI.getOperand(2).getImm(); 278 unsigned Dst = MI.getOperand(0).getReg(); 279 unsigned ListPtr = MI.getOperand(1).getReg(); 280 281 LLT PtrTy = MRI.getType(ListPtr); 282 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 283 284 const unsigned PtrSize = PtrTy.getSizeInBits() / 8; 285 unsigned List = MRI.createGenericVirtualRegister(PtrTy); 286 MIRBuilder.buildLoad( 287 List, ListPtr, 288 *MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad, 289 PtrSize, /* Align = */ PtrSize)); 290 291 unsigned DstPtr; 292 if (Align > PtrSize) { 293 // Realign the list to the actual required alignment. 294 auto AlignMinus1 = MIRBuilder.buildConstant(IntPtrTy, Align - 1); 295 296 unsigned ListTmp = MRI.createGenericVirtualRegister(PtrTy); 297 MIRBuilder.buildGEP(ListTmp, List, AlignMinus1->getOperand(0).getReg()); 298 299 DstPtr = MRI.createGenericVirtualRegister(PtrTy); 300 MIRBuilder.buildPtrMask(DstPtr, ListTmp, Log2_64(Align)); 301 } else 302 DstPtr = List; 303 304 uint64_t ValSize = MRI.getType(Dst).getSizeInBits() / 8; 305 MIRBuilder.buildLoad( 306 Dst, DstPtr, 307 *MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad, 308 ValSize, std::max(Align, PtrSize))); 309 310 unsigned SizeReg = MRI.createGenericVirtualRegister(IntPtrTy); 311 MIRBuilder.buildConstant(SizeReg, alignTo(ValSize, PtrSize)); 312 313 unsigned NewList = MRI.createGenericVirtualRegister(PtrTy); 314 MIRBuilder.buildGEP(NewList, DstPtr, SizeReg); 315 316 MIRBuilder.buildStore( 317 NewList, ListPtr, 318 *MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore, 319 PtrSize, /* Align = */ PtrSize)); 320 321 MI.eraseFromParent(); 322 return true; 323 } 324