1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file When allowed by the instruction, replace a dead definition of a GPR
10 /// with the zero register. This makes the code a bit friendlier towards the
11 /// hardware's register renamer.
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64.h"
15 #include "AArch64RegisterInfo.h"
16 #include "AArch64Subtarget.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/ISDOpcodes.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetSubtargetInfo.h"
27 using namespace llvm;
28 
29 #define DEBUG_TYPE "aarch64-dead-defs"
30 
31 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
32 
33 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
34 
35 namespace {
36 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
37 private:
38   const TargetRegisterInfo *TRI;
39   const MachineRegisterInfo *MRI;
40   const TargetInstrInfo *TII;
41   bool Changed;
42   void processMachineBasicBlock(MachineBasicBlock &MBB);
43 public:
44   static char ID; // Pass identification, replacement for typeid.
45   AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
46     initializeAArch64DeadRegisterDefinitionsPass(
47         *PassRegistry::getPassRegistry());
48   }
49 
50   bool runOnMachineFunction(MachineFunction &F) override;
51 
52   StringRef getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
53 
54   void getAnalysisUsage(AnalysisUsage &AU) const override {
55     AU.setPreservesCFG();
56     MachineFunctionPass::getAnalysisUsage(AU);
57   }
58 };
59 char AArch64DeadRegisterDefinitions::ID = 0;
60 } // end anonymous namespace
61 
62 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
63                 AARCH64_DEAD_REG_DEF_NAME, false, false)
64 
65 static bool usesFrameIndex(const MachineInstr &MI) {
66   for (const MachineOperand &MO : MI.uses())
67     if (MO.isFI())
68       return true;
69   return false;
70 }
71 
72 void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
73     MachineBasicBlock &MBB) {
74   const MachineFunction &MF = *MBB.getParent();
75   for (MachineInstr &MI : MBB) {
76     if (usesFrameIndex(MI)) {
77       // We need to skip this instruction because while it appears to have a
78       // dead def it uses a frame index which might expand into a multi
79       // instruction sequence during EPI.
80       DEBUG(dbgs() << "    Ignoring, operand is frame index\n");
81       continue;
82     }
83     if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
84       // It is not allowed to write to the same register (not even the zero
85       // register) twice in a single instruction.
86       DEBUG(dbgs() << "    Ignoring, XZR or WZR already used by the instruction\n");
87       continue;
88     }
89     if (MF.getSubtarget<AArch64Subtarget>().hasLSE()) {
90       // XZ/WZ for LSE can only be used when acquire semantics are not used,
91       // LDOPAL WZ is an invalid opcode.
92       switch (MI.getOpcode()) {
93       case AArch64::CASALb:
94       case AArch64::CASALh:
95       case AArch64::CASALs:
96       case AArch64::CASALd:
97       case AArch64::SWPALb:
98       case AArch64::SWPALh:
99       case AArch64::SWPALs:
100       case AArch64::SWPALd:
101       case AArch64::LDADDALb:
102       case AArch64::LDADDALh:
103       case AArch64::LDADDALs:
104       case AArch64::LDADDALd:
105       case AArch64::LDCLRALb:
106       case AArch64::LDCLRALh:
107       case AArch64::LDCLRALs:
108       case AArch64::LDCLRALd:
109       case AArch64::LDEORALb:
110       case AArch64::LDEORALh:
111       case AArch64::LDEORALs:
112       case AArch64::LDEORALd:
113       case AArch64::LDSETALb:
114       case AArch64::LDSETALh:
115       case AArch64::LDSETALs:
116       case AArch64::LDSETALd:
117       case AArch64::LDSMINALb:
118       case AArch64::LDSMINALh:
119       case AArch64::LDSMINALs:
120       case AArch64::LDSMINALd:
121       case AArch64::LDSMAXALb:
122       case AArch64::LDSMAXALh:
123       case AArch64::LDSMAXALs:
124       case AArch64::LDSMAXALd:
125       case AArch64::LDUMINALb:
126       case AArch64::LDUMINALh:
127       case AArch64::LDUMINALs:
128       case AArch64::LDUMINALd:
129       case AArch64::LDUMAXALb:
130       case AArch64::LDUMAXALh:
131       case AArch64::LDUMAXALs:
132       case AArch64::LDUMAXALd:
133         continue;
134       default:
135         break;
136       }
137     }
138     const MCInstrDesc &Desc = MI.getDesc();
139     for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
140       MachineOperand &MO = MI.getOperand(I);
141       if (!MO.isReg() || !MO.isDef())
142         continue;
143       // We should not have any relevant physreg defs that are replacable by
144       // zero before register allocation. So we just check for dead vreg defs.
145       unsigned Reg = MO.getReg();
146       if (!TargetRegisterInfo::isVirtualRegister(Reg) ||
147           (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
148         continue;
149       assert(!MO.isImplicit() && "Unexpected implicit def!");
150       DEBUG(dbgs() << "  Dead def operand #" << I << " in:\n    ";
151             MI.print(dbgs()));
152       // Be careful not to change the register if it's a tied operand.
153       if (MI.isRegTiedToUseOperand(I)) {
154         DEBUG(dbgs() << "    Ignoring, def is tied operand.\n");
155         continue;
156       }
157       const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
158       unsigned NewReg;
159       if (RC == nullptr) {
160         DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
161         continue;
162       } else if (RC->contains(AArch64::WZR))
163         NewReg = AArch64::WZR;
164       else if (RC->contains(AArch64::XZR))
165         NewReg = AArch64::XZR;
166       else {
167         DEBUG(dbgs() << "    Ignoring, register is not a GPR.\n");
168         continue;
169       }
170       DEBUG(dbgs() << "    Replacing with zero register. New:\n      ");
171       MO.setReg(NewReg);
172       MO.setIsDead();
173       DEBUG(MI.print(dbgs()));
174       ++NumDeadDefsReplaced;
175       Changed = true;
176       // Only replace one dead register, see check for zero register above.
177       break;
178     }
179   }
180 }
181 
182 // Scan the function for instructions that have a dead definition of a
183 // register. Replace that register with the zero register when possible.
184 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
185   if (skipFunction(*MF.getFunction()))
186     return false;
187 
188   TRI = MF.getSubtarget().getRegisterInfo();
189   TII = MF.getSubtarget().getInstrInfo();
190   MRI = &MF.getRegInfo();
191   DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
192   Changed = false;
193   for (auto &MBB : MF)
194     processMachineBasicBlock(MBB);
195   return Changed;
196 }
197 
198 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
199   return new AArch64DeadRegisterDefinitions();
200 }
201