1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This file implements the lowering of LLVM calls to machine code calls for 12 /// GlobalISel. 13 /// 14 //===----------------------------------------------------------------------===// 15 16 #include "AArch64CallLowering.h" 17 #include "AArch64ISelLowering.h" 18 #include "AArch64MachineFunctionInfo.h" 19 #include "AArch64Subtarget.h" 20 #include "llvm/ADT/ArrayRef.h" 21 #include "llvm/ADT/SmallVector.h" 22 #include "llvm/CodeGen/Analysis.h" 23 #include "llvm/CodeGen/CallingConvLower.h" 24 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" 25 #include "llvm/CodeGen/GlobalISel/Utils.h" 26 #include "llvm/CodeGen/LowLevelType.h" 27 #include "llvm/CodeGen/MachineBasicBlock.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineInstrBuilder.h" 31 #include "llvm/CodeGen/MachineMemOperand.h" 32 #include "llvm/CodeGen/MachineOperand.h" 33 #include "llvm/CodeGen/MachineRegisterInfo.h" 34 #include "llvm/CodeGen/MachineValueType.h" 35 #include "llvm/CodeGen/TargetRegisterInfo.h" 36 #include "llvm/CodeGen/TargetSubtargetInfo.h" 37 #include "llvm/CodeGen/ValueTypes.h" 38 #include "llvm/IR/Argument.h" 39 #include "llvm/IR/Attributes.h" 40 #include "llvm/IR/Function.h" 41 #include "llvm/IR/Type.h" 42 #include "llvm/IR/Value.h" 43 #include <algorithm> 44 #include <cassert> 45 #include <cstdint> 46 #include <iterator> 47 48 using namespace llvm; 49 50 AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI) 51 : CallLowering(&TLI) {} 52 53 namespace { 54 struct IncomingArgHandler : public CallLowering::ValueHandler { 55 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 56 CCAssignFn *AssignFn) 57 : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {} 58 59 unsigned getStackAddress(uint64_t Size, int64_t Offset, 60 MachinePointerInfo &MPO) override { 61 auto &MFI = MIRBuilder.getMF().getFrameInfo(); 62 int FI = MFI.CreateFixedObject(Size, Offset, true); 63 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); 64 unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64)); 65 MIRBuilder.buildFrameIndex(AddrReg, FI); 66 StackUsed = std::max(StackUsed, Size + Offset); 67 return AddrReg; 68 } 69 70 void assignValueToReg(unsigned ValVReg, unsigned PhysReg, 71 CCValAssign &VA) override { 72 markPhysRegUsed(PhysReg); 73 switch (VA.getLocInfo()) { 74 default: 75 MIRBuilder.buildCopy(ValVReg, PhysReg); 76 break; 77 case CCValAssign::LocInfo::SExt: 78 case CCValAssign::LocInfo::ZExt: 79 case CCValAssign::LocInfo::AExt: { 80 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); 81 MIRBuilder.buildTrunc(ValVReg, Copy); 82 break; 83 } 84 } 85 } 86 87 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size, 88 MachinePointerInfo &MPO, CCValAssign &VA) override { 89 auto MMO = MIRBuilder.getMF().getMachineMemOperand( 90 MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size, 91 0); 92 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); 93 } 94 95 /// How the physical register gets marked varies between formal 96 /// parameters (it's a basic-block live-in), and a call instruction 97 /// (it's an implicit-def of the BL). 98 virtual void markPhysRegUsed(unsigned PhysReg) = 0; 99 100 uint64_t StackUsed; 101 }; 102 103 struct FormalArgHandler : public IncomingArgHandler { 104 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 105 CCAssignFn *AssignFn) 106 : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {} 107 108 void markPhysRegUsed(unsigned PhysReg) override { 109 MIRBuilder.getMBB().addLiveIn(PhysReg); 110 } 111 }; 112 113 struct CallReturnHandler : public IncomingArgHandler { 114 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 115 MachineInstrBuilder MIB, CCAssignFn *AssignFn) 116 : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} 117 118 void markPhysRegUsed(unsigned PhysReg) override { 119 MIB.addDef(PhysReg, RegState::Implicit); 120 } 121 122 MachineInstrBuilder MIB; 123 }; 124 125 struct OutgoingArgHandler : public CallLowering::ValueHandler { 126 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 127 MachineInstrBuilder MIB, CCAssignFn *AssignFn, 128 CCAssignFn *AssignFnVarArg) 129 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), 130 AssignFnVarArg(AssignFnVarArg), StackSize(0) {} 131 132 unsigned getStackAddress(uint64_t Size, int64_t Offset, 133 MachinePointerInfo &MPO) override { 134 LLT p0 = LLT::pointer(0, 64); 135 LLT s64 = LLT::scalar(64); 136 unsigned SPReg = MRI.createGenericVirtualRegister(p0); 137 MIRBuilder.buildCopy(SPReg, AArch64::SP); 138 139 unsigned OffsetReg = MRI.createGenericVirtualRegister(s64); 140 MIRBuilder.buildConstant(OffsetReg, Offset); 141 142 unsigned AddrReg = MRI.createGenericVirtualRegister(p0); 143 MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg); 144 145 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); 146 return AddrReg; 147 } 148 149 void assignValueToReg(unsigned ValVReg, unsigned PhysReg, 150 CCValAssign &VA) override { 151 MIB.addUse(PhysReg, RegState::Implicit); 152 unsigned ExtReg = extendRegister(ValVReg, VA); 153 MIRBuilder.buildCopy(PhysReg, ExtReg); 154 } 155 156 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size, 157 MachinePointerInfo &MPO, CCValAssign &VA) override { 158 auto MMO = MIRBuilder.getMF().getMachineMemOperand( 159 MPO, MachineMemOperand::MOStore, Size, 0); 160 MIRBuilder.buildStore(ValVReg, Addr, *MMO); 161 } 162 163 bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT, 164 CCValAssign::LocInfo LocInfo, 165 const CallLowering::ArgInfo &Info, 166 CCState &State) override { 167 bool Res; 168 if (Info.IsFixed) 169 Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State); 170 else 171 Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Info.Flags, State); 172 173 StackSize = State.getNextStackOffset(); 174 return Res; 175 } 176 177 MachineInstrBuilder MIB; 178 CCAssignFn *AssignFnVarArg; 179 uint64_t StackSize; 180 }; 181 } // namespace 182 183 void AArch64CallLowering::splitToValueTypes( 184 const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs, 185 const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv, 186 const SplitArgTy &PerformArgSplit) const { 187 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>(); 188 LLVMContext &Ctx = OrigArg.Ty->getContext(); 189 190 SmallVector<EVT, 4> SplitVTs; 191 SmallVector<uint64_t, 4> Offsets; 192 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0); 193 194 if (SplitVTs.size() == 1) { 195 // No splitting to do, but we want to replace the original type (e.g. [1 x 196 // double] -> double). 197 SplitArgs.emplace_back(OrigArg.Reg, SplitVTs[0].getTypeForEVT(Ctx), 198 OrigArg.Flags, OrigArg.IsFixed); 199 return; 200 } 201 202 unsigned FirstRegIdx = SplitArgs.size(); 203 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters( 204 OrigArg.Ty, CallConv, false); 205 for (auto SplitVT : SplitVTs) { 206 Type *SplitTy = SplitVT.getTypeForEVT(Ctx); 207 SplitArgs.push_back( 208 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*SplitTy, DL)), 209 SplitTy, OrigArg.Flags, OrigArg.IsFixed}); 210 if (NeedsRegBlock) 211 SplitArgs.back().Flags.setInConsecutiveRegs(); 212 } 213 214 SplitArgs.back().Flags.setInConsecutiveRegsLast(); 215 216 for (unsigned i = 0; i < Offsets.size(); ++i) 217 PerformArgSplit(SplitArgs[FirstRegIdx + i].Reg, Offsets[i] * 8); 218 } 219 220 bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, 221 const Value *Val, unsigned VReg) const { 222 MachineFunction &MF = MIRBuilder.getMF(); 223 const Function &F = MF.getFunction(); 224 225 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR); 226 assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg"); 227 bool Success = true; 228 if (VReg) { 229 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>(); 230 CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv()); 231 MachineRegisterInfo &MRI = MF.getRegInfo(); 232 auto &DL = F.getParent()->getDataLayout(); 233 234 ArgInfo OrigArg{VReg, Val->getType()}; 235 setArgFlags(OrigArg, AttributeList::ReturnIndex, DL, F); 236 237 SmallVector<ArgInfo, 8> SplitArgs; 238 splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(), 239 [&](unsigned Reg, uint64_t Offset) { 240 MIRBuilder.buildExtract(Reg, VReg, Offset); 241 }); 242 243 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn); 244 Success = handleAssignments(MIRBuilder, SplitArgs, Handler); 245 } 246 247 MIRBuilder.insertInstr(MIB); 248 return Success; 249 } 250 251 bool AArch64CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder, 252 const Function &F, 253 ArrayRef<unsigned> VRegs) const { 254 MachineFunction &MF = MIRBuilder.getMF(); 255 MachineBasicBlock &MBB = MIRBuilder.getMBB(); 256 MachineRegisterInfo &MRI = MF.getRegInfo(); 257 auto &DL = F.getParent()->getDataLayout(); 258 259 SmallVector<ArgInfo, 8> SplitArgs; 260 unsigned i = 0; 261 for (auto &Arg : F.args()) { 262 if (DL.getTypeStoreSize(Arg.getType()) == 0) 263 continue; 264 ArgInfo OrigArg{VRegs[i], Arg.getType()}; 265 setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F); 266 bool Split = false; 267 LLT Ty = MRI.getType(VRegs[i]); 268 unsigned Dst = VRegs[i]; 269 270 splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv(), 271 [&](unsigned Reg, uint64_t Offset) { 272 if (!Split) { 273 Split = true; 274 Dst = MRI.createGenericVirtualRegister(Ty); 275 MIRBuilder.buildUndef(Dst); 276 } 277 unsigned Tmp = MRI.createGenericVirtualRegister(Ty); 278 MIRBuilder.buildInsert(Tmp, Dst, Reg, Offset); 279 Dst = Tmp; 280 }); 281 282 if (Dst != VRegs[i]) 283 MIRBuilder.buildCopy(VRegs[i], Dst); 284 ++i; 285 } 286 287 if (!MBB.empty()) 288 MIRBuilder.setInstr(*MBB.begin()); 289 290 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>(); 291 CCAssignFn *AssignFn = 292 TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false); 293 294 FormalArgHandler Handler(MIRBuilder, MRI, AssignFn); 295 if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) 296 return false; 297 298 if (F.isVarArg()) { 299 if (!MF.getSubtarget<AArch64Subtarget>().isTargetDarwin()) { 300 // FIXME: we need to reimplement saveVarArgsRegisters from 301 // AArch64ISelLowering. 302 return false; 303 } 304 305 // We currently pass all varargs at 8-byte alignment. 306 uint64_t StackOffset = alignTo(Handler.StackUsed, 8); 307 308 auto &MFI = MIRBuilder.getMF().getFrameInfo(); 309 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>(); 310 FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true)); 311 } 312 313 // Move back to the end of the basic block. 314 MIRBuilder.setMBB(MBB); 315 316 return true; 317 } 318 319 bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, 320 CallingConv::ID CallConv, 321 const MachineOperand &Callee, 322 const ArgInfo &OrigRet, 323 ArrayRef<ArgInfo> OrigArgs) const { 324 MachineFunction &MF = MIRBuilder.getMF(); 325 const Function &F = MF.getFunction(); 326 MachineRegisterInfo &MRI = MF.getRegInfo(); 327 auto &DL = F.getParent()->getDataLayout(); 328 329 SmallVector<ArgInfo, 8> SplitArgs; 330 for (auto &OrigArg : OrigArgs) { 331 splitToValueTypes(OrigArg, SplitArgs, DL, MRI, CallConv, 332 [&](unsigned Reg, uint64_t Offset) { 333 MIRBuilder.buildExtract(Reg, OrigArg.Reg, Offset); 334 }); 335 } 336 337 // Find out which ABI gets to decide where things go. 338 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>(); 339 CCAssignFn *AssignFnFixed = 340 TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/false); 341 CCAssignFn *AssignFnVarArg = 342 TLI.CCAssignFnForCall(CallConv, /*IsVarArg=*/true); 343 344 auto CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); 345 346 // Create a temporarily-floating call instruction so we can add the implicit 347 // uses of arg registers. 348 auto MIB = MIRBuilder.buildInstrNoInsert(Callee.isReg() ? AArch64::BLR 349 : AArch64::BL); 350 MIB.add(Callee); 351 352 // Tell the call which registers are clobbered. 353 auto TRI = MF.getSubtarget().getRegisterInfo(); 354 MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv())); 355 356 // Do the actual argument marshalling. 357 SmallVector<unsigned, 8> PhysRegs; 358 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed, 359 AssignFnVarArg); 360 if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) 361 return false; 362 363 // Now we can add the actual call instruction to the correct basic block. 364 MIRBuilder.insertInstr(MIB); 365 366 // If Callee is a reg, since it is used by a target specific 367 // instruction, it must have a register class matching the 368 // constraint of that instruction. 369 if (Callee.isReg()) 370 MIB->getOperand(0).setReg(constrainOperandRegClass( 371 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), 372 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), 373 Callee.getReg(), 0)); 374 375 // Finally we can copy the returned value back into its virtual-register. In 376 // symmetry with the arugments, the physical register must be an 377 // implicit-define of the call instruction. 378 CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv()); 379 if (OrigRet.Reg) { 380 SplitArgs.clear(); 381 382 SmallVector<uint64_t, 8> RegOffsets; 383 SmallVector<unsigned, 8> SplitRegs; 384 splitToValueTypes(OrigRet, SplitArgs, DL, MRI, F.getCallingConv(), 385 [&](unsigned Reg, uint64_t Offset) { 386 RegOffsets.push_back(Offset); 387 SplitRegs.push_back(Reg); 388 }); 389 390 CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn); 391 if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) 392 return false; 393 394 if (!RegOffsets.empty()) 395 MIRBuilder.buildSequence(OrigRet.Reg, SplitRegs, RegOffsets); 396 } 397 398 CallSeqStart.addImm(Handler.StackSize).addImm(0); 399 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP) 400 .addImm(Handler.StackSize) 401 .addImm(0); 402 403 return true; 404 } 405