1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the operating system Host concept. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Support/Host.h" 15 #include "llvm/ADT/SmallSet.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/StringSwitch.h" 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Config/config.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/FileSystem.h" 23 #include "llvm/Support/MemoryBuffer.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <assert.h> 26 #include <string.h> 27 28 // Include the platform-specific parts of this class. 29 #ifdef LLVM_ON_UNIX 30 #include "Unix/Host.inc" 31 #endif 32 #ifdef LLVM_ON_WIN32 33 #include "Windows/Host.inc" 34 #endif 35 #ifdef _MSC_VER 36 #include <intrin.h> 37 #endif 38 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 39 #include <mach/host_info.h> 40 #include <mach/mach.h> 41 #include <mach/mach_host.h> 42 #include <mach/machine.h> 43 #endif 44 45 #define DEBUG_TYPE "host-detection" 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Implementations of the CPU detection routines 50 // 51 //===----------------------------------------------------------------------===// 52 53 using namespace llvm; 54 55 static std::unique_ptr<llvm::MemoryBuffer> 56 LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { 57 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 58 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 59 if (std::error_code EC = Text.getError()) { 60 llvm::errs() << "Can't read " 61 << "/proc/cpuinfo: " << EC.message() << "\n"; 62 return nullptr; 63 } 64 return std::move(*Text); 65 } 66 67 StringRef sys::detail::getHostCPUNameForPowerPC( 68 const StringRef &ProcCpuinfoContent) { 69 // Access to the Processor Version Register (PVR) on PowerPC is privileged, 70 // and so we must use an operating-system interface to determine the current 71 // processor type. On Linux, this is exposed through the /proc/cpuinfo file. 72 const char *generic = "generic"; 73 74 // The cpu line is second (after the 'processor: 0' line), so if this 75 // buffer is too small then something has changed (or is wrong). 76 StringRef::const_iterator CPUInfoStart = ProcCpuinfoContent.begin(); 77 StringRef::const_iterator CPUInfoEnd = ProcCpuinfoContent.end(); 78 79 StringRef::const_iterator CIP = CPUInfoStart; 80 81 StringRef::const_iterator CPUStart = 0; 82 size_t CPULen = 0; 83 84 // We need to find the first line which starts with cpu, spaces, and a colon. 85 // After the colon, there may be some additional spaces and then the cpu type. 86 while (CIP < CPUInfoEnd && CPUStart == 0) { 87 if (CIP < CPUInfoEnd && *CIP == '\n') 88 ++CIP; 89 90 if (CIP < CPUInfoEnd && *CIP == 'c') { 91 ++CIP; 92 if (CIP < CPUInfoEnd && *CIP == 'p') { 93 ++CIP; 94 if (CIP < CPUInfoEnd && *CIP == 'u') { 95 ++CIP; 96 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 97 ++CIP; 98 99 if (CIP < CPUInfoEnd && *CIP == ':') { 100 ++CIP; 101 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t')) 102 ++CIP; 103 104 if (CIP < CPUInfoEnd) { 105 CPUStart = CIP; 106 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' && 107 *CIP != ',' && *CIP != '\n')) 108 ++CIP; 109 CPULen = CIP - CPUStart; 110 } 111 } 112 } 113 } 114 } 115 116 if (CPUStart == 0) 117 while (CIP < CPUInfoEnd && *CIP != '\n') 118 ++CIP; 119 } 120 121 if (CPUStart == 0) 122 return generic; 123 124 return StringSwitch<const char *>(StringRef(CPUStart, CPULen)) 125 .Case("604e", "604e") 126 .Case("604", "604") 127 .Case("7400", "7400") 128 .Case("7410", "7400") 129 .Case("7447", "7400") 130 .Case("7455", "7450") 131 .Case("G4", "g4") 132 .Case("POWER4", "970") 133 .Case("PPC970FX", "970") 134 .Case("PPC970MP", "970") 135 .Case("G5", "g5") 136 .Case("POWER5", "g5") 137 .Case("A2", "a2") 138 .Case("POWER6", "pwr6") 139 .Case("POWER7", "pwr7") 140 .Case("POWER8", "pwr8") 141 .Case("POWER8E", "pwr8") 142 .Case("POWER8NVL", "pwr8") 143 .Case("POWER9", "pwr9") 144 .Default(generic); 145 } 146 147 StringRef sys::detail::getHostCPUNameForARM( 148 const StringRef &ProcCpuinfoContent) { 149 // The cpuid register on arm is not accessible from user space. On Linux, 150 // it is exposed through the /proc/cpuinfo file. 151 152 // Read 32 lines from /proc/cpuinfo, which should contain the CPU part line 153 // in all cases. 154 SmallVector<StringRef, 32> Lines; 155 ProcCpuinfoContent.split(Lines, "\n"); 156 157 // Look for the CPU implementer line. 158 StringRef Implementer; 159 StringRef Hardware; 160 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 161 if (Lines[I].startswith("CPU implementer")) 162 Implementer = Lines[I].substr(15).ltrim("\t :"); 163 if (Lines[I].startswith("Hardware")) 164 Hardware = Lines[I].substr(8).ltrim("\t :"); 165 } 166 167 if (Implementer == "0x41") { // ARM Ltd. 168 // MSM8992/8994 may give cpu part for the core that the kernel is running on, 169 // which is undeterministic and wrong. Always return cortex-a53 for these SoC. 170 if (Hardware.endswith("MSM8994") || Hardware.endswith("MSM8996")) 171 return "cortex-a53"; 172 173 174 // Look for the CPU part line. 175 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 176 if (Lines[I].startswith("CPU part")) 177 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 178 // values correspond to the "Part number" in the CP15/c0 register. The 179 // contents are specified in the various processor manuals. 180 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 181 .Case("0x926", "arm926ej-s") 182 .Case("0xb02", "mpcore") 183 .Case("0xb36", "arm1136j-s") 184 .Case("0xb56", "arm1156t2-s") 185 .Case("0xb76", "arm1176jz-s") 186 .Case("0xc08", "cortex-a8") 187 .Case("0xc09", "cortex-a9") 188 .Case("0xc0f", "cortex-a15") 189 .Case("0xc20", "cortex-m0") 190 .Case("0xc23", "cortex-m3") 191 .Case("0xc24", "cortex-m4") 192 .Case("0xd04", "cortex-a35") 193 .Case("0xd03", "cortex-a53") 194 .Case("0xd07", "cortex-a57") 195 .Case("0xd08", "cortex-a72") 196 .Case("0xd09", "cortex-a73") 197 .Default("generic"); 198 } 199 200 if (Implementer == "0x51") // Qualcomm Technologies, Inc. 201 // Look for the CPU part line. 202 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 203 if (Lines[I].startswith("CPU part")) 204 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The 205 // values correspond to the "Part number" in the CP15/c0 register. The 206 // contents are specified in the various processor manuals. 207 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :")) 208 .Case("0x06f", "krait") // APQ8064 209 .Case("0x201", "kryo") 210 .Case("0x205", "kryo") 211 .Case("0xc00", "falkor") 212 .Default("generic"); 213 214 return "generic"; 215 } 216 217 StringRef sys::detail::getHostCPUNameForS390x( 218 const StringRef &ProcCpuinfoContent) { 219 // STIDP is a privileged operation, so use /proc/cpuinfo instead. 220 221 // The "processor 0:" line comes after a fair amount of other information, 222 // including a cache breakdown, but this should be plenty. 223 SmallVector<StringRef, 32> Lines; 224 ProcCpuinfoContent.split(Lines, "\n"); 225 226 // Look for the CPU features. 227 SmallVector<StringRef, 32> CPUFeatures; 228 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 229 if (Lines[I].startswith("features")) { 230 size_t Pos = Lines[I].find(":"); 231 if (Pos != StringRef::npos) { 232 Lines[I].drop_front(Pos + 1).split(CPUFeatures, ' '); 233 break; 234 } 235 } 236 237 // We need to check for the presence of vector support independently of 238 // the machine type, since we may only use the vector register set when 239 // supported by the kernel (and hypervisor). 240 bool HaveVectorSupport = false; 241 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 242 if (CPUFeatures[I] == "vx") 243 HaveVectorSupport = true; 244 } 245 246 // Now check the processor machine type. 247 for (unsigned I = 0, E = Lines.size(); I != E; ++I) { 248 if (Lines[I].startswith("processor ")) { 249 size_t Pos = Lines[I].find("machine = "); 250 if (Pos != StringRef::npos) { 251 Pos += sizeof("machine = ") - 1; 252 unsigned int Id; 253 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { 254 if (Id >= 3906 && HaveVectorSupport) 255 return "z14"; 256 if (Id >= 2964 && HaveVectorSupport) 257 return "z13"; 258 if (Id >= 2827) 259 return "zEC12"; 260 if (Id >= 2817) 261 return "z196"; 262 } 263 } 264 break; 265 } 266 } 267 268 return "generic"; 269 } 270 271 #if defined(__i386__) || defined(_M_IX86) || \ 272 defined(__x86_64__) || defined(_M_X64) 273 274 enum VendorSignatures { 275 SIG_INTEL = 0x756e6547 /* Genu */, 276 SIG_AMD = 0x68747541 /* Auth */ 277 }; 278 279 enum ProcessorVendors { 280 VENDOR_INTEL = 1, 281 VENDOR_AMD, 282 VENDOR_OTHER, 283 VENDOR_MAX 284 }; 285 286 enum ProcessorTypes { 287 INTEL_BONNELL = 1, 288 INTEL_CORE2, 289 INTEL_COREI7, 290 AMDFAM10H, 291 AMDFAM15H, 292 INTEL_SILVERMONT, 293 INTEL_KNL, 294 AMD_BTVER1, 295 AMD_BTVER2, 296 AMDFAM17H, 297 // Entries below this are not in libgcc/compiler-rt. 298 INTEL_i386, 299 INTEL_i486, 300 INTEL_PENTIUM, 301 INTEL_PENTIUM_PRO, 302 INTEL_PENTIUM_II, 303 INTEL_PENTIUM_III, 304 INTEL_PENTIUM_IV, 305 INTEL_PENTIUM_M, 306 INTEL_CORE_DUO, 307 INTEL_X86_64, 308 INTEL_NOCONA, 309 INTEL_PRESCOTT, 310 AMD_i486, 311 AMDPENTIUM, 312 AMDATHLON, 313 INTEL_GOLDMONT, 314 CPU_TYPE_MAX 315 }; 316 317 enum ProcessorSubtypes { 318 INTEL_COREI7_NEHALEM = 1, 319 INTEL_COREI7_WESTMERE, 320 INTEL_COREI7_SANDYBRIDGE, 321 AMDFAM10H_BARCELONA, 322 AMDFAM10H_SHANGHAI, 323 AMDFAM10H_ISTANBUL, 324 AMDFAM15H_BDVER1, 325 AMDFAM15H_BDVER2, 326 AMDFAM15H_BDVER3, 327 AMDFAM15H_BDVER4, 328 AMDFAM17H_ZNVER1, 329 INTEL_COREI7_IVYBRIDGE, 330 INTEL_COREI7_HASWELL, 331 INTEL_COREI7_BROADWELL, 332 INTEL_COREI7_SKYLAKE, 333 INTEL_COREI7_SKYLAKE_AVX512, 334 // Entries below this are not in libgcc/compiler-rt. 335 INTEL_PENTIUM_MMX, 336 INTEL_CORE2_65, 337 INTEL_CORE2_45, 338 AMDPENTIUM_K6, 339 AMDPENTIUM_K62, 340 AMDPENTIUM_K63, 341 AMDPENTIUM_GEODE, 342 AMDATHLON_CLASSIC, 343 AMDATHLON_XP, 344 AMDATHLON_K8, 345 AMDATHLON_K8SSE3, 346 CPU_SUBTYPE_MAX 347 }; 348 349 enum ProcessorFeatures { 350 FEATURE_CMOV = 0, 351 FEATURE_MMX, 352 FEATURE_POPCNT, 353 FEATURE_SSE, 354 FEATURE_SSE2, 355 FEATURE_SSE3, 356 FEATURE_SSSE3, 357 FEATURE_SSE4_1, 358 FEATURE_SSE4_2, 359 FEATURE_AVX, 360 FEATURE_AVX2, 361 FEATURE_SSE4_A, 362 FEATURE_FMA4, 363 FEATURE_XOP, 364 FEATURE_FMA, 365 FEATURE_AVX512F, 366 FEATURE_BMI, 367 FEATURE_BMI2, 368 FEATURE_AES, 369 FEATURE_PCLMUL, 370 FEATURE_AVX512VL, 371 FEATURE_AVX512BW, 372 FEATURE_AVX512DQ, 373 FEATURE_AVX512CD, 374 FEATURE_AVX512ER, 375 FEATURE_AVX512PF, 376 FEATURE_AVX512VBMI, 377 FEATURE_AVX512IFMA, 378 FEATURE_AVX5124VNNIW, 379 FEATURE_AVX5124FMAPS, 380 FEATURE_AVX512VPOPCNTDQ, 381 // Only one bit free left in the first 32 features. 382 FEATURE_MOVBE = 32, 383 FEATURE_ADX, 384 FEATURE_EM64T 385 }; 386 387 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max). 388 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID 389 // support. Consequently, for i386, the presence of CPUID is checked first 390 // via the corresponding eflags bit. 391 // Removal of cpuid.h header motivated by PR30384 392 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp 393 // or test-suite, but are used in external projects e.g. libstdcxx 394 static bool isCpuIdSupported() { 395 #if defined(__GNUC__) || defined(__clang__) 396 #if defined(__i386__) 397 int __cpuid_supported; 398 __asm__(" pushfl\n" 399 " popl %%eax\n" 400 " movl %%eax,%%ecx\n" 401 " xorl $0x00200000,%%eax\n" 402 " pushl %%eax\n" 403 " popfl\n" 404 " pushfl\n" 405 " popl %%eax\n" 406 " movl $0,%0\n" 407 " cmpl %%eax,%%ecx\n" 408 " je 1f\n" 409 " movl $1,%0\n" 410 "1:" 411 : "=r"(__cpuid_supported) 412 : 413 : "eax", "ecx"); 414 if (!__cpuid_supported) 415 return false; 416 #endif 417 return true; 418 #endif 419 return true; 420 } 421 422 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in 423 /// the specified arguments. If we can't run cpuid on the host, return true. 424 static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX, 425 unsigned *rECX, unsigned *rEDX) { 426 #if defined(__GNUC__) || defined(__clang__) 427 #if defined(__x86_64__) 428 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 429 // FIXME: should we save this for Clang? 430 __asm__("movq\t%%rbx, %%rsi\n\t" 431 "cpuid\n\t" 432 "xchgq\t%%rbx, %%rsi\n\t" 433 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 434 : "a"(value)); 435 return false; 436 #elif defined(__i386__) 437 __asm__("movl\t%%ebx, %%esi\n\t" 438 "cpuid\n\t" 439 "xchgl\t%%ebx, %%esi\n\t" 440 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 441 : "a"(value)); 442 return false; 443 #else 444 return true; 445 #endif 446 #elif defined(_MSC_VER) 447 // The MSVC intrinsic is portable across x86 and x64. 448 int registers[4]; 449 __cpuid(registers, value); 450 *rEAX = registers[0]; 451 *rEBX = registers[1]; 452 *rECX = registers[2]; 453 *rEDX = registers[3]; 454 return false; 455 #else 456 return true; 457 #endif 458 } 459 460 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return 461 /// the 4 values in the specified arguments. If we can't run cpuid on the host, 462 /// return true. 463 static bool getX86CpuIDAndInfoEx(unsigned value, unsigned subleaf, 464 unsigned *rEAX, unsigned *rEBX, unsigned *rECX, 465 unsigned *rEDX) { 466 #if defined(__GNUC__) || defined(__clang__) 467 #if defined(__x86_64__) 468 // gcc doesn't know cpuid would clobber ebx/rbx. Preserve it manually. 469 // FIXME: should we save this for Clang? 470 __asm__("movq\t%%rbx, %%rsi\n\t" 471 "cpuid\n\t" 472 "xchgq\t%%rbx, %%rsi\n\t" 473 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 474 : "a"(value), "c"(subleaf)); 475 return false; 476 #elif defined(__i386__) 477 __asm__("movl\t%%ebx, %%esi\n\t" 478 "cpuid\n\t" 479 "xchgl\t%%ebx, %%esi\n\t" 480 : "=a"(*rEAX), "=S"(*rEBX), "=c"(*rECX), "=d"(*rEDX) 481 : "a"(value), "c"(subleaf)); 482 return false; 483 #else 484 return true; 485 #endif 486 #elif defined(_MSC_VER) 487 int registers[4]; 488 __cpuidex(registers, value, subleaf); 489 *rEAX = registers[0]; 490 *rEBX = registers[1]; 491 *rECX = registers[2]; 492 *rEDX = registers[3]; 493 return false; 494 #else 495 return true; 496 #endif 497 } 498 499 // Read control register 0 (XCR0). Used to detect features such as AVX. 500 static bool getX86XCR0(unsigned *rEAX, unsigned *rEDX) { 501 #if defined(__GNUC__) || defined(__clang__) 502 // Check xgetbv; this uses a .byte sequence instead of the instruction 503 // directly because older assemblers do not include support for xgetbv and 504 // there is no easy way to conditionally compile based on the assembler used. 505 __asm__(".byte 0x0f, 0x01, 0xd0" : "=a"(*rEAX), "=d"(*rEDX) : "c"(0)); 506 return false; 507 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) 508 unsigned long long Result = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); 509 *rEAX = Result; 510 *rEDX = Result >> 32; 511 return false; 512 #else 513 return true; 514 #endif 515 } 516 517 static void detectX86FamilyModel(unsigned EAX, unsigned *Family, 518 unsigned *Model) { 519 *Family = (EAX >> 8) & 0xf; // Bits 8 - 11 520 *Model = (EAX >> 4) & 0xf; // Bits 4 - 7 521 if (*Family == 6 || *Family == 0xf) { 522 if (*Family == 0xf) 523 // Examine extended family ID if family ID is F. 524 *Family += (EAX >> 20) & 0xff; // Bits 20 - 27 525 // Examine extended model ID if family ID is 6 or F. 526 *Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19 527 } 528 } 529 530 static void 531 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model, 532 unsigned Brand_id, unsigned Features, 533 unsigned Features2, unsigned *Type, 534 unsigned *Subtype) { 535 if (Brand_id != 0) 536 return; 537 switch (Family) { 538 case 3: 539 *Type = INTEL_i386; 540 break; 541 case 4: 542 switch (Model) { 543 case 0: // Intel486 DX processors 544 case 1: // Intel486 DX processors 545 case 2: // Intel486 SX processors 546 case 3: // Intel487 processors, IntelDX2 OverDrive processors, 547 // IntelDX2 processors 548 case 4: // Intel486 SL processor 549 case 5: // IntelSX2 processors 550 case 7: // Write-Back Enhanced IntelDX2 processors 551 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors 552 default: 553 *Type = INTEL_i486; 554 break; 555 } 556 break; 557 case 5: 558 switch (Model) { 559 case 1: // Pentium OverDrive processor for Pentium processor (60, 66), 560 // Pentium processors (60, 66) 561 case 2: // Pentium OverDrive processor for Pentium processor (75, 90, 562 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, 563 // 150, 166, 200) 564 case 3: // Pentium OverDrive processors for Intel486 processor-based 565 // systems 566 *Type = INTEL_PENTIUM; 567 break; 568 case 4: // Pentium OverDrive processor with MMX technology for Pentium 569 // processor (75, 90, 100, 120, 133), Pentium processor with 570 // MMX technology (166, 200) 571 *Type = INTEL_PENTIUM; 572 *Subtype = INTEL_PENTIUM_MMX; 573 break; 574 default: 575 *Type = INTEL_PENTIUM; 576 break; 577 } 578 break; 579 case 6: 580 switch (Model) { 581 case 0x01: // Pentium Pro processor 582 *Type = INTEL_PENTIUM_PRO; 583 break; 584 case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor, 585 // model 03 586 case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor, 587 // model 05, and Intel Celeron processor, model 05 588 case 0x06: // Celeron processor, model 06 589 *Type = INTEL_PENTIUM_II; 590 break; 591 case 0x07: // Pentium III processor, model 07, and Pentium III Xeon 592 // processor, model 07 593 case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor, 594 // model 08, and Celeron processor, model 08 595 case 0x0a: // Pentium III Xeon processor, model 0Ah 596 case 0x0b: // Pentium III processor, model 0Bh 597 *Type = INTEL_PENTIUM_III; 598 break; 599 case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09. 600 case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model 601 // 0Dh. All processors are manufactured using the 90 nm process. 602 case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579 603 // Integrated Processor with Intel QuickAssist Technology 604 *Type = INTEL_PENTIUM_M; 605 break; 606 case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model 607 // 0Eh. All processors are manufactured using the 65 nm process. 608 *Type = INTEL_CORE_DUO; 609 break; // yonah 610 case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile 611 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad 612 // mobile processor, Intel Core 2 Extreme processor, Intel 613 // Pentium Dual-Core processor, Intel Xeon processor, model 614 // 0Fh. All processors are manufactured using the 65 nm process. 615 case 0x16: // Intel Celeron processor model 16h. All processors are 616 // manufactured using the 65 nm process 617 *Type = INTEL_CORE2; // "core2" 618 *Subtype = INTEL_CORE2_65; 619 break; 620 case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model 621 // 17h. All processors are manufactured using the 45 nm process. 622 // 623 // 45nm: Penryn , Wolfdale, Yorkfield (XE) 624 case 0x1d: // Intel Xeon processor MP. All processors are manufactured using 625 // the 45 nm process. 626 *Type = INTEL_CORE2; // "penryn" 627 *Subtype = INTEL_CORE2_45; 628 break; 629 case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All 630 // processors are manufactured using the 45 nm process. 631 case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz. 632 // As found in a Summer 2010 model iMac. 633 case 0x1f: 634 case 0x2e: // Nehalem EX 635 *Type = INTEL_COREI7; // "nehalem" 636 *Subtype = INTEL_COREI7_NEHALEM; 637 break; 638 case 0x25: // Intel Core i7, laptop version. 639 case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All 640 // processors are manufactured using the 32 nm process. 641 case 0x2f: // Westmere EX 642 *Type = INTEL_COREI7; // "westmere" 643 *Subtype = INTEL_COREI7_WESTMERE; 644 break; 645 case 0x2a: // Intel Core i7 processor. All processors are manufactured 646 // using the 32 nm process. 647 case 0x2d: 648 *Type = INTEL_COREI7; //"sandybridge" 649 *Subtype = INTEL_COREI7_SANDYBRIDGE; 650 break; 651 case 0x3a: 652 case 0x3e: // Ivy Bridge EP 653 *Type = INTEL_COREI7; // "ivybridge" 654 *Subtype = INTEL_COREI7_IVYBRIDGE; 655 break; 656 657 // Haswell: 658 case 0x3c: 659 case 0x3f: 660 case 0x45: 661 case 0x46: 662 *Type = INTEL_COREI7; // "haswell" 663 *Subtype = INTEL_COREI7_HASWELL; 664 break; 665 666 // Broadwell: 667 case 0x3d: 668 case 0x47: 669 case 0x4f: 670 case 0x56: 671 *Type = INTEL_COREI7; // "broadwell" 672 *Subtype = INTEL_COREI7_BROADWELL; 673 break; 674 675 // Skylake: 676 case 0x4e: // Skylake mobile 677 case 0x5e: // Skylake desktop 678 case 0x8e: // Kaby Lake mobile 679 case 0x9e: // Kaby Lake desktop 680 *Type = INTEL_COREI7; // "skylake" 681 *Subtype = INTEL_COREI7_SKYLAKE; 682 break; 683 684 // Skylake Xeon: 685 case 0x55: 686 *Type = INTEL_COREI7; 687 *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512" 688 break; 689 690 case 0x1c: // Most 45 nm Intel Atom processors 691 case 0x26: // 45 nm Atom Lincroft 692 case 0x27: // 32 nm Atom Medfield 693 case 0x35: // 32 nm Atom Midview 694 case 0x36: // 32 nm Atom Midview 695 *Type = INTEL_BONNELL; 696 break; // "bonnell" 697 698 // Atom Silvermont codes from the Intel software optimization guide. 699 case 0x37: 700 case 0x4a: 701 case 0x4d: 702 case 0x5a: 703 case 0x5d: 704 case 0x4c: // really airmont 705 *Type = INTEL_SILVERMONT; 706 break; // "silvermont" 707 // Goldmont: 708 case 0x5c: 709 case 0x5f: 710 *Type = INTEL_GOLDMONT; 711 break; // "goldmont" 712 case 0x57: 713 *Type = INTEL_KNL; // knl 714 break; 715 716 default: // Unknown family 6 CPU, try to guess. 717 if (Features & (1 << FEATURE_AVX512F)) { 718 *Type = INTEL_KNL; // knl 719 break; 720 } 721 if (Features2 & (1 << (FEATURE_ADX - 32))) { 722 *Type = INTEL_COREI7; 723 *Subtype = INTEL_COREI7_BROADWELL; 724 break; 725 } 726 if (Features & (1 << FEATURE_AVX2)) { 727 *Type = INTEL_COREI7; 728 *Subtype = INTEL_COREI7_HASWELL; 729 break; 730 } 731 if (Features & (1 << FEATURE_AVX)) { 732 *Type = INTEL_COREI7; 733 *Subtype = INTEL_COREI7_SANDYBRIDGE; 734 break; 735 } 736 if (Features & (1 << FEATURE_SSE4_2)) { 737 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 738 *Type = INTEL_SILVERMONT; 739 } else { 740 *Type = INTEL_COREI7; 741 *Subtype = INTEL_COREI7_NEHALEM; 742 } 743 break; 744 } 745 if (Features & (1 << FEATURE_SSE4_1)) { 746 *Type = INTEL_CORE2; // "penryn" 747 *Subtype = INTEL_CORE2_45; 748 break; 749 } 750 if (Features & (1 << FEATURE_SSSE3)) { 751 if (Features2 & (1 << (FEATURE_MOVBE - 32))) { 752 *Type = INTEL_BONNELL; // "bonnell" 753 } else { 754 *Type = INTEL_CORE2; // "core2" 755 *Subtype = INTEL_CORE2_65; 756 } 757 break; 758 } 759 if (Features2 & (1 << (FEATURE_EM64T - 32))) { 760 *Type = INTEL_X86_64; 761 break; // x86-64 762 } 763 if (Features & (1 << FEATURE_SSE2)) { 764 *Type = INTEL_PENTIUM_M; 765 break; 766 } 767 if (Features & (1 << FEATURE_SSE)) { 768 *Type = INTEL_PENTIUM_III; 769 break; 770 } 771 if (Features & (1 << FEATURE_MMX)) { 772 *Type = INTEL_PENTIUM_II; 773 break; 774 } 775 *Type = INTEL_PENTIUM_PRO; 776 break; 777 } 778 break; 779 case 15: { 780 switch (Model) { 781 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are 782 // model 00h and manufactured using the 0.18 micron process. 783 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon 784 // processor MP, and Intel Celeron processor. All processors are 785 // model 01h and manufactured using the 0.18 micron process. 786 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, 787 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron 788 // processor, and Mobile Intel Celeron processor. All processors 789 // are model 02h and manufactured using the 0.13 micron process. 790 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 791 : INTEL_PENTIUM_IV); 792 break; 793 794 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D 795 // processor. All processors are model 03h and manufactured using 796 // the 90 nm process. 797 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition, 798 // Pentium D processor, Intel Xeon processor, Intel Xeon 799 // processor MP, Intel Celeron D processor. All processors are 800 // model 04h and manufactured using the 90 nm process. 801 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor 802 // Extreme Edition, Intel Xeon processor, Intel Xeon processor 803 // MP, Intel Celeron D processor. All processors are model 06h 804 // and manufactured using the 65 nm process. 805 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_NOCONA 806 : INTEL_PRESCOTT); 807 break; 808 809 default: 810 *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64 811 : INTEL_PENTIUM_IV); 812 break; 813 } 814 break; 815 } 816 default: 817 break; /*"generic"*/ 818 } 819 } 820 821 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model, 822 unsigned Features, unsigned *Type, 823 unsigned *Subtype) { 824 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There 825 // appears to be no way to generate the wide variety of AMD-specific targets 826 // from the information returned from CPUID. 827 switch (Family) { 828 case 4: 829 *Type = AMD_i486; 830 break; 831 case 5: 832 *Type = AMDPENTIUM; 833 switch (Model) { 834 case 6: 835 case 7: 836 *Subtype = AMDPENTIUM_K6; 837 break; // "k6" 838 case 8: 839 *Subtype = AMDPENTIUM_K62; 840 break; // "k6-2" 841 case 9: 842 case 13: 843 *Subtype = AMDPENTIUM_K63; 844 break; // "k6-3" 845 case 10: 846 *Subtype = AMDPENTIUM_GEODE; 847 break; // "geode" 848 } 849 break; 850 case 6: 851 *Type = AMDATHLON; 852 if (Features & (1 << FEATURE_SSE)) { 853 *Subtype = AMDATHLON_XP; 854 break; // "athlon-xp" 855 } 856 *Subtype = AMDATHLON_CLASSIC; 857 break; // "athlon" 858 case 15: 859 *Type = AMDATHLON; 860 if (Features & (1 << FEATURE_SSE3)) { 861 *Subtype = AMDATHLON_K8SSE3; 862 break; // "k8-sse3" 863 } 864 *Subtype = AMDATHLON_K8; 865 break; // "k8" 866 case 16: 867 *Type = AMDFAM10H; // "amdfam10" 868 switch (Model) { 869 case 2: 870 *Subtype = AMDFAM10H_BARCELONA; 871 break; 872 case 4: 873 *Subtype = AMDFAM10H_SHANGHAI; 874 break; 875 case 8: 876 *Subtype = AMDFAM10H_ISTANBUL; 877 break; 878 } 879 break; 880 case 20: 881 *Type = AMD_BTVER1; 882 break; // "btver1"; 883 case 21: 884 *Type = AMDFAM15H; 885 if (Model >= 0x60 && Model <= 0x7f) { 886 *Subtype = AMDFAM15H_BDVER4; 887 break; // "bdver4"; 60h-7Fh: Excavator 888 } 889 if (Model >= 0x30 && Model <= 0x3f) { 890 *Subtype = AMDFAM15H_BDVER3; 891 break; // "bdver3"; 30h-3Fh: Steamroller 892 } 893 if (Model >= 0x10 && Model <= 0x1f) { 894 *Subtype = AMDFAM15H_BDVER2; 895 break; // "bdver2"; 10h-1Fh: Piledriver 896 } 897 if (Model <= 0x0f) { 898 *Subtype = AMDFAM15H_BDVER1; 899 break; // "bdver1"; 00h-0Fh: Bulldozer 900 } 901 break; 902 case 22: 903 *Type = AMD_BTVER2; 904 break; // "btver2" 905 case 23: 906 *Type = AMDFAM17H; 907 *Subtype = AMDFAM17H_ZNVER1; 908 break; 909 default: 910 break; // "generic" 911 } 912 } 913 914 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, 915 unsigned *FeaturesOut, 916 unsigned *Features2Out) { 917 unsigned Features = 0; 918 unsigned Features2 = 0; 919 unsigned EAX, EBX; 920 921 if ((EDX >> 15) & 1) 922 Features |= 1 << FEATURE_CMOV; 923 if ((EDX >> 23) & 1) 924 Features |= 1 << FEATURE_MMX; 925 if ((EDX >> 25) & 1) 926 Features |= 1 << FEATURE_SSE; 927 if ((EDX >> 26) & 1) 928 Features |= 1 << FEATURE_SSE2; 929 930 if ((ECX >> 0) & 1) 931 Features |= 1 << FEATURE_SSE3; 932 if ((ECX >> 1) & 1) 933 Features |= 1 << FEATURE_PCLMUL; 934 if ((ECX >> 9) & 1) 935 Features |= 1 << FEATURE_SSSE3; 936 if ((ECX >> 12) & 1) 937 Features |= 1 << FEATURE_FMA; 938 if ((ECX >> 19) & 1) 939 Features |= 1 << FEATURE_SSE4_1; 940 if ((ECX >> 20) & 1) 941 Features |= 1 << FEATURE_SSE4_2; 942 if ((ECX >> 23) & 1) 943 Features |= 1 << FEATURE_POPCNT; 944 if ((ECX >> 25) & 1) 945 Features |= 1 << FEATURE_AES; 946 947 if ((ECX >> 22) & 1) 948 Features2 |= 1 << (FEATURE_MOVBE - 32); 949 950 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 951 // indicates that the AVX registers will be saved and restored on context 952 // switch, then we have full AVX support. 953 const unsigned AVXBits = (1 << 27) | (1 << 28); 954 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && 955 ((EAX & 0x6) == 0x6); 956 bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0); 957 958 if (HasAVX) 959 Features |= 1 << FEATURE_AVX; 960 961 bool HasLeaf7 = 962 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 963 964 if (HasLeaf7 && ((EBX >> 3) & 1)) 965 Features |= 1 << FEATURE_BMI; 966 if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX) 967 Features |= 1 << FEATURE_AVX2; 968 if (HasLeaf7 && ((EBX >> 9) & 1)) 969 Features |= 1 << FEATURE_BMI2; 970 if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) 971 Features |= 1 << FEATURE_AVX512F; 972 if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) 973 Features |= 1 << FEATURE_AVX512DQ; 974 if (HasLeaf7 && ((EBX >> 19) & 1)) 975 Features2 |= 1 << (FEATURE_ADX - 32); 976 if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save) 977 Features |= 1 << FEATURE_AVX512IFMA; 978 if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save) 979 Features |= 1 << FEATURE_AVX512PF; 980 if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save) 981 Features |= 1 << FEATURE_AVX512ER; 982 if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save) 983 Features |= 1 << FEATURE_AVX512CD; 984 if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save) 985 Features |= 1 << FEATURE_AVX512BW; 986 if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save) 987 Features |= 1 << FEATURE_AVX512VL; 988 989 if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save) 990 Features |= 1 << FEATURE_AVX512VBMI; 991 if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save) 992 Features |= 1 << FEATURE_AVX512VPOPCNTDQ; 993 994 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) 995 Features |= 1 << FEATURE_AVX5124VNNIW; 996 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) 997 Features |= 1 << FEATURE_AVX5124FMAPS; 998 999 unsigned MaxExtLevel; 1000 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1001 1002 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1003 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1004 if (HasExtLeaf1 && ((ECX >> 6) & 1)) 1005 Features |= 1 << FEATURE_SSE4_A; 1006 if (HasExtLeaf1 && ((ECX >> 11) & 1)) 1007 Features |= 1 << FEATURE_XOP; 1008 if (HasExtLeaf1 && ((ECX >> 16) & 1)) 1009 Features |= 1 << FEATURE_FMA4; 1010 1011 if (HasExtLeaf1 && ((EDX >> 29) & 1)) 1012 Features2 |= 1 << (FEATURE_EM64T - 32); 1013 1014 *FeaturesOut = Features; 1015 *Features2Out = Features2; 1016 } 1017 1018 StringRef sys::getHostCPUName() { 1019 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1020 unsigned MaxLeaf, Vendor; 1021 1022 #if defined(__GNUC__) || defined(__clang__) 1023 //FIXME: include cpuid.h from clang or copy __get_cpuid_max here 1024 // and simplify it to not invoke __cpuid (like cpu_model.c in 1025 // compiler-rt/lib/builtins/cpu_model.c? 1026 // Opting for the second option. 1027 if(!isCpuIdSupported()) 1028 return "generic"; 1029 #endif 1030 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1) 1031 return "generic"; 1032 getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); 1033 1034 unsigned Brand_id = EBX & 0xff; 1035 unsigned Family = 0, Model = 0; 1036 unsigned Features = 0, Features2 = 0; 1037 detectX86FamilyModel(EAX, &Family, &Model); 1038 getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2); 1039 1040 unsigned Type; 1041 unsigned Subtype; 1042 1043 if (Vendor == SIG_INTEL) { 1044 getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, 1045 Features2, &Type, &Subtype); 1046 switch (Type) { 1047 case INTEL_i386: 1048 return "i386"; 1049 case INTEL_i486: 1050 return "i486"; 1051 case INTEL_PENTIUM: 1052 if (Subtype == INTEL_PENTIUM_MMX) 1053 return "pentium-mmx"; 1054 return "pentium"; 1055 case INTEL_PENTIUM_PRO: 1056 return "pentiumpro"; 1057 case INTEL_PENTIUM_II: 1058 return "pentium2"; 1059 case INTEL_PENTIUM_III: 1060 return "pentium3"; 1061 case INTEL_PENTIUM_IV: 1062 return "pentium4"; 1063 case INTEL_PENTIUM_M: 1064 return "pentium-m"; 1065 case INTEL_CORE_DUO: 1066 return "yonah"; 1067 case INTEL_CORE2: 1068 switch (Subtype) { 1069 case INTEL_CORE2_65: 1070 return "core2"; 1071 case INTEL_CORE2_45: 1072 return "penryn"; 1073 default: 1074 llvm_unreachable("Unexpected subtype!"); 1075 } 1076 case INTEL_COREI7: 1077 switch (Subtype) { 1078 case INTEL_COREI7_NEHALEM: 1079 return "nehalem"; 1080 case INTEL_COREI7_WESTMERE: 1081 return "westmere"; 1082 case INTEL_COREI7_SANDYBRIDGE: 1083 return "sandybridge"; 1084 case INTEL_COREI7_IVYBRIDGE: 1085 return "ivybridge"; 1086 case INTEL_COREI7_HASWELL: 1087 return "haswell"; 1088 case INTEL_COREI7_BROADWELL: 1089 return "broadwell"; 1090 case INTEL_COREI7_SKYLAKE: 1091 return "skylake"; 1092 case INTEL_COREI7_SKYLAKE_AVX512: 1093 return "skylake-avx512"; 1094 default: 1095 llvm_unreachable("Unexpected subtype!"); 1096 } 1097 case INTEL_BONNELL: 1098 return "bonnell"; 1099 case INTEL_SILVERMONT: 1100 return "silvermont"; 1101 case INTEL_GOLDMONT: 1102 return "goldmont"; 1103 case INTEL_KNL: 1104 return "knl"; 1105 case INTEL_X86_64: 1106 return "x86-64"; 1107 case INTEL_NOCONA: 1108 return "nocona"; 1109 case INTEL_PRESCOTT: 1110 return "prescott"; 1111 default: 1112 break; 1113 } 1114 } else if (Vendor == SIG_AMD) { 1115 getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype); 1116 switch (Type) { 1117 case AMD_i486: 1118 return "i486"; 1119 case AMDPENTIUM: 1120 switch (Subtype) { 1121 case AMDPENTIUM_K6: 1122 return "k6"; 1123 case AMDPENTIUM_K62: 1124 return "k6-2"; 1125 case AMDPENTIUM_K63: 1126 return "k6-3"; 1127 case AMDPENTIUM_GEODE: 1128 return "geode"; 1129 default: 1130 return "pentium"; 1131 } 1132 case AMDATHLON: 1133 switch (Subtype) { 1134 case AMDATHLON_CLASSIC: 1135 return "athlon"; 1136 case AMDATHLON_XP: 1137 return "athlon-xp"; 1138 case AMDATHLON_K8: 1139 return "k8"; 1140 case AMDATHLON_K8SSE3: 1141 return "k8-sse3"; 1142 default: 1143 llvm_unreachable("Unexpected subtype!"); 1144 } 1145 case AMDFAM10H: 1146 return "amdfam10"; 1147 case AMD_BTVER1: 1148 return "btver1"; 1149 case AMDFAM15H: 1150 switch (Subtype) { 1151 default: // There are gaps in the subtype detection. 1152 case AMDFAM15H_BDVER1: 1153 return "bdver1"; 1154 case AMDFAM15H_BDVER2: 1155 return "bdver2"; 1156 case AMDFAM15H_BDVER3: 1157 return "bdver3"; 1158 case AMDFAM15H_BDVER4: 1159 return "bdver4"; 1160 } 1161 case AMD_BTVER2: 1162 return "btver2"; 1163 case AMDFAM17H: 1164 return "znver1"; 1165 default: 1166 break; 1167 } 1168 } 1169 return "generic"; 1170 } 1171 1172 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__)) 1173 StringRef sys::getHostCPUName() { 1174 host_basic_info_data_t hostInfo; 1175 mach_msg_type_number_t infoCount; 1176 1177 infoCount = HOST_BASIC_INFO_COUNT; 1178 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo, 1179 &infoCount); 1180 1181 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) 1182 return "generic"; 1183 1184 switch (hostInfo.cpu_subtype) { 1185 case CPU_SUBTYPE_POWERPC_601: 1186 return "601"; 1187 case CPU_SUBTYPE_POWERPC_602: 1188 return "602"; 1189 case CPU_SUBTYPE_POWERPC_603: 1190 return "603"; 1191 case CPU_SUBTYPE_POWERPC_603e: 1192 return "603e"; 1193 case CPU_SUBTYPE_POWERPC_603ev: 1194 return "603ev"; 1195 case CPU_SUBTYPE_POWERPC_604: 1196 return "604"; 1197 case CPU_SUBTYPE_POWERPC_604e: 1198 return "604e"; 1199 case CPU_SUBTYPE_POWERPC_620: 1200 return "620"; 1201 case CPU_SUBTYPE_POWERPC_750: 1202 return "750"; 1203 case CPU_SUBTYPE_POWERPC_7400: 1204 return "7400"; 1205 case CPU_SUBTYPE_POWERPC_7450: 1206 return "7450"; 1207 case CPU_SUBTYPE_POWERPC_970: 1208 return "970"; 1209 default:; 1210 } 1211 1212 return "generic"; 1213 } 1214 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__)) 1215 StringRef sys::getHostCPUName() { 1216 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1217 const StringRef& Content = P ? P->getBuffer() : ""; 1218 return detail::getHostCPUNameForPowerPC(Content); 1219 } 1220 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1221 StringRef sys::getHostCPUName() { 1222 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1223 const StringRef& Content = P ? P->getBuffer() : ""; 1224 return detail::getHostCPUNameForARM(Content); 1225 } 1226 #elif defined(__linux__) && defined(__s390x__) 1227 StringRef sys::getHostCPUName() { 1228 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1229 const StringRef& Content = P ? P->getBuffer() : ""; 1230 return detail::getHostCPUNameForS390x(Content); 1231 } 1232 #else 1233 StringRef sys::getHostCPUName() { return "generic"; } 1234 #endif 1235 1236 #if defined(__linux__) && defined(__x86_64__) 1237 // On Linux, the number of physical cores can be computed from /proc/cpuinfo, 1238 // using the number of unique physical/core id pairs. The following 1239 // implementation reads the /proc/cpuinfo format on an x86_64 system. 1240 static int computeHostNumPhysicalCores() { 1241 // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be 1242 // mmapped because it appears to have 0 size. 1243 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> Text = 1244 llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); 1245 if (std::error_code EC = Text.getError()) { 1246 llvm::errs() << "Can't read " 1247 << "/proc/cpuinfo: " << EC.message() << "\n"; 1248 return -1; 1249 } 1250 SmallVector<StringRef, 8> strs; 1251 (*Text)->getBuffer().split(strs, "\n", /*MaxSplit=*/-1, 1252 /*KeepEmpty=*/false); 1253 int CurPhysicalId = -1; 1254 int CurCoreId = -1; 1255 SmallSet<std::pair<int, int>, 32> UniqueItems; 1256 for (auto &Line : strs) { 1257 Line = Line.trim(); 1258 if (!Line.startswith("physical id") && !Line.startswith("core id")) 1259 continue; 1260 std::pair<StringRef, StringRef> Data = Line.split(':'); 1261 auto Name = Data.first.trim(); 1262 auto Val = Data.second.trim(); 1263 if (Name == "physical id") { 1264 assert(CurPhysicalId == -1 && 1265 "Expected a core id before seeing another physical id"); 1266 Val.getAsInteger(10, CurPhysicalId); 1267 } 1268 if (Name == "core id") { 1269 assert(CurCoreId == -1 && 1270 "Expected a physical id before seeing another core id"); 1271 Val.getAsInteger(10, CurCoreId); 1272 } 1273 if (CurPhysicalId != -1 && CurCoreId != -1) { 1274 UniqueItems.insert(std::make_pair(CurPhysicalId, CurCoreId)); 1275 CurPhysicalId = -1; 1276 CurCoreId = -1; 1277 } 1278 } 1279 return UniqueItems.size(); 1280 } 1281 #elif defined(__APPLE__) && defined(__x86_64__) 1282 #include <sys/param.h> 1283 #include <sys/sysctl.h> 1284 1285 // Gets the number of *physical cores* on the machine. 1286 static int computeHostNumPhysicalCores() { 1287 uint32_t count; 1288 size_t len = sizeof(count); 1289 sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); 1290 if (count < 1) { 1291 int nm[2]; 1292 nm[0] = CTL_HW; 1293 nm[1] = HW_AVAILCPU; 1294 sysctl(nm, 2, &count, &len, NULL, 0); 1295 if (count < 1) 1296 return -1; 1297 } 1298 return count; 1299 } 1300 #else 1301 // On other systems, return -1 to indicate unknown. 1302 static int computeHostNumPhysicalCores() { return -1; } 1303 #endif 1304 1305 int sys::getHostNumPhysicalCores() { 1306 static int NumCores = computeHostNumPhysicalCores(); 1307 return NumCores; 1308 } 1309 1310 #if defined(__i386__) || defined(_M_IX86) || \ 1311 defined(__x86_64__) || defined(_M_X64) 1312 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1313 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; 1314 unsigned MaxLevel; 1315 union { 1316 unsigned u[3]; 1317 char c[12]; 1318 } text; 1319 1320 if (getX86CpuIDAndInfo(0, &MaxLevel, text.u + 0, text.u + 2, text.u + 1) || 1321 MaxLevel < 1) 1322 return false; 1323 1324 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); 1325 1326 Features["cmov"] = (EDX >> 15) & 1; 1327 Features["mmx"] = (EDX >> 23) & 1; 1328 Features["sse"] = (EDX >> 25) & 1; 1329 Features["sse2"] = (EDX >> 26) & 1; 1330 Features["sse3"] = (ECX >> 0) & 1; 1331 Features["ssse3"] = (ECX >> 9) & 1; 1332 Features["sse4.1"] = (ECX >> 19) & 1; 1333 Features["sse4.2"] = (ECX >> 20) & 1; 1334 1335 Features["pclmul"] = (ECX >> 1) & 1; 1336 Features["cx16"] = (ECX >> 13) & 1; 1337 Features["movbe"] = (ECX >> 22) & 1; 1338 Features["popcnt"] = (ECX >> 23) & 1; 1339 Features["aes"] = (ECX >> 25) & 1; 1340 Features["rdrnd"] = (ECX >> 30) & 1; 1341 1342 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV 1343 // indicates that the AVX registers will be saved and restored on context 1344 // switch, then we have full AVX support. 1345 bool HasAVXSave = ((ECX >> 27) & 1) && ((ECX >> 28) & 1) && 1346 !getX86XCR0(&EAX, &EDX) && ((EAX & 0x6) == 0x6); 1347 Features["avx"] = HasAVXSave; 1348 Features["fma"] = HasAVXSave && (ECX >> 12) & 1; 1349 Features["f16c"] = HasAVXSave && (ECX >> 29) & 1; 1350 1351 // Only enable XSAVE if OS has enabled support for saving YMM state. 1352 Features["xsave"] = HasAVXSave && (ECX >> 26) & 1; 1353 1354 // AVX512 requires additional context to be saved by the OS. 1355 bool HasAVX512Save = HasAVXSave && ((EAX & 0xe0) == 0xe0); 1356 1357 unsigned MaxExtLevel; 1358 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); 1359 1360 bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 && 1361 !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); 1362 Features["lzcnt"] = HasExtLeaf1 && ((ECX >> 5) & 1); 1363 Features["sse4a"] = HasExtLeaf1 && ((ECX >> 6) & 1); 1364 Features["prfchw"] = HasExtLeaf1 && ((ECX >> 8) & 1); 1365 Features["xop"] = HasExtLeaf1 && ((ECX >> 11) & 1) && HasAVXSave; 1366 Features["lwp"] = HasExtLeaf1 && ((ECX >> 15) & 1); 1367 Features["fma4"] = HasExtLeaf1 && ((ECX >> 16) & 1) && HasAVXSave; 1368 Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1); 1369 Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1); 1370 1371 bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 && 1372 !getX86CpuIDAndInfoEx(0x80000008,0x0, &EAX, &EBX, &ECX, &EDX); 1373 Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1); 1374 1375 bool HasLeaf7 = 1376 MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); 1377 1378 // AVX2 is only supported if we have the OS save support from AVX. 1379 Features["avx2"] = HasAVXSave && HasLeaf7 && ((EBX >> 5) & 1); 1380 1381 Features["fsgsbase"] = HasLeaf7 && ((EBX >> 0) & 1); 1382 Features["sgx"] = HasLeaf7 && ((EBX >> 2) & 1); 1383 Features["bmi"] = HasLeaf7 && ((EBX >> 3) & 1); 1384 Features["bmi2"] = HasLeaf7 && ((EBX >> 8) & 1); 1385 Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); 1386 Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); 1387 Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); 1388 Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); 1389 Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); 1390 Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); 1391 1392 // AVX512 is only supported if the OS supports the context save for it. 1393 Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; 1394 Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; 1395 Features["avx512ifma"] = HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save; 1396 Features["avx512pf"] = HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save; 1397 Features["avx512er"] = HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save; 1398 Features["avx512cd"] = HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save; 1399 Features["avx512bw"] = HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save; 1400 Features["avx512vl"] = HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save; 1401 1402 Features["prefetchwt1"] = HasLeaf7 && (ECX & 1); 1403 Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save; 1404 Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save; 1405 // Enable protection keys 1406 Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1); 1407 1408 bool HasLeafD = MaxLevel >= 0xd && 1409 !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX); 1410 1411 // Only enable XSAVE if OS has enabled support for saving YMM state. 1412 Features["xsaveopt"] = HasAVXSave && HasLeafD && ((EAX >> 0) & 1); 1413 Features["xsavec"] = HasAVXSave && HasLeafD && ((EAX >> 1) & 1); 1414 Features["xsaves"] = HasAVXSave && HasLeafD && ((EAX >> 3) & 1); 1415 1416 return true; 1417 } 1418 #elif defined(__linux__) && (defined(__arm__) || defined(__aarch64__)) 1419 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { 1420 std::unique_ptr<llvm::MemoryBuffer> P = getProcCpuinfoContent(); 1421 if (!P) 1422 return false; 1423 1424 SmallVector<StringRef, 32> Lines; 1425 P->getBuffer().split(Lines, "\n"); 1426 1427 SmallVector<StringRef, 32> CPUFeatures; 1428 1429 // Look for the CPU features. 1430 for (unsigned I = 0, E = Lines.size(); I != E; ++I) 1431 if (Lines[I].startswith("Features")) { 1432 Lines[I].split(CPUFeatures, ' '); 1433 break; 1434 } 1435 1436 #if defined(__aarch64__) 1437 // Keep track of which crypto features we have seen 1438 enum { CAP_AES = 0x1, CAP_PMULL = 0x2, CAP_SHA1 = 0x4, CAP_SHA2 = 0x8 }; 1439 uint32_t crypto = 0; 1440 #endif 1441 1442 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) { 1443 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I]) 1444 #if defined(__aarch64__) 1445 .Case("asimd", "neon") 1446 .Case("fp", "fp-armv8") 1447 .Case("crc32", "crc") 1448 #else 1449 .Case("half", "fp16") 1450 .Case("neon", "neon") 1451 .Case("vfpv3", "vfp3") 1452 .Case("vfpv3d16", "d16") 1453 .Case("vfpv4", "vfp4") 1454 .Case("idiva", "hwdiv-arm") 1455 .Case("idivt", "hwdiv") 1456 #endif 1457 .Default(""); 1458 1459 #if defined(__aarch64__) 1460 // We need to check crypto separately since we need all of the crypto 1461 // extensions to enable the subtarget feature 1462 if (CPUFeatures[I] == "aes") 1463 crypto |= CAP_AES; 1464 else if (CPUFeatures[I] == "pmull") 1465 crypto |= CAP_PMULL; 1466 else if (CPUFeatures[I] == "sha1") 1467 crypto |= CAP_SHA1; 1468 else if (CPUFeatures[I] == "sha2") 1469 crypto |= CAP_SHA2; 1470 #endif 1471 1472 if (LLVMFeatureStr != "") 1473 Features[LLVMFeatureStr] = true; 1474 } 1475 1476 #if defined(__aarch64__) 1477 // If we have all crypto bits we can add the feature 1478 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2)) 1479 Features["crypto"] = true; 1480 #endif 1481 1482 return true; 1483 } 1484 #else 1485 bool sys::getHostCPUFeatures(StringMap<bool> &Features) { return false; } 1486 #endif 1487 1488 std::string sys::getProcessTriple() { 1489 std::string TargetTripleString = updateTripleOSVersion(LLVM_HOST_TRIPLE); 1490 Triple PT(Triple::normalize(TargetTripleString)); 1491 1492 if (sizeof(void *) == 8 && PT.isArch32Bit()) 1493 PT = PT.get64BitArchVariant(); 1494 if (sizeof(void *) == 4 && PT.isArch64Bit()) 1495 PT = PT.get32BitArchVariant(); 1496 1497 return PT.str(); 1498 } 1499