1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TargetRegisterInfo interface.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/TargetRegisterInfo.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/TargetFrameLowering.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/CodeGen/VirtRegMap.h"
26 #include "llvm/Config/llvm-config.h"
27 #include "llvm/IR/Attributes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCRegisterInfo.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MachineValueType.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/Printable.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include <cassert>
37 #include <utility>
38 
39 #define DEBUG_TYPE "target-reg-info"
40 
41 using namespace llvm;
42 
43 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
44                              regclass_iterator RCB, regclass_iterator RCE,
45                              const char *const *SRINames,
46                              const LaneBitmask *SRILaneMasks,
47                              LaneBitmask SRICoveringLanes,
48                              const RegClassInfo *const RCIs,
49                              unsigned Mode)
50   : InfoDesc(ID), SubRegIndexNames(SRINames),
51     SubRegIndexLaneMasks(SRILaneMasks),
52     RegClassBegin(RCB), RegClassEnd(RCE),
53     CoveringLanes(SRICoveringLanes),
54     RCInfos(RCIs), HwMode(Mode) {
55 }
56 
57 TargetRegisterInfo::~TargetRegisterInfo() = default;
58 
59 void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg)
60     const {
61   for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
62     RegisterSet.set(*AI);
63 }
64 
65 bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet,
66     ArrayRef<MCPhysReg> Exceptions) const {
67   // Check that all super registers of reserved regs are reserved as well.
68   BitVector Checked(getNumRegs());
69   for (unsigned Reg : RegisterSet.set_bits()) {
70     if (Checked[Reg])
71       continue;
72     for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
73       if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
74         dbgs() << "Error: Super register " << printReg(*SR, this)
75                << " of reserved register " << printReg(Reg, this)
76                << " is not reserved.\n";
77         return false;
78       }
79 
80       // We transitively check superregs. So we can remember this for later
81       // to avoid compiletime explosion in deep register hierarchies.
82       Checked.set(*SR);
83     }
84   }
85   return true;
86 }
87 
88 namespace llvm {
89 
90 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI,
91                    unsigned SubIdx, const MachineRegisterInfo *MRI) {
92   return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
93     if (!Reg)
94       OS << "$noreg";
95     else if (TargetRegisterInfo::isStackSlot(Reg))
96       OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
97     else if (TargetRegisterInfo::isVirtualRegister(Reg)) {
98       StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
99       if (Name != "") {
100         OS << '%' << Name;
101       } else {
102         OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
103       }
104     }
105     else if (!TRI)
106       OS << '$' << "physreg" << Reg;
107     else if (Reg < TRI->getNumRegs()) {
108       OS << '$';
109       printLowerCase(TRI->getName(Reg), OS);
110     } else
111       llvm_unreachable("Register kind is unsupported.");
112 
113     if (SubIdx) {
114       if (TRI)
115         OS << ':' << TRI->getSubRegIndexName(SubIdx);
116       else
117         OS << ":sub(" << SubIdx << ')';
118     }
119   });
120 }
121 
122 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
123   return Printable([Unit, TRI](raw_ostream &OS) {
124     // Generic printout when TRI is missing.
125     if (!TRI) {
126       OS << "Unit~" << Unit;
127       return;
128     }
129 
130     // Check for invalid register units.
131     if (Unit >= TRI->getNumRegUnits()) {
132       OS << "BadUnit~" << Unit;
133       return;
134     }
135 
136     // Normal units have at least one root.
137     MCRegUnitRootIterator Roots(Unit, TRI);
138     assert(Roots.isValid() && "Unit has no roots.");
139     OS << TRI->getName(*Roots);
140     for (++Roots; Roots.isValid(); ++Roots)
141       OS << '~' << TRI->getName(*Roots);
142   });
143 }
144 
145 Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
146   return Printable([Unit, TRI](raw_ostream &OS) {
147     if (TRI && TRI->isVirtualRegister(Unit)) {
148       OS << '%' << TargetRegisterInfo::virtReg2Index(Unit);
149     } else {
150       OS << printRegUnit(Unit, TRI);
151     }
152   });
153 }
154 
155 Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
156                               const TargetRegisterInfo *TRI) {
157   return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
158     if (RegInfo.getRegClassOrNull(Reg))
159       OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
160     else if (RegInfo.getRegBankOrNull(Reg))
161       OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
162     else {
163       OS << "_";
164       assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
165              "Generic registers must have a valid type");
166     }
167   });
168 }
169 
170 } // end namespace llvm
171 
172 /// getAllocatableClass - Return the maximal subclass of the given register
173 /// class that is alloctable, or NULL.
174 const TargetRegisterClass *
175 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
176   if (!RC || RC->isAllocatable())
177     return RC;
178 
179   for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
180        ++It) {
181     const TargetRegisterClass *SubRC = getRegClass(It.getID());
182     if (SubRC->isAllocatable())
183       return SubRC;
184   }
185   return nullptr;
186 }
187 
188 /// getMinimalPhysRegClass - Returns the Register Class of a physical
189 /// register of the given type, picking the most sub register class of
190 /// the right type that contains this physreg.
191 const TargetRegisterClass *
192 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const {
193   assert(isPhysicalRegister(reg) && "reg must be a physical register");
194 
195   // Pick the most sub register class of the right type that contains
196   // this physreg.
197   const TargetRegisterClass* BestRC = nullptr;
198   for (const TargetRegisterClass* RC : regclasses()) {
199     if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
200         RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
201       BestRC = RC;
202   }
203 
204   assert(BestRC && "Couldn't find the register class");
205   return BestRC;
206 }
207 
208 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
209 /// registers for the specific register class.
210 static void getAllocatableSetForRC(const MachineFunction &MF,
211                                    const TargetRegisterClass *RC, BitVector &R){
212   assert(RC->isAllocatable() && "invalid for nonallocatable sets");
213   ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
214   for (unsigned i = 0; i != Order.size(); ++i)
215     R.set(Order[i]);
216 }
217 
218 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
219                                           const TargetRegisterClass *RC) const {
220   BitVector Allocatable(getNumRegs());
221   if (RC) {
222     // A register class with no allocatable subclass returns an empty set.
223     const TargetRegisterClass *SubClass = getAllocatableClass(RC);
224     if (SubClass)
225       getAllocatableSetForRC(MF, SubClass, Allocatable);
226   } else {
227     for (const TargetRegisterClass *C : regclasses())
228       if (C->isAllocatable())
229         getAllocatableSetForRC(MF, C, Allocatable);
230   }
231 
232   // Mask out the reserved registers
233   BitVector Reserved = getReservedRegs(MF);
234   Allocatable &= Reserved.flip();
235 
236   return Allocatable;
237 }
238 
239 static inline
240 const TargetRegisterClass *firstCommonClass(const uint32_t *A,
241                                             const uint32_t *B,
242                                             const TargetRegisterInfo *TRI,
243                                             const MVT::SimpleValueType SVT =
244                                             MVT::SimpleValueType::Any) {
245   const MVT VT(SVT);
246   for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
247     if (unsigned Common = *A++ & *B++) {
248       const TargetRegisterClass *RC =
249           TRI->getRegClass(I + countTrailingZeros(Common));
250       if (SVT == MVT::SimpleValueType::Any || TRI->isTypeLegalForClass(*RC, VT))
251         return RC;
252     }
253   return nullptr;
254 }
255 
256 const TargetRegisterClass *
257 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
258                                       const TargetRegisterClass *B,
259                                       const MVT::SimpleValueType SVT) const {
260   // First take care of the trivial cases.
261   if (A == B)
262     return A;
263   if (!A || !B)
264     return nullptr;
265 
266   // Register classes are ordered topologically, so the largest common
267   // sub-class it the common sub-class with the smallest ID.
268   return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT);
269 }
270 
271 const TargetRegisterClass *
272 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
273                                              const TargetRegisterClass *B,
274                                              unsigned Idx) const {
275   assert(A && B && "Missing register class");
276   assert(Idx && "Bad sub-register index");
277 
278   // Find Idx in the list of super-register indices.
279   for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
280     if (RCI.getSubReg() == Idx)
281       // The bit mask contains all register classes that are projected into B
282       // by Idx. Find a class that is also a sub-class of A.
283       return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
284   return nullptr;
285 }
286 
287 const TargetRegisterClass *TargetRegisterInfo::
288 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
289                        const TargetRegisterClass *RCB, unsigned SubB,
290                        unsigned &PreA, unsigned &PreB) const {
291   assert(RCA && SubA && RCB && SubB && "Invalid arguments");
292 
293   // Search all pairs of sub-register indices that project into RCA and RCB
294   // respectively. This is quadratic, but usually the sets are very small. On
295   // most targets like X86, there will only be a single sub-register index
296   // (e.g., sub_16bit projecting into GR16).
297   //
298   // The worst case is a register class like DPR on ARM.
299   // We have indices dsub_0..dsub_7 projecting into that class.
300   //
301   // It is very common that one register class is a sub-register of the other.
302   // Arrange for RCA to be the larger register so the answer will be found in
303   // the first iteration. This makes the search linear for the most common
304   // case.
305   const TargetRegisterClass *BestRC = nullptr;
306   unsigned *BestPreA = &PreA;
307   unsigned *BestPreB = &PreB;
308   if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
309     std::swap(RCA, RCB);
310     std::swap(SubA, SubB);
311     std::swap(BestPreA, BestPreB);
312   }
313 
314   // Also terminate the search one we have found a register class as small as
315   // RCA.
316   unsigned MinSize = getRegSizeInBits(*RCA);
317 
318   for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
319     unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
320     for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
321       // Check if a common super-register class exists for this index pair.
322       const TargetRegisterClass *RC =
323         firstCommonClass(IA.getMask(), IB.getMask(), this);
324       if (!RC || getRegSizeInBits(*RC) < MinSize)
325         continue;
326 
327       // The indexes must compose identically: PreA+SubA == PreB+SubB.
328       unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
329       if (FinalA != FinalB)
330         continue;
331 
332       // Is RC a better candidate than BestRC?
333       if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
334         continue;
335 
336       // Yes, RC is the smallest super-register seen so far.
337       BestRC = RC;
338       *BestPreA = IA.getSubReg();
339       *BestPreB = IB.getSubReg();
340 
341       // Bail early if we reached MinSize. We won't find a better candidate.
342       if (getRegSizeInBits(*BestRC) == MinSize)
343         return BestRC;
344     }
345   }
346   return BestRC;
347 }
348 
349 /// Check if the registers defined by the pair (RegisterClass, SubReg)
350 /// share the same register file.
351 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
352                                   const TargetRegisterClass *DefRC,
353                                   unsigned DefSubReg,
354                                   const TargetRegisterClass *SrcRC,
355                                   unsigned SrcSubReg) {
356   // Same register class.
357   if (DefRC == SrcRC)
358     return true;
359 
360   // Both operands are sub registers. Check if they share a register class.
361   unsigned SrcIdx, DefIdx;
362   if (SrcSubReg && DefSubReg) {
363     return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
364                                       SrcIdx, DefIdx) != nullptr;
365   }
366 
367   // At most one of the register is a sub register, make it Src to avoid
368   // duplicating the test.
369   if (!SrcSubReg) {
370     std::swap(DefSubReg, SrcSubReg);
371     std::swap(DefRC, SrcRC);
372   }
373 
374   // One of the register is a sub register, check if we can get a superclass.
375   if (SrcSubReg)
376     return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
377 
378   // Plain copy.
379   return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
380 }
381 
382 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
383                                               unsigned DefSubReg,
384                                               const TargetRegisterClass *SrcRC,
385                                               unsigned SrcSubReg) const {
386   // If this source does not incur a cross register bank copy, use it.
387   return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
388 }
389 
390 // Compute target-independent register allocator hints to help eliminate copies.
391 bool
392 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
393                                           ArrayRef<MCPhysReg> Order,
394                                           SmallVectorImpl<MCPhysReg> &Hints,
395                                           const MachineFunction &MF,
396                                           const VirtRegMap *VRM,
397                                           const LiveRegMatrix *Matrix) const {
398   const MachineRegisterInfo &MRI = MF.getRegInfo();
399   const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
400     MRI.getRegAllocationHints(VirtReg);
401 
402   SmallSet<unsigned, 32> HintedRegs;
403   // First hint may be a target hint.
404   bool Skip = (Hints_MRI.first != 0);
405   for (auto Reg : Hints_MRI.second) {
406     if (Skip) {
407       Skip = false;
408       continue;
409     }
410 
411     // Target-independent hints are either a physical or a virtual register.
412     unsigned Phys = Reg;
413     if (VRM && isVirtualRegister(Phys))
414       Phys = VRM->getPhys(Phys);
415 
416     // Don't add the same reg twice (Hints_MRI may contain multiple virtual
417     // registers allocated to the same physreg).
418     if (!HintedRegs.insert(Phys).second)
419       continue;
420     // Check that Phys is a valid hint in VirtReg's register class.
421     if (!isPhysicalRegister(Phys))
422       continue;
423     if (MRI.isReserved(Phys))
424       continue;
425     // Check that Phys is in the allocation order. We shouldn't heed hints
426     // from VirtReg's register class if they aren't in the allocation order. The
427     // target probably has a reason for removing the register.
428     if (!is_contained(Order, Phys))
429       continue;
430 
431     // All clear, tell the register allocator to prefer this register.
432     Hints.push_back(Phys);
433   }
434   return false;
435 }
436 
437 bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
438   return !MF.getFunction().hasFnAttribute("no-realign-stack");
439 }
440 
441 bool TargetRegisterInfo::needsStackRealignment(
442     const MachineFunction &MF) const {
443   const MachineFrameInfo &MFI = MF.getFrameInfo();
444   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
445   const Function &F = MF.getFunction();
446   unsigned StackAlign = TFI->getStackAlignment();
447   bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
448                               F.hasFnAttribute(Attribute::StackAlignment));
449   if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
450     if (canRealignStack(MF))
451       return true;
452     LLVM_DEBUG(dbgs() << "Can't realign function's stack: " << F.getName()
453                       << "\n");
454   }
455   return false;
456 }
457 
458 bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0,
459                                             const uint32_t *mask1) const {
460   unsigned N = (getNumRegs()+31) / 32;
461   for (unsigned I = 0; I < N; ++I)
462     if ((mask0[I] & mask1[I]) != mask0[I])
463       return false;
464   return true;
465 }
466 
467 unsigned TargetRegisterInfo::getRegSizeInBits(unsigned Reg,
468                                          const MachineRegisterInfo &MRI) const {
469   const TargetRegisterClass *RC{};
470   if (isPhysicalRegister(Reg)) {
471     // The size is not directly available for physical registers.
472     // Instead, we need to access a register class that contains Reg and
473     // get the size of that register class.
474     RC = getMinimalPhysRegClass(Reg);
475   } else {
476     LLT Ty = MRI.getType(Reg);
477     unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
478     // If Reg is not a generic register, query the register class to
479     // get its size.
480     if (RegSize)
481       return RegSize;
482     // Since Reg is not a generic register, it must have a register class.
483     RC = MRI.getRegClass(Reg);
484   }
485   assert(RC && "Unable to deduce the register class");
486   return getRegSizeInBits(*RC);
487 }
488 
489 unsigned
490 TargetRegisterInfo::lookThruCopyLike(unsigned SrcReg,
491                                      const MachineRegisterInfo *MRI) const {
492   while (true) {
493     const MachineInstr *MI = MRI->getVRegDef(SrcReg);
494     if (!MI->isCopyLike())
495       return SrcReg;
496 
497     unsigned CopySrcReg;
498     if (MI->isCopy())
499       CopySrcReg = MI->getOperand(1).getReg();
500     else {
501       assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
502       CopySrcReg = MI->getOperand(2).getReg();
503     }
504 
505     if (!isVirtualRegister(CopySrcReg))
506       return CopySrcReg;
507 
508     SrcReg = CopySrcReg;
509   }
510 }
511 
512 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
513 LLVM_DUMP_METHOD
514 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
515                                  const TargetRegisterInfo *TRI) {
516   dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
517 }
518 #endif
519