1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/CodeGen/Analysis.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineJumpTableInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/StackMaps.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/IR/DerivedTypes.h" 28 #include "llvm/IR/GlobalVariable.h" 29 #include "llvm/IR/Mangler.h" 30 #include "llvm/MC/MCAsmInfo.h" 31 #include "llvm/MC/MCContext.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/Support/BranchProbability.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/Target/TargetLoweringObjectFile.h" 38 #include "llvm/Target/TargetMachine.h" 39 #include "llvm/Target/TargetRegisterInfo.h" 40 #include "llvm/Target/TargetSubtargetInfo.h" 41 #include <cctype> 42 using namespace llvm; 43 44 static cl::opt<bool> JumpIsExpensiveOverride( 45 "jump-is-expensive", cl::init(false), 46 cl::desc("Do not create extra branches to split comparison logic."), 47 cl::Hidden); 48 49 static cl::opt<unsigned> MinimumJumpTableEntries 50 ("min-jump-table-entries", cl::init(4), cl::Hidden, 51 cl::desc("Set minimum number of entries to use a jump table.")); 52 53 static cl::opt<unsigned> MaximumJumpTableSize 54 ("max-jump-table-size", cl::init(0), cl::Hidden, 55 cl::desc("Set maximum size of jump tables; zero for no limit.")); 56 57 /// Minimum jump table density for normal functions. 58 static cl::opt<unsigned> 59 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, 60 cl::desc("Minimum density for building a jump table in " 61 "a normal function")); 62 63 /// Minimum jump table density for -Os or -Oz functions. 64 static cl::opt<unsigned> OptsizeJumpTableDensity( 65 "optsize-jump-table-density", cl::init(40), cl::Hidden, 66 cl::desc("Minimum density for building a jump table in " 67 "an optsize function")); 68 69 // Although this default value is arbitrary, it is not random. It is assumed 70 // that a condition that evaluates the same way by a higher percentage than this 71 // is best represented as control flow. Therefore, the default value N should be 72 // set such that the win from N% correct executions is greater than the loss 73 // from (100 - N)% mispredicted executions for the majority of intended targets. 74 static cl::opt<int> MinPercentageForPredictableBranch( 75 "min-predictable-branch", cl::init(99), 76 cl::desc("Minimum percentage (0-100) that a condition must be either true " 77 "or false to assume that the condition is predictable"), 78 cl::Hidden); 79 80 /// InitLibcallNames - Set default libcall names. 81 /// 82 static void InitLibcallNames(const char **Names, const Triple &TT) { 83 Names[RTLIB::SHL_I16] = "__ashlhi3"; 84 Names[RTLIB::SHL_I32] = "__ashlsi3"; 85 Names[RTLIB::SHL_I64] = "__ashldi3"; 86 Names[RTLIB::SHL_I128] = "__ashlti3"; 87 Names[RTLIB::SRL_I16] = "__lshrhi3"; 88 Names[RTLIB::SRL_I32] = "__lshrsi3"; 89 Names[RTLIB::SRL_I64] = "__lshrdi3"; 90 Names[RTLIB::SRL_I128] = "__lshrti3"; 91 Names[RTLIB::SRA_I16] = "__ashrhi3"; 92 Names[RTLIB::SRA_I32] = "__ashrsi3"; 93 Names[RTLIB::SRA_I64] = "__ashrdi3"; 94 Names[RTLIB::SRA_I128] = "__ashrti3"; 95 Names[RTLIB::MUL_I8] = "__mulqi3"; 96 Names[RTLIB::MUL_I16] = "__mulhi3"; 97 Names[RTLIB::MUL_I32] = "__mulsi3"; 98 Names[RTLIB::MUL_I64] = "__muldi3"; 99 Names[RTLIB::MUL_I128] = "__multi3"; 100 Names[RTLIB::MULO_I32] = "__mulosi4"; 101 Names[RTLIB::MULO_I64] = "__mulodi4"; 102 Names[RTLIB::MULO_I128] = "__muloti4"; 103 Names[RTLIB::SDIV_I8] = "__divqi3"; 104 Names[RTLIB::SDIV_I16] = "__divhi3"; 105 Names[RTLIB::SDIV_I32] = "__divsi3"; 106 Names[RTLIB::SDIV_I64] = "__divdi3"; 107 Names[RTLIB::SDIV_I128] = "__divti3"; 108 Names[RTLIB::UDIV_I8] = "__udivqi3"; 109 Names[RTLIB::UDIV_I16] = "__udivhi3"; 110 Names[RTLIB::UDIV_I32] = "__udivsi3"; 111 Names[RTLIB::UDIV_I64] = "__udivdi3"; 112 Names[RTLIB::UDIV_I128] = "__udivti3"; 113 Names[RTLIB::SREM_I8] = "__modqi3"; 114 Names[RTLIB::SREM_I16] = "__modhi3"; 115 Names[RTLIB::SREM_I32] = "__modsi3"; 116 Names[RTLIB::SREM_I64] = "__moddi3"; 117 Names[RTLIB::SREM_I128] = "__modti3"; 118 Names[RTLIB::UREM_I8] = "__umodqi3"; 119 Names[RTLIB::UREM_I16] = "__umodhi3"; 120 Names[RTLIB::UREM_I32] = "__umodsi3"; 121 Names[RTLIB::UREM_I64] = "__umoddi3"; 122 Names[RTLIB::UREM_I128] = "__umodti3"; 123 124 Names[RTLIB::NEG_I32] = "__negsi2"; 125 Names[RTLIB::NEG_I64] = "__negdi2"; 126 Names[RTLIB::ADD_F32] = "__addsf3"; 127 Names[RTLIB::ADD_F64] = "__adddf3"; 128 Names[RTLIB::ADD_F80] = "__addxf3"; 129 Names[RTLIB::ADD_F128] = "__addtf3"; 130 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 131 Names[RTLIB::SUB_F32] = "__subsf3"; 132 Names[RTLIB::SUB_F64] = "__subdf3"; 133 Names[RTLIB::SUB_F80] = "__subxf3"; 134 Names[RTLIB::SUB_F128] = "__subtf3"; 135 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 136 Names[RTLIB::MUL_F32] = "__mulsf3"; 137 Names[RTLIB::MUL_F64] = "__muldf3"; 138 Names[RTLIB::MUL_F80] = "__mulxf3"; 139 Names[RTLIB::MUL_F128] = "__multf3"; 140 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 141 Names[RTLIB::DIV_F32] = "__divsf3"; 142 Names[RTLIB::DIV_F64] = "__divdf3"; 143 Names[RTLIB::DIV_F80] = "__divxf3"; 144 Names[RTLIB::DIV_F128] = "__divtf3"; 145 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 146 Names[RTLIB::REM_F32] = "fmodf"; 147 Names[RTLIB::REM_F64] = "fmod"; 148 Names[RTLIB::REM_F80] = "fmodl"; 149 Names[RTLIB::REM_F128] = "fmodl"; 150 Names[RTLIB::REM_PPCF128] = "fmodl"; 151 Names[RTLIB::FMA_F32] = "fmaf"; 152 Names[RTLIB::FMA_F64] = "fma"; 153 Names[RTLIB::FMA_F80] = "fmal"; 154 Names[RTLIB::FMA_F128] = "fmal"; 155 Names[RTLIB::FMA_PPCF128] = "fmal"; 156 Names[RTLIB::POWI_F32] = "__powisf2"; 157 Names[RTLIB::POWI_F64] = "__powidf2"; 158 Names[RTLIB::POWI_F80] = "__powixf2"; 159 Names[RTLIB::POWI_F128] = "__powitf2"; 160 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 161 Names[RTLIB::SQRT_F32] = "sqrtf"; 162 Names[RTLIB::SQRT_F64] = "sqrt"; 163 Names[RTLIB::SQRT_F80] = "sqrtl"; 164 Names[RTLIB::SQRT_F128] = "sqrtl"; 165 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 166 Names[RTLIB::LOG_F32] = "logf"; 167 Names[RTLIB::LOG_F64] = "log"; 168 Names[RTLIB::LOG_F80] = "logl"; 169 Names[RTLIB::LOG_F128] = "logl"; 170 Names[RTLIB::LOG_PPCF128] = "logl"; 171 Names[RTLIB::LOG2_F32] = "log2f"; 172 Names[RTLIB::LOG2_F64] = "log2"; 173 Names[RTLIB::LOG2_F80] = "log2l"; 174 Names[RTLIB::LOG2_F128] = "log2l"; 175 Names[RTLIB::LOG2_PPCF128] = "log2l"; 176 Names[RTLIB::LOG10_F32] = "log10f"; 177 Names[RTLIB::LOG10_F64] = "log10"; 178 Names[RTLIB::LOG10_F80] = "log10l"; 179 Names[RTLIB::LOG10_F128] = "log10l"; 180 Names[RTLIB::LOG10_PPCF128] = "log10l"; 181 Names[RTLIB::EXP_F32] = "expf"; 182 Names[RTLIB::EXP_F64] = "exp"; 183 Names[RTLIB::EXP_F80] = "expl"; 184 Names[RTLIB::EXP_F128] = "expl"; 185 Names[RTLIB::EXP_PPCF128] = "expl"; 186 Names[RTLIB::EXP2_F32] = "exp2f"; 187 Names[RTLIB::EXP2_F64] = "exp2"; 188 Names[RTLIB::EXP2_F80] = "exp2l"; 189 Names[RTLIB::EXP2_F128] = "exp2l"; 190 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 191 Names[RTLIB::SIN_F32] = "sinf"; 192 Names[RTLIB::SIN_F64] = "sin"; 193 Names[RTLIB::SIN_F80] = "sinl"; 194 Names[RTLIB::SIN_F128] = "sinl"; 195 Names[RTLIB::SIN_PPCF128] = "sinl"; 196 Names[RTLIB::COS_F32] = "cosf"; 197 Names[RTLIB::COS_F64] = "cos"; 198 Names[RTLIB::COS_F80] = "cosl"; 199 Names[RTLIB::COS_F128] = "cosl"; 200 Names[RTLIB::COS_PPCF128] = "cosl"; 201 Names[RTLIB::POW_F32] = "powf"; 202 Names[RTLIB::POW_F64] = "pow"; 203 Names[RTLIB::POW_F80] = "powl"; 204 Names[RTLIB::POW_F128] = "powl"; 205 Names[RTLIB::POW_PPCF128] = "powl"; 206 Names[RTLIB::CEIL_F32] = "ceilf"; 207 Names[RTLIB::CEIL_F64] = "ceil"; 208 Names[RTLIB::CEIL_F80] = "ceill"; 209 Names[RTLIB::CEIL_F128] = "ceill"; 210 Names[RTLIB::CEIL_PPCF128] = "ceill"; 211 Names[RTLIB::TRUNC_F32] = "truncf"; 212 Names[RTLIB::TRUNC_F64] = "trunc"; 213 Names[RTLIB::TRUNC_F80] = "truncl"; 214 Names[RTLIB::TRUNC_F128] = "truncl"; 215 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 216 Names[RTLIB::RINT_F32] = "rintf"; 217 Names[RTLIB::RINT_F64] = "rint"; 218 Names[RTLIB::RINT_F80] = "rintl"; 219 Names[RTLIB::RINT_F128] = "rintl"; 220 Names[RTLIB::RINT_PPCF128] = "rintl"; 221 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 222 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 223 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 224 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 225 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 226 Names[RTLIB::ROUND_F32] = "roundf"; 227 Names[RTLIB::ROUND_F64] = "round"; 228 Names[RTLIB::ROUND_F80] = "roundl"; 229 Names[RTLIB::ROUND_F128] = "roundl"; 230 Names[RTLIB::ROUND_PPCF128] = "roundl"; 231 Names[RTLIB::FLOOR_F32] = "floorf"; 232 Names[RTLIB::FLOOR_F64] = "floor"; 233 Names[RTLIB::FLOOR_F80] = "floorl"; 234 Names[RTLIB::FLOOR_F128] = "floorl"; 235 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 236 Names[RTLIB::FMIN_F32] = "fminf"; 237 Names[RTLIB::FMIN_F64] = "fmin"; 238 Names[RTLIB::FMIN_F80] = "fminl"; 239 Names[RTLIB::FMIN_F128] = "fminl"; 240 Names[RTLIB::FMIN_PPCF128] = "fminl"; 241 Names[RTLIB::FMAX_F32] = "fmaxf"; 242 Names[RTLIB::FMAX_F64] = "fmax"; 243 Names[RTLIB::FMAX_F80] = "fmaxl"; 244 Names[RTLIB::FMAX_F128] = "fmaxl"; 245 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 246 Names[RTLIB::ROUND_F32] = "roundf"; 247 Names[RTLIB::ROUND_F64] = "round"; 248 Names[RTLIB::ROUND_F80] = "roundl"; 249 Names[RTLIB::ROUND_F128] = "roundl"; 250 Names[RTLIB::ROUND_PPCF128] = "roundl"; 251 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 252 Names[RTLIB::COPYSIGN_F64] = "copysign"; 253 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 254 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 255 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 256 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq"; 257 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq"; 258 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 259 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 260 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 261 if (TT.isOSDarwin()) { 262 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 263 // of the gnueabi-style __gnu_*_ieee. 264 // FIXME: What about other targets? 265 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2"; 266 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2"; 267 } else { 268 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 269 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 270 } 271 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 272 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 273 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 274 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 275 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 276 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 277 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 278 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos"; 279 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 280 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 281 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod"; 282 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 283 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 284 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 285 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 286 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 287 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 288 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 289 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 290 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 291 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 292 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 293 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 294 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou"; 295 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 296 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 297 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 298 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 299 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 300 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 301 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 302 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 303 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 304 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 305 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 306 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 307 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 308 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 309 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 310 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 311 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 312 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 313 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 314 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 315 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 316 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq"; 317 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 318 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 319 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 320 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 321 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 322 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 323 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 324 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 325 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 326 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 327 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 328 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 329 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 330 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 331 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq"; 332 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 333 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 334 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 335 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 336 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 337 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 338 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 339 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 340 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 341 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 342 Names[RTLIB::OEQ_F32] = "__eqsf2"; 343 Names[RTLIB::OEQ_F64] = "__eqdf2"; 344 Names[RTLIB::OEQ_F128] = "__eqtf2"; 345 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq"; 346 Names[RTLIB::UNE_F32] = "__nesf2"; 347 Names[RTLIB::UNE_F64] = "__nedf2"; 348 Names[RTLIB::UNE_F128] = "__netf2"; 349 Names[RTLIB::UNE_PPCF128] = "__gcc_qne"; 350 Names[RTLIB::OGE_F32] = "__gesf2"; 351 Names[RTLIB::OGE_F64] = "__gedf2"; 352 Names[RTLIB::OGE_F128] = "__getf2"; 353 Names[RTLIB::OGE_PPCF128] = "__gcc_qge"; 354 Names[RTLIB::OLT_F32] = "__ltsf2"; 355 Names[RTLIB::OLT_F64] = "__ltdf2"; 356 Names[RTLIB::OLT_F128] = "__lttf2"; 357 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt"; 358 Names[RTLIB::OLE_F32] = "__lesf2"; 359 Names[RTLIB::OLE_F64] = "__ledf2"; 360 Names[RTLIB::OLE_F128] = "__letf2"; 361 Names[RTLIB::OLE_PPCF128] = "__gcc_qle"; 362 Names[RTLIB::OGT_F32] = "__gtsf2"; 363 Names[RTLIB::OGT_F64] = "__gtdf2"; 364 Names[RTLIB::OGT_F128] = "__gttf2"; 365 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt"; 366 Names[RTLIB::UO_F32] = "__unordsf2"; 367 Names[RTLIB::UO_F64] = "__unorddf2"; 368 Names[RTLIB::UO_F128] = "__unordtf2"; 369 Names[RTLIB::UO_PPCF128] = "__gcc_qunord"; 370 Names[RTLIB::O_F32] = "__unordsf2"; 371 Names[RTLIB::O_F64] = "__unorddf2"; 372 Names[RTLIB::O_F128] = "__unordtf2"; 373 Names[RTLIB::O_PPCF128] = "__gcc_qunord"; 374 Names[RTLIB::MEMCPY] = "memcpy"; 375 Names[RTLIB::MEMMOVE] = "memmove"; 376 Names[RTLIB::MEMSET] = "memset"; 377 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_1] = "__llvm_memcpy_element_atomic_1"; 378 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_2] = "__llvm_memcpy_element_atomic_2"; 379 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_4] = "__llvm_memcpy_element_atomic_4"; 380 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_8] = "__llvm_memcpy_element_atomic_8"; 381 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_16] = "__llvm_memcpy_element_atomic_16"; 382 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 383 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 384 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 385 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 386 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 387 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 388 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 389 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 390 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 391 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 392 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 393 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 394 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 395 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 396 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 397 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 398 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 399 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 400 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 401 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 402 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 403 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 404 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 405 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 406 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 407 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 408 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 409 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 410 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 411 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 412 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 413 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 414 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 415 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 416 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 417 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 418 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 419 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 420 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 421 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 422 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 423 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 424 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 425 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 426 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 427 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 428 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 429 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 430 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 431 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 432 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 433 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 434 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 435 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 436 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 437 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 438 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 439 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 440 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 441 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 442 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 443 444 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load"; 445 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1"; 446 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2"; 447 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4"; 448 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8"; 449 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16"; 450 451 Names[RTLIB::ATOMIC_STORE] = "__atomic_store"; 452 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1"; 453 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2"; 454 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4"; 455 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8"; 456 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16"; 457 458 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange"; 459 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1"; 460 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2"; 461 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4"; 462 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8"; 463 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16"; 464 465 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange"; 466 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1"; 467 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2"; 468 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4"; 469 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8"; 470 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16"; 471 472 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1"; 473 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2"; 474 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4"; 475 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8"; 476 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16"; 477 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1"; 478 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2"; 479 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4"; 480 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8"; 481 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16"; 482 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1"; 483 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2"; 484 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4"; 485 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8"; 486 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16"; 487 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1"; 488 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2"; 489 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4"; 490 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8"; 491 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16"; 492 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1"; 493 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2"; 494 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4"; 495 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8"; 496 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16"; 497 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1"; 498 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2"; 499 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4"; 500 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8"; 501 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16"; 502 503 if (TT.isGNUEnvironment()) { 504 Names[RTLIB::SINCOS_F32] = "sincosf"; 505 Names[RTLIB::SINCOS_F64] = "sincos"; 506 Names[RTLIB::SINCOS_F80] = "sincosl"; 507 Names[RTLIB::SINCOS_F128] = "sincosl"; 508 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 509 } 510 511 if (!TT.isOSOpenBSD()) { 512 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 513 } 514 515 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize"; 516 } 517 518 /// Set default libcall CallingConvs. 519 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 520 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 521 CCs[LC] = CallingConv::C; 522 } 523 524 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 525 /// UNKNOWN_LIBCALL if there is none. 526 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 527 if (OpVT == MVT::f16) { 528 if (RetVT == MVT::f32) 529 return FPEXT_F16_F32; 530 } else if (OpVT == MVT::f32) { 531 if (RetVT == MVT::f64) 532 return FPEXT_F32_F64; 533 if (RetVT == MVT::f128) 534 return FPEXT_F32_F128; 535 if (RetVT == MVT::ppcf128) 536 return FPEXT_F32_PPCF128; 537 } else if (OpVT == MVT::f64) { 538 if (RetVT == MVT::f128) 539 return FPEXT_F64_F128; 540 else if (RetVT == MVT::ppcf128) 541 return FPEXT_F64_PPCF128; 542 } 543 544 return UNKNOWN_LIBCALL; 545 } 546 547 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 548 /// UNKNOWN_LIBCALL if there is none. 549 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 550 if (RetVT == MVT::f16) { 551 if (OpVT == MVT::f32) 552 return FPROUND_F32_F16; 553 if (OpVT == MVT::f64) 554 return FPROUND_F64_F16; 555 if (OpVT == MVT::f80) 556 return FPROUND_F80_F16; 557 if (OpVT == MVT::f128) 558 return FPROUND_F128_F16; 559 if (OpVT == MVT::ppcf128) 560 return FPROUND_PPCF128_F16; 561 } else if (RetVT == MVT::f32) { 562 if (OpVT == MVT::f64) 563 return FPROUND_F64_F32; 564 if (OpVT == MVT::f80) 565 return FPROUND_F80_F32; 566 if (OpVT == MVT::f128) 567 return FPROUND_F128_F32; 568 if (OpVT == MVT::ppcf128) 569 return FPROUND_PPCF128_F32; 570 } else if (RetVT == MVT::f64) { 571 if (OpVT == MVT::f80) 572 return FPROUND_F80_F64; 573 if (OpVT == MVT::f128) 574 return FPROUND_F128_F64; 575 if (OpVT == MVT::ppcf128) 576 return FPROUND_PPCF128_F64; 577 } 578 579 return UNKNOWN_LIBCALL; 580 } 581 582 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 583 /// UNKNOWN_LIBCALL if there is none. 584 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 585 if (OpVT == MVT::f32) { 586 if (RetVT == MVT::i32) 587 return FPTOSINT_F32_I32; 588 if (RetVT == MVT::i64) 589 return FPTOSINT_F32_I64; 590 if (RetVT == MVT::i128) 591 return FPTOSINT_F32_I128; 592 } else if (OpVT == MVT::f64) { 593 if (RetVT == MVT::i32) 594 return FPTOSINT_F64_I32; 595 if (RetVT == MVT::i64) 596 return FPTOSINT_F64_I64; 597 if (RetVT == MVT::i128) 598 return FPTOSINT_F64_I128; 599 } else if (OpVT == MVT::f80) { 600 if (RetVT == MVT::i32) 601 return FPTOSINT_F80_I32; 602 if (RetVT == MVT::i64) 603 return FPTOSINT_F80_I64; 604 if (RetVT == MVT::i128) 605 return FPTOSINT_F80_I128; 606 } else if (OpVT == MVT::f128) { 607 if (RetVT == MVT::i32) 608 return FPTOSINT_F128_I32; 609 if (RetVT == MVT::i64) 610 return FPTOSINT_F128_I64; 611 if (RetVT == MVT::i128) 612 return FPTOSINT_F128_I128; 613 } else if (OpVT == MVT::ppcf128) { 614 if (RetVT == MVT::i32) 615 return FPTOSINT_PPCF128_I32; 616 if (RetVT == MVT::i64) 617 return FPTOSINT_PPCF128_I64; 618 if (RetVT == MVT::i128) 619 return FPTOSINT_PPCF128_I128; 620 } 621 return UNKNOWN_LIBCALL; 622 } 623 624 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 625 /// UNKNOWN_LIBCALL if there is none. 626 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 627 if (OpVT == MVT::f32) { 628 if (RetVT == MVT::i32) 629 return FPTOUINT_F32_I32; 630 if (RetVT == MVT::i64) 631 return FPTOUINT_F32_I64; 632 if (RetVT == MVT::i128) 633 return FPTOUINT_F32_I128; 634 } else if (OpVT == MVT::f64) { 635 if (RetVT == MVT::i32) 636 return FPTOUINT_F64_I32; 637 if (RetVT == MVT::i64) 638 return FPTOUINT_F64_I64; 639 if (RetVT == MVT::i128) 640 return FPTOUINT_F64_I128; 641 } else if (OpVT == MVT::f80) { 642 if (RetVT == MVT::i32) 643 return FPTOUINT_F80_I32; 644 if (RetVT == MVT::i64) 645 return FPTOUINT_F80_I64; 646 if (RetVT == MVT::i128) 647 return FPTOUINT_F80_I128; 648 } else if (OpVT == MVT::f128) { 649 if (RetVT == MVT::i32) 650 return FPTOUINT_F128_I32; 651 if (RetVT == MVT::i64) 652 return FPTOUINT_F128_I64; 653 if (RetVT == MVT::i128) 654 return FPTOUINT_F128_I128; 655 } else if (OpVT == MVT::ppcf128) { 656 if (RetVT == MVT::i32) 657 return FPTOUINT_PPCF128_I32; 658 if (RetVT == MVT::i64) 659 return FPTOUINT_PPCF128_I64; 660 if (RetVT == MVT::i128) 661 return FPTOUINT_PPCF128_I128; 662 } 663 return UNKNOWN_LIBCALL; 664 } 665 666 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 667 /// UNKNOWN_LIBCALL if there is none. 668 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 669 if (OpVT == MVT::i32) { 670 if (RetVT == MVT::f32) 671 return SINTTOFP_I32_F32; 672 if (RetVT == MVT::f64) 673 return SINTTOFP_I32_F64; 674 if (RetVT == MVT::f80) 675 return SINTTOFP_I32_F80; 676 if (RetVT == MVT::f128) 677 return SINTTOFP_I32_F128; 678 if (RetVT == MVT::ppcf128) 679 return SINTTOFP_I32_PPCF128; 680 } else if (OpVT == MVT::i64) { 681 if (RetVT == MVT::f32) 682 return SINTTOFP_I64_F32; 683 if (RetVT == MVT::f64) 684 return SINTTOFP_I64_F64; 685 if (RetVT == MVT::f80) 686 return SINTTOFP_I64_F80; 687 if (RetVT == MVT::f128) 688 return SINTTOFP_I64_F128; 689 if (RetVT == MVT::ppcf128) 690 return SINTTOFP_I64_PPCF128; 691 } else if (OpVT == MVT::i128) { 692 if (RetVT == MVT::f32) 693 return SINTTOFP_I128_F32; 694 if (RetVT == MVT::f64) 695 return SINTTOFP_I128_F64; 696 if (RetVT == MVT::f80) 697 return SINTTOFP_I128_F80; 698 if (RetVT == MVT::f128) 699 return SINTTOFP_I128_F128; 700 if (RetVT == MVT::ppcf128) 701 return SINTTOFP_I128_PPCF128; 702 } 703 return UNKNOWN_LIBCALL; 704 } 705 706 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 707 /// UNKNOWN_LIBCALL if there is none. 708 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 709 if (OpVT == MVT::i32) { 710 if (RetVT == MVT::f32) 711 return UINTTOFP_I32_F32; 712 if (RetVT == MVT::f64) 713 return UINTTOFP_I32_F64; 714 if (RetVT == MVT::f80) 715 return UINTTOFP_I32_F80; 716 if (RetVT == MVT::f128) 717 return UINTTOFP_I32_F128; 718 if (RetVT == MVT::ppcf128) 719 return UINTTOFP_I32_PPCF128; 720 } else if (OpVT == MVT::i64) { 721 if (RetVT == MVT::f32) 722 return UINTTOFP_I64_F32; 723 if (RetVT == MVT::f64) 724 return UINTTOFP_I64_F64; 725 if (RetVT == MVT::f80) 726 return UINTTOFP_I64_F80; 727 if (RetVT == MVT::f128) 728 return UINTTOFP_I64_F128; 729 if (RetVT == MVT::ppcf128) 730 return UINTTOFP_I64_PPCF128; 731 } else if (OpVT == MVT::i128) { 732 if (RetVT == MVT::f32) 733 return UINTTOFP_I128_F32; 734 if (RetVT == MVT::f64) 735 return UINTTOFP_I128_F64; 736 if (RetVT == MVT::f80) 737 return UINTTOFP_I128_F80; 738 if (RetVT == MVT::f128) 739 return UINTTOFP_I128_F128; 740 if (RetVT == MVT::ppcf128) 741 return UINTTOFP_I128_PPCF128; 742 } 743 return UNKNOWN_LIBCALL; 744 } 745 746 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 747 #define OP_TO_LIBCALL(Name, Enum) \ 748 case Name: \ 749 switch (VT.SimpleTy) { \ 750 default: \ 751 return UNKNOWN_LIBCALL; \ 752 case MVT::i8: \ 753 return Enum##_1; \ 754 case MVT::i16: \ 755 return Enum##_2; \ 756 case MVT::i32: \ 757 return Enum##_4; \ 758 case MVT::i64: \ 759 return Enum##_8; \ 760 case MVT::i128: \ 761 return Enum##_16; \ 762 } 763 764 switch (Opc) { 765 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 766 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 767 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 768 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 769 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 770 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 771 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 772 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 773 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 774 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 775 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 776 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 777 } 778 779 #undef OP_TO_LIBCALL 780 781 return UNKNOWN_LIBCALL; 782 } 783 784 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_ATOMIC(uint64_t ElementSize) { 785 switch (ElementSize) { 786 case 1: 787 return MEMCPY_ELEMENT_ATOMIC_1; 788 case 2: 789 return MEMCPY_ELEMENT_ATOMIC_2; 790 case 4: 791 return MEMCPY_ELEMENT_ATOMIC_4; 792 case 8: 793 return MEMCPY_ELEMENT_ATOMIC_8; 794 case 16: 795 return MEMCPY_ELEMENT_ATOMIC_16; 796 default: 797 return UNKNOWN_LIBCALL; 798 } 799 800 } 801 802 /// InitCmpLibcallCCs - Set default comparison libcall CC. 803 /// 804 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 805 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 806 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 807 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 808 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 809 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 810 CCs[RTLIB::UNE_F32] = ISD::SETNE; 811 CCs[RTLIB::UNE_F64] = ISD::SETNE; 812 CCs[RTLIB::UNE_F128] = ISD::SETNE; 813 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 814 CCs[RTLIB::OGE_F32] = ISD::SETGE; 815 CCs[RTLIB::OGE_F64] = ISD::SETGE; 816 CCs[RTLIB::OGE_F128] = ISD::SETGE; 817 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 818 CCs[RTLIB::OLT_F32] = ISD::SETLT; 819 CCs[RTLIB::OLT_F64] = ISD::SETLT; 820 CCs[RTLIB::OLT_F128] = ISD::SETLT; 821 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 822 CCs[RTLIB::OLE_F32] = ISD::SETLE; 823 CCs[RTLIB::OLE_F64] = ISD::SETLE; 824 CCs[RTLIB::OLE_F128] = ISD::SETLE; 825 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 826 CCs[RTLIB::OGT_F32] = ISD::SETGT; 827 CCs[RTLIB::OGT_F64] = ISD::SETGT; 828 CCs[RTLIB::OGT_F128] = ISD::SETGT; 829 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 830 CCs[RTLIB::UO_F32] = ISD::SETNE; 831 CCs[RTLIB::UO_F64] = ISD::SETNE; 832 CCs[RTLIB::UO_F128] = ISD::SETNE; 833 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 834 CCs[RTLIB::O_F32] = ISD::SETEQ; 835 CCs[RTLIB::O_F64] = ISD::SETEQ; 836 CCs[RTLIB::O_F128] = ISD::SETEQ; 837 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; 838 } 839 840 /// NOTE: The TargetMachine owns TLOF. 841 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 842 initActions(); 843 844 // Perform these initializations only once. 845 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 846 MaxLoadsPerMemcmp = 8; 847 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize = 848 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4; 849 UseUnderscoreSetJmp = false; 850 UseUnderscoreLongJmp = false; 851 HasMultipleConditionRegisters = false; 852 HasExtractBitsInsn = false; 853 JumpIsExpensive = JumpIsExpensiveOverride; 854 PredictableSelectIsExpensive = false; 855 EnableExtLdPromotion = false; 856 HasFloatingPointExceptions = true; 857 StackPointerRegisterToSaveRestore = 0; 858 BooleanContents = UndefinedBooleanContent; 859 BooleanFloatContents = UndefinedBooleanContent; 860 BooleanVectorContents = UndefinedBooleanContent; 861 SchedPreferenceInfo = Sched::ILP; 862 JumpBufSize = 0; 863 JumpBufAlignment = 0; 864 MinFunctionAlignment = 0; 865 PrefFunctionAlignment = 0; 866 PrefLoopAlignment = 0; 867 GatherAllAliasesMaxDepth = 18; 868 MinStackArgumentAlignment = 1; 869 // TODO: the default will be switched to 0 in the next commit, along 870 // with the Target-specific changes necessary. 871 MaxAtomicSizeInBitsSupported = 1024; 872 873 MinCmpXchgSizeInBits = 0; 874 875 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 876 877 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple()); 878 InitCmpLibcallCCs(CmpLibcallCCs); 879 InitLibcallCallingConvs(LibcallCallingConvs); 880 } 881 882 void TargetLoweringBase::initActions() { 883 // All operations default to being supported. 884 memset(OpActions, 0, sizeof(OpActions)); 885 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 886 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 887 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 888 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 889 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 890 std::fill(std::begin(TargetDAGCombineArray), 891 std::end(TargetDAGCombineArray), 0); 892 893 // Set default actions for various operations. 894 for (MVT VT : MVT::all_valuetypes()) { 895 // Default all indexed load / store to expand. 896 for (unsigned IM = (unsigned)ISD::PRE_INC; 897 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 898 setIndexedLoadAction(IM, VT, Expand); 899 setIndexedStoreAction(IM, VT, Expand); 900 } 901 902 // Most backends expect to see the node which just returns the value loaded. 903 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 904 905 // These operations default to expand. 906 setOperationAction(ISD::FGETSIGN, VT, Expand); 907 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 908 setOperationAction(ISD::FMINNUM, VT, Expand); 909 setOperationAction(ISD::FMAXNUM, VT, Expand); 910 setOperationAction(ISD::FMINNAN, VT, Expand); 911 setOperationAction(ISD::FMAXNAN, VT, Expand); 912 setOperationAction(ISD::FMAD, VT, Expand); 913 setOperationAction(ISD::SMIN, VT, Expand); 914 setOperationAction(ISD::SMAX, VT, Expand); 915 setOperationAction(ISD::UMIN, VT, Expand); 916 setOperationAction(ISD::UMAX, VT, Expand); 917 setOperationAction(ISD::ABS, VT, Expand); 918 919 // Overflow operations default to expand 920 setOperationAction(ISD::SADDO, VT, Expand); 921 setOperationAction(ISD::SSUBO, VT, Expand); 922 setOperationAction(ISD::UADDO, VT, Expand); 923 setOperationAction(ISD::USUBO, VT, Expand); 924 setOperationAction(ISD::SMULO, VT, Expand); 925 setOperationAction(ISD::UMULO, VT, Expand); 926 927 // ADDCARRY operations default to expand 928 setOperationAction(ISD::ADDCARRY, VT, Expand); 929 setOperationAction(ISD::SUBCARRY, VT, Expand); 930 setOperationAction(ISD::SETCCCARRY, VT, Expand); 931 932 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 933 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 934 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 935 936 setOperationAction(ISD::BITREVERSE, VT, Expand); 937 938 // These library functions default to expand. 939 setOperationAction(ISD::FROUND, VT, Expand); 940 setOperationAction(ISD::FPOWI, VT, Expand); 941 942 // These operations default to expand for vector types. 943 if (VT.isVector()) { 944 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 945 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 946 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 947 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 948 } 949 950 // For most targets @llvm.get.dynamic.area.offset just returns 0. 951 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 952 } 953 954 // Most targets ignore the @llvm.prefetch intrinsic. 955 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 956 957 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 958 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 959 960 // ConstantFP nodes default to expand. Targets can either change this to 961 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 962 // to optimize expansions for certain constants. 963 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 964 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 965 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 966 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 967 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 968 969 // These library functions default to expand. 970 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 971 setOperationAction(ISD::FLOG , VT, Expand); 972 setOperationAction(ISD::FLOG2, VT, Expand); 973 setOperationAction(ISD::FLOG10, VT, Expand); 974 setOperationAction(ISD::FEXP , VT, Expand); 975 setOperationAction(ISD::FEXP2, VT, Expand); 976 setOperationAction(ISD::FFLOOR, VT, Expand); 977 setOperationAction(ISD::FNEARBYINT, VT, Expand); 978 setOperationAction(ISD::FCEIL, VT, Expand); 979 setOperationAction(ISD::FRINT, VT, Expand); 980 setOperationAction(ISD::FTRUNC, VT, Expand); 981 setOperationAction(ISD::FROUND, VT, Expand); 982 } 983 984 // Default ISD::TRAP to expand (which turns it into abort). 985 setOperationAction(ISD::TRAP, MVT::Other, Expand); 986 987 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 988 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 989 // 990 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 991 } 992 993 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 994 EVT) const { 995 return MVT::getIntegerVT(8 * DL.getPointerSize(0)); 996 } 997 998 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, 999 const DataLayout &DL) const { 1000 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 1001 if (LHSTy.isVector()) 1002 return LHSTy; 1003 return getScalarShiftAmountTy(DL, LHSTy); 1004 } 1005 1006 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 1007 assert(isTypeLegal(VT)); 1008 switch (Op) { 1009 default: 1010 return false; 1011 case ISD::SDIV: 1012 case ISD::UDIV: 1013 case ISD::SREM: 1014 case ISD::UREM: 1015 return true; 1016 } 1017 } 1018 1019 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 1020 // If the command-line option was specified, ignore this request. 1021 if (!JumpIsExpensiveOverride.getNumOccurrences()) 1022 JumpIsExpensive = isExpensive; 1023 } 1024 1025 TargetLoweringBase::LegalizeKind 1026 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 1027 // If this is a simple type, use the ComputeRegisterProp mechanism. 1028 if (VT.isSimple()) { 1029 MVT SVT = VT.getSimpleVT(); 1030 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 1031 MVT NVT = TransformToType[SVT.SimpleTy]; 1032 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 1033 1034 assert((LA == TypeLegal || LA == TypeSoftenFloat || 1035 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 1036 "Promote may not follow Expand or Promote"); 1037 1038 if (LA == TypeSplitVector) 1039 return LegalizeKind(LA, 1040 EVT::getVectorVT(Context, SVT.getVectorElementType(), 1041 SVT.getVectorNumElements() / 2)); 1042 if (LA == TypeScalarizeVector) 1043 return LegalizeKind(LA, SVT.getVectorElementType()); 1044 return LegalizeKind(LA, NVT); 1045 } 1046 1047 // Handle Extended Scalar Types. 1048 if (!VT.isVector()) { 1049 assert(VT.isInteger() && "Float types must be simple"); 1050 unsigned BitSize = VT.getSizeInBits(); 1051 // First promote to a power-of-two size, then expand if necessary. 1052 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1053 EVT NVT = VT.getRoundIntegerType(Context); 1054 assert(NVT != VT && "Unable to round integer VT"); 1055 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1056 // Avoid multi-step promotion. 1057 if (NextStep.first == TypePromoteInteger) 1058 return NextStep; 1059 // Return rounded integer type. 1060 return LegalizeKind(TypePromoteInteger, NVT); 1061 } 1062 1063 return LegalizeKind(TypeExpandInteger, 1064 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 1065 } 1066 1067 // Handle vector types. 1068 unsigned NumElts = VT.getVectorNumElements(); 1069 EVT EltVT = VT.getVectorElementType(); 1070 1071 // Vectors with only one element are always scalarized. 1072 if (NumElts == 1) 1073 return LegalizeKind(TypeScalarizeVector, EltVT); 1074 1075 // Try to widen vector elements until the element type is a power of two and 1076 // promote it to a legal type later on, for example: 1077 // <3 x i8> -> <4 x i8> -> <4 x i32> 1078 if (EltVT.isInteger()) { 1079 // Vectors with a number of elements that is not a power of two are always 1080 // widened, for example <3 x i8> -> <4 x i8>. 1081 if (!VT.isPow2VectorType()) { 1082 NumElts = (unsigned)NextPowerOf2(NumElts); 1083 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1084 return LegalizeKind(TypeWidenVector, NVT); 1085 } 1086 1087 // Examine the element type. 1088 LegalizeKind LK = getTypeConversion(Context, EltVT); 1089 1090 // If type is to be expanded, split the vector. 1091 // <4 x i140> -> <2 x i140> 1092 if (LK.first == TypeExpandInteger) 1093 return LegalizeKind(TypeSplitVector, 1094 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1095 1096 // Promote the integer element types until a legal vector type is found 1097 // or until the element integer type is too big. If a legal type was not 1098 // found, fallback to the usual mechanism of widening/splitting the 1099 // vector. 1100 EVT OldEltVT = EltVT; 1101 while (1) { 1102 // Increase the bitwidth of the element to the next pow-of-two 1103 // (which is greater than 8 bits). 1104 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 1105 .getRoundIntegerType(Context); 1106 1107 // Stop trying when getting a non-simple element type. 1108 // Note that vector elements may be greater than legal vector element 1109 // types. Example: X86 XMM registers hold 64bit element on 32bit 1110 // systems. 1111 if (!EltVT.isSimple()) 1112 break; 1113 1114 // Build a new vector type and check if it is legal. 1115 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1116 // Found a legal promoted vector type. 1117 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1118 return LegalizeKind(TypePromoteInteger, 1119 EVT::getVectorVT(Context, EltVT, NumElts)); 1120 } 1121 1122 // Reset the type to the unexpanded type if we did not find a legal vector 1123 // type with a promoted vector element type. 1124 EltVT = OldEltVT; 1125 } 1126 1127 // Try to widen the vector until a legal type is found. 1128 // If there is no wider legal type, split the vector. 1129 while (1) { 1130 // Round up to the next power of 2. 1131 NumElts = (unsigned)NextPowerOf2(NumElts); 1132 1133 // If there is no simple vector type with this many elements then there 1134 // cannot be a larger legal vector type. Note that this assumes that 1135 // there are no skipped intermediate vector types in the simple types. 1136 if (!EltVT.isSimple()) 1137 break; 1138 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1139 if (LargerVector == MVT()) 1140 break; 1141 1142 // If this type is legal then widen the vector. 1143 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1144 return LegalizeKind(TypeWidenVector, LargerVector); 1145 } 1146 1147 // Widen odd vectors to next power of two. 1148 if (!VT.isPow2VectorType()) { 1149 EVT NVT = VT.getPow2VectorType(Context); 1150 return LegalizeKind(TypeWidenVector, NVT); 1151 } 1152 1153 // Vectors with illegal element types are expanded. 1154 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1155 return LegalizeKind(TypeSplitVector, NVT); 1156 } 1157 1158 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1159 unsigned &NumIntermediates, 1160 MVT &RegisterVT, 1161 TargetLoweringBase *TLI) { 1162 // Figure out the right, legal destination reg to copy into. 1163 unsigned NumElts = VT.getVectorNumElements(); 1164 MVT EltTy = VT.getVectorElementType(); 1165 1166 unsigned NumVectorRegs = 1; 1167 1168 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1169 // could break down into LHS/RHS like LegalizeDAG does. 1170 if (!isPowerOf2_32(NumElts)) { 1171 NumVectorRegs = NumElts; 1172 NumElts = 1; 1173 } 1174 1175 // Divide the input until we get to a supported size. This will always 1176 // end with a scalar if the target doesn't support vectors. 1177 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1178 NumElts >>= 1; 1179 NumVectorRegs <<= 1; 1180 } 1181 1182 NumIntermediates = NumVectorRegs; 1183 1184 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1185 if (!TLI->isTypeLegal(NewVT)) 1186 NewVT = EltTy; 1187 IntermediateVT = NewVT; 1188 1189 unsigned NewVTSize = NewVT.getSizeInBits(); 1190 1191 // Convert sizes such as i33 to i64. 1192 if (!isPowerOf2_32(NewVTSize)) 1193 NewVTSize = NextPowerOf2(NewVTSize); 1194 1195 MVT DestVT = TLI->getRegisterType(NewVT); 1196 RegisterVT = DestVT; 1197 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1198 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1199 1200 // Otherwise, promotion or legal types use the same number of registers as 1201 // the vector decimated to the appropriate level. 1202 return NumVectorRegs; 1203 } 1204 1205 /// isLegalRC - Return true if the value types that can be represented by the 1206 /// specified register class are all legal. 1207 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI, 1208 const TargetRegisterClass &RC) const { 1209 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I) 1210 if (isTypeLegal(*I)) 1211 return true; 1212 return false; 1213 } 1214 1215 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1216 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1217 MachineBasicBlock * 1218 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1219 MachineBasicBlock *MBB) const { 1220 MachineInstr *MI = &InitialMI; 1221 MachineFunction &MF = *MI->getParent()->getParent(); 1222 MachineFrameInfo &MFI = MF.getFrameInfo(); 1223 1224 // We're handling multiple types of operands here: 1225 // PATCHPOINT MetaArgs - live-in, read only, direct 1226 // STATEPOINT Deopt Spill - live-through, read only, indirect 1227 // STATEPOINT Deopt Alloca - live-through, read only, direct 1228 // (We're currently conservative and mark the deopt slots read/write in 1229 // practice.) 1230 // STATEPOINT GC Spill - live-through, read/write, indirect 1231 // STATEPOINT GC Alloca - live-through, read/write, direct 1232 // The live-in vs live-through is handled already (the live through ones are 1233 // all stack slots), but we need to handle the different type of stackmap 1234 // operands and memory effects here. 1235 1236 // MI changes inside this loop as we grow operands. 1237 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1238 MachineOperand &MO = MI->getOperand(OperIdx); 1239 if (!MO.isFI()) 1240 continue; 1241 1242 // foldMemoryOperand builds a new MI after replacing a single FI operand 1243 // with the canonical set of five x86 addressing-mode operands. 1244 int FI = MO.getIndex(); 1245 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1246 1247 // Copy operands before the frame-index. 1248 for (unsigned i = 0; i < OperIdx; ++i) 1249 MIB.add(MI->getOperand(i)); 1250 // Add frame index operands recognized by stackmaps.cpp 1251 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1252 // indirect-mem-ref tag, size, #FI, offset. 1253 // Used for spills inserted by StatepointLowering. This codepath is not 1254 // used for patchpoints/stackmaps at all, for these spilling is done via 1255 // foldMemoryOperand callback only. 1256 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1257 MIB.addImm(StackMaps::IndirectMemRefOp); 1258 MIB.addImm(MFI.getObjectSize(FI)); 1259 MIB.add(MI->getOperand(OperIdx)); 1260 MIB.addImm(0); 1261 } else { 1262 // direct-mem-ref tag, #FI, offset. 1263 // Used by patchpoint, and direct alloca arguments to statepoints 1264 MIB.addImm(StackMaps::DirectMemRefOp); 1265 MIB.add(MI->getOperand(OperIdx)); 1266 MIB.addImm(0); 1267 } 1268 // Copy the operands after the frame index. 1269 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1270 MIB.add(MI->getOperand(i)); 1271 1272 // Inherit previous memory operands. 1273 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1274 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1275 1276 // Add a new memory operand for this FI. 1277 assert(MFI.getObjectOffset(FI) != -1); 1278 1279 auto Flags = MachineMemOperand::MOLoad; 1280 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1281 Flags |= MachineMemOperand::MOStore; 1282 Flags |= MachineMemOperand::MOVolatile; 1283 } 1284 MachineMemOperand *MMO = MF.getMachineMemOperand( 1285 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1286 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI)); 1287 MIB->addMemOperand(MF, MMO); 1288 1289 // Replace the instruction and update the operand index. 1290 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1291 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1292 MI->eraseFromParent(); 1293 MI = MIB; 1294 } 1295 return MBB; 1296 } 1297 1298 /// findRepresentativeClass - Return the largest legal super-reg register class 1299 /// of the register class for the specified type and its associated "cost". 1300 // This function is in TargetLowering because it uses RegClassForVT which would 1301 // need to be moved to TargetRegisterInfo and would necessitate moving 1302 // isTypeLegal over as well - a massive change that would just require 1303 // TargetLowering having a TargetRegisterInfo class member that it would use. 1304 std::pair<const TargetRegisterClass *, uint8_t> 1305 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1306 MVT VT) const { 1307 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1308 if (!RC) 1309 return std::make_pair(RC, 0); 1310 1311 // Compute the set of all super-register classes. 1312 BitVector SuperRegRC(TRI->getNumRegClasses()); 1313 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1314 SuperRegRC.setBitsInMask(RCI.getMask()); 1315 1316 // Find the first legal register class with the largest spill size. 1317 const TargetRegisterClass *BestRC = RC; 1318 for (unsigned i : SuperRegRC.set_bits()) { 1319 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1320 // We want the largest possible spill size. 1321 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) 1322 continue; 1323 if (!isLegalRC(*TRI, *SuperRC)) 1324 continue; 1325 BestRC = SuperRC; 1326 } 1327 return std::make_pair(BestRC, 1); 1328 } 1329 1330 /// computeRegisterProperties - Once all of the register classes are added, 1331 /// this allows us to compute derived properties we expose. 1332 void TargetLoweringBase::computeRegisterProperties( 1333 const TargetRegisterInfo *TRI) { 1334 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1335 "Too many value types for ValueTypeActions to hold!"); 1336 1337 // Everything defaults to needing one register. 1338 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1339 NumRegistersForVT[i] = 1; 1340 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1341 } 1342 // ...except isVoid, which doesn't need any registers. 1343 NumRegistersForVT[MVT::isVoid] = 0; 1344 1345 // Find the largest integer register class. 1346 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1347 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1348 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1349 1350 // Every integer value type larger than this largest register takes twice as 1351 // many registers to represent as the previous ValueType. 1352 for (unsigned ExpandedReg = LargestIntReg + 1; 1353 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1354 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1355 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1356 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1357 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1358 TypeExpandInteger); 1359 } 1360 1361 // Inspect all of the ValueType's smaller than the largest integer 1362 // register to see which ones need promotion. 1363 unsigned LegalIntReg = LargestIntReg; 1364 for (unsigned IntReg = LargestIntReg - 1; 1365 IntReg >= (unsigned)MVT::i1; --IntReg) { 1366 MVT IVT = (MVT::SimpleValueType)IntReg; 1367 if (isTypeLegal(IVT)) { 1368 LegalIntReg = IntReg; 1369 } else { 1370 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1371 (const MVT::SimpleValueType)LegalIntReg; 1372 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1373 } 1374 } 1375 1376 // ppcf128 type is really two f64's. 1377 if (!isTypeLegal(MVT::ppcf128)) { 1378 if (isTypeLegal(MVT::f64)) { 1379 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1380 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1381 TransformToType[MVT::ppcf128] = MVT::f64; 1382 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1383 } else { 1384 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1385 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1386 TransformToType[MVT::ppcf128] = MVT::i128; 1387 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1388 } 1389 } 1390 1391 // Decide how to handle f128. If the target does not have native f128 support, 1392 // expand it to i128 and we will be generating soft float library calls. 1393 if (!isTypeLegal(MVT::f128)) { 1394 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1395 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1396 TransformToType[MVT::f128] = MVT::i128; 1397 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1398 } 1399 1400 // Decide how to handle f64. If the target does not have native f64 support, 1401 // expand it to i64 and we will be generating soft float library calls. 1402 if (!isTypeLegal(MVT::f64)) { 1403 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1404 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1405 TransformToType[MVT::f64] = MVT::i64; 1406 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1407 } 1408 1409 // Decide how to handle f32. If the target does not have native f32 support, 1410 // expand it to i32 and we will be generating soft float library calls. 1411 if (!isTypeLegal(MVT::f32)) { 1412 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1413 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1414 TransformToType[MVT::f32] = MVT::i32; 1415 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1416 } 1417 1418 // Decide how to handle f16. If the target does not have native f16 support, 1419 // promote it to f32, because there are no f16 library calls (except for 1420 // conversions). 1421 if (!isTypeLegal(MVT::f16)) { 1422 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1423 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1424 TransformToType[MVT::f16] = MVT::f32; 1425 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1426 } 1427 1428 // Loop over all of the vector value types to see which need transformations. 1429 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1430 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1431 MVT VT = (MVT::SimpleValueType) i; 1432 if (isTypeLegal(VT)) 1433 continue; 1434 1435 MVT EltVT = VT.getVectorElementType(); 1436 unsigned NElts = VT.getVectorNumElements(); 1437 bool IsLegalWiderType = false; 1438 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1439 switch (PreferredAction) { 1440 case TypePromoteInteger: { 1441 // Try to promote the elements of integer vectors. If no legal 1442 // promotion was found, fall through to the widen-vector method. 1443 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) { 1444 MVT SVT = (MVT::SimpleValueType) nVT; 1445 // Promote vectors of integers to vectors with the same number 1446 // of elements, with a wider element type. 1447 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() && 1448 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) { 1449 TransformToType[i] = SVT; 1450 RegisterTypeForVT[i] = SVT; 1451 NumRegistersForVT[i] = 1; 1452 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1453 IsLegalWiderType = true; 1454 break; 1455 } 1456 } 1457 if (IsLegalWiderType) 1458 break; 1459 LLVM_FALLTHROUGH; 1460 } 1461 case TypeWidenVector: { 1462 // Try to widen the vector. 1463 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1464 MVT SVT = (MVT::SimpleValueType) nVT; 1465 if (SVT.getVectorElementType() == EltVT 1466 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1467 TransformToType[i] = SVT; 1468 RegisterTypeForVT[i] = SVT; 1469 NumRegistersForVT[i] = 1; 1470 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1471 IsLegalWiderType = true; 1472 break; 1473 } 1474 } 1475 if (IsLegalWiderType) 1476 break; 1477 LLVM_FALLTHROUGH; 1478 } 1479 case TypeSplitVector: 1480 case TypeScalarizeVector: { 1481 MVT IntermediateVT; 1482 MVT RegisterVT; 1483 unsigned NumIntermediates; 1484 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1485 NumIntermediates, RegisterVT, this); 1486 RegisterTypeForVT[i] = RegisterVT; 1487 1488 MVT NVT = VT.getPow2VectorType(); 1489 if (NVT == VT) { 1490 // Type is already a power of 2. The default action is to split. 1491 TransformToType[i] = MVT::Other; 1492 if (PreferredAction == TypeScalarizeVector) 1493 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1494 else if (PreferredAction == TypeSplitVector) 1495 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1496 else 1497 // Set type action according to the number of elements. 1498 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1499 : TypeSplitVector); 1500 } else { 1501 TransformToType[i] = NVT; 1502 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1503 } 1504 break; 1505 } 1506 default: 1507 llvm_unreachable("Unknown vector legalization action!"); 1508 } 1509 } 1510 1511 // Determine the 'representative' register class for each value type. 1512 // An representative register class is the largest (meaning one which is 1513 // not a sub-register class / subreg register class) legal register class for 1514 // a group of value types. For example, on i386, i8, i16, and i32 1515 // representative would be GR32; while on x86_64 it's GR64. 1516 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1517 const TargetRegisterClass* RRC; 1518 uint8_t Cost; 1519 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1520 RepRegClassForVT[i] = RRC; 1521 RepRegClassCostForVT[i] = Cost; 1522 } 1523 } 1524 1525 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1526 EVT VT) const { 1527 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1528 return getPointerTy(DL).SimpleTy; 1529 } 1530 1531 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1532 return MVT::i32; // return the default value 1533 } 1534 1535 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1536 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1537 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1538 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1539 /// 1540 /// This method returns the number of registers needed, and the VT for each 1541 /// register. It also returns the VT and quantity of the intermediate values 1542 /// before they are promoted/expanded. 1543 /// 1544 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1545 EVT &IntermediateVT, 1546 unsigned &NumIntermediates, 1547 MVT &RegisterVT) const { 1548 unsigned NumElts = VT.getVectorNumElements(); 1549 1550 // If there is a wider vector type with the same element type as this one, 1551 // or a promoted vector type that has the same number of elements which 1552 // are wider, then we should convert to that legal vector type. 1553 // This handles things like <2 x float> -> <4 x float> and 1554 // <4 x i1> -> <4 x i32>. 1555 LegalizeTypeAction TA = getTypeAction(Context, VT); 1556 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1557 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1558 if (isTypeLegal(RegisterEVT)) { 1559 IntermediateVT = RegisterEVT; 1560 RegisterVT = RegisterEVT.getSimpleVT(); 1561 NumIntermediates = 1; 1562 return 1; 1563 } 1564 } 1565 1566 // Figure out the right, legal destination reg to copy into. 1567 EVT EltTy = VT.getVectorElementType(); 1568 1569 unsigned NumVectorRegs = 1; 1570 1571 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1572 // could break down into LHS/RHS like LegalizeDAG does. 1573 if (!isPowerOf2_32(NumElts)) { 1574 NumVectorRegs = NumElts; 1575 NumElts = 1; 1576 } 1577 1578 // Divide the input until we get to a supported size. This will always 1579 // end with a scalar if the target doesn't support vectors. 1580 while (NumElts > 1 && !isTypeLegal( 1581 EVT::getVectorVT(Context, EltTy, NumElts))) { 1582 NumElts >>= 1; 1583 NumVectorRegs <<= 1; 1584 } 1585 1586 NumIntermediates = NumVectorRegs; 1587 1588 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1589 if (!isTypeLegal(NewVT)) 1590 NewVT = EltTy; 1591 IntermediateVT = NewVT; 1592 1593 MVT DestVT = getRegisterType(Context, NewVT); 1594 RegisterVT = DestVT; 1595 unsigned NewVTSize = NewVT.getSizeInBits(); 1596 1597 // Convert sizes such as i33 to i64. 1598 if (!isPowerOf2_32(NewVTSize)) 1599 NewVTSize = NextPowerOf2(NewVTSize); 1600 1601 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1602 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1603 1604 // Otherwise, promotion or legal types use the same number of registers as 1605 // the vector decimated to the appropriate level. 1606 return NumVectorRegs; 1607 } 1608 1609 /// Get the EVTs and ArgFlags collections that represent the legalized return 1610 /// type of the given function. This does not require a DAG or a return value, 1611 /// and is suitable for use before any DAGs for the function are constructed. 1612 /// TODO: Move this out of TargetLowering.cpp. 1613 void llvm::GetReturnInfo(Type *ReturnType, AttributeList attr, 1614 SmallVectorImpl<ISD::OutputArg> &Outs, 1615 const TargetLowering &TLI, const DataLayout &DL) { 1616 SmallVector<EVT, 4> ValueVTs; 1617 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1618 unsigned NumValues = ValueVTs.size(); 1619 if (NumValues == 0) return; 1620 1621 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1622 EVT VT = ValueVTs[j]; 1623 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1624 1625 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1626 ExtendKind = ISD::SIGN_EXTEND; 1627 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1628 ExtendKind = ISD::ZERO_EXTEND; 1629 1630 // FIXME: C calling convention requires the return type to be promoted to 1631 // at least 32-bit. But this is not necessary for non-C calling 1632 // conventions. The frontend should mark functions whose return values 1633 // require promoting with signext or zeroext attributes. 1634 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1635 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1636 if (VT.bitsLT(MinVT)) 1637 VT = MinVT; 1638 } 1639 1640 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1641 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1642 1643 // 'inreg' on function refers to return value 1644 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1645 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg)) 1646 Flags.setInReg(); 1647 1648 // Propagate extension type if any 1649 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1650 Flags.setSExt(); 1651 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1652 Flags.setZExt(); 1653 1654 for (unsigned i = 0; i < NumParts; ++i) 1655 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1656 } 1657 } 1658 1659 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1660 /// function arguments in the caller parameter area. This is the actual 1661 /// alignment, not its logarithm. 1662 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1663 const DataLayout &DL) const { 1664 return DL.getABITypeAlignment(Ty); 1665 } 1666 1667 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1668 const DataLayout &DL, EVT VT, 1669 unsigned AddrSpace, 1670 unsigned Alignment, 1671 bool *Fast) const { 1672 // Check if the specified alignment is sufficient based on the data layout. 1673 // TODO: While using the data layout works in practice, a better solution 1674 // would be to implement this check directly (make this a virtual function). 1675 // For example, the ABI alignment may change based on software platform while 1676 // this function should only be affected by hardware implementation. 1677 Type *Ty = VT.getTypeForEVT(Context); 1678 if (Alignment >= DL.getABITypeAlignment(Ty)) { 1679 // Assume that an access that meets the ABI-specified alignment is fast. 1680 if (Fast != nullptr) 1681 *Fast = true; 1682 return true; 1683 } 1684 1685 // This is a misaligned access. 1686 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast); 1687 } 1688 1689 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1690 return BranchProbability(MinPercentageForPredictableBranch, 100); 1691 } 1692 1693 //===----------------------------------------------------------------------===// 1694 // TargetTransformInfo Helpers 1695 //===----------------------------------------------------------------------===// 1696 1697 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1698 enum InstructionOpcodes { 1699 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1700 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1701 #include "llvm/IR/Instruction.def" 1702 }; 1703 switch (static_cast<InstructionOpcodes>(Opcode)) { 1704 case Ret: return 0; 1705 case Br: return 0; 1706 case Switch: return 0; 1707 case IndirectBr: return 0; 1708 case Invoke: return 0; 1709 case Resume: return 0; 1710 case Unreachable: return 0; 1711 case CleanupRet: return 0; 1712 case CatchRet: return 0; 1713 case CatchPad: return 0; 1714 case CatchSwitch: return 0; 1715 case CleanupPad: return 0; 1716 case Add: return ISD::ADD; 1717 case FAdd: return ISD::FADD; 1718 case Sub: return ISD::SUB; 1719 case FSub: return ISD::FSUB; 1720 case Mul: return ISD::MUL; 1721 case FMul: return ISD::FMUL; 1722 case UDiv: return ISD::UDIV; 1723 case SDiv: return ISD::SDIV; 1724 case FDiv: return ISD::FDIV; 1725 case URem: return ISD::UREM; 1726 case SRem: return ISD::SREM; 1727 case FRem: return ISD::FREM; 1728 case Shl: return ISD::SHL; 1729 case LShr: return ISD::SRL; 1730 case AShr: return ISD::SRA; 1731 case And: return ISD::AND; 1732 case Or: return ISD::OR; 1733 case Xor: return ISD::XOR; 1734 case Alloca: return 0; 1735 case Load: return ISD::LOAD; 1736 case Store: return ISD::STORE; 1737 case GetElementPtr: return 0; 1738 case Fence: return 0; 1739 case AtomicCmpXchg: return 0; 1740 case AtomicRMW: return 0; 1741 case Trunc: return ISD::TRUNCATE; 1742 case ZExt: return ISD::ZERO_EXTEND; 1743 case SExt: return ISD::SIGN_EXTEND; 1744 case FPToUI: return ISD::FP_TO_UINT; 1745 case FPToSI: return ISD::FP_TO_SINT; 1746 case UIToFP: return ISD::UINT_TO_FP; 1747 case SIToFP: return ISD::SINT_TO_FP; 1748 case FPTrunc: return ISD::FP_ROUND; 1749 case FPExt: return ISD::FP_EXTEND; 1750 case PtrToInt: return ISD::BITCAST; 1751 case IntToPtr: return ISD::BITCAST; 1752 case BitCast: return ISD::BITCAST; 1753 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1754 case ICmp: return ISD::SETCC; 1755 case FCmp: return ISD::SETCC; 1756 case PHI: return 0; 1757 case Call: return 0; 1758 case Select: return ISD::SELECT; 1759 case UserOp1: return 0; 1760 case UserOp2: return 0; 1761 case VAArg: return 0; 1762 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1763 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1764 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1765 case ExtractValue: return ISD::MERGE_VALUES; 1766 case InsertValue: return ISD::MERGE_VALUES; 1767 case LandingPad: return 0; 1768 } 1769 1770 llvm_unreachable("Unknown instruction type encountered!"); 1771 } 1772 1773 std::pair<int, MVT> 1774 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1775 Type *Ty) const { 1776 LLVMContext &C = Ty->getContext(); 1777 EVT MTy = getValueType(DL, Ty); 1778 1779 int Cost = 1; 1780 // We keep legalizing the type until we find a legal kind. We assume that 1781 // the only operation that costs anything is the split. After splitting 1782 // we need to handle two types. 1783 while (true) { 1784 LegalizeKind LK = getTypeConversion(C, MTy); 1785 1786 if (LK.first == TypeLegal) 1787 return std::make_pair(Cost, MTy.getSimpleVT()); 1788 1789 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1790 Cost *= 2; 1791 1792 // Do not loop with f128 type. 1793 if (MTy == LK.second) 1794 return std::make_pair(Cost, MTy.getSimpleVT()); 1795 1796 // Keep legalizing the type. 1797 MTy = LK.second; 1798 } 1799 } 1800 1801 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, 1802 bool UseTLS) const { 1803 // compiler-rt provides a variable with a magic name. Targets that do not 1804 // link with compiler-rt may also provide such a variable. 1805 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1806 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr"; 1807 auto UnsafeStackPtr = 1808 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar)); 1809 1810 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1811 1812 if (!UnsafeStackPtr) { 1813 auto TLSModel = UseTLS ? 1814 GlobalValue::InitialExecTLSModel : 1815 GlobalValue::NotThreadLocal; 1816 // The global variable is not defined yet, define it ourselves. 1817 // We use the initial-exec TLS model because we do not support the 1818 // variable living anywhere other than in the main executable. 1819 UnsafeStackPtr = new GlobalVariable( 1820 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr, 1821 UnsafeStackPtrVar, nullptr, TLSModel); 1822 } else { 1823 // The variable exists, check its type and attributes. 1824 if (UnsafeStackPtr->getValueType() != StackPtrTy) 1825 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type"); 1826 if (UseTLS != UnsafeStackPtr->isThreadLocal()) 1827 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " + 1828 (UseTLS ? "" : "not ") + "be thread-local"); 1829 } 1830 return UnsafeStackPtr; 1831 } 1832 1833 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1834 if (!TM.getTargetTriple().isAndroid()) 1835 return getDefaultSafeStackPointerLocation(IRB, true); 1836 1837 // Android provides a libc function to retrieve the address of the current 1838 // thread's unsafe stack pointer. 1839 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1840 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1841 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address", 1842 StackPtrTy->getPointerTo(0)); 1843 return IRB.CreateCall(Fn); 1844 } 1845 1846 //===----------------------------------------------------------------------===// 1847 // Loop Strength Reduction hooks 1848 //===----------------------------------------------------------------------===// 1849 1850 /// isLegalAddressingMode - Return true if the addressing mode represented 1851 /// by AM is legal for this target, for a load/store of the specified type. 1852 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1853 const AddrMode &AM, Type *Ty, 1854 unsigned AS) const { 1855 // The default implementation of this implements a conservative RISCy, r+r and 1856 // r+i addr mode. 1857 1858 // Allows a sign-extended 16-bit immediate field. 1859 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1860 return false; 1861 1862 // No global is ever allowed as a base. 1863 if (AM.BaseGV) 1864 return false; 1865 1866 // Only support r+r, 1867 switch (AM.Scale) { 1868 case 0: // "r+i" or just "i", depending on HasBaseReg. 1869 break; 1870 case 1: 1871 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1872 return false; 1873 // Otherwise we have r+r or r+i. 1874 break; 1875 case 2: 1876 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1877 return false; 1878 // Allow 2*r as r+r. 1879 break; 1880 default: // Don't allow n * r 1881 return false; 1882 } 1883 1884 return true; 1885 } 1886 1887 //===----------------------------------------------------------------------===// 1888 // Stack Protector 1889 //===----------------------------------------------------------------------===// 1890 1891 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1892 // so that SelectionDAG handle SSP. 1893 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1894 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1895 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1896 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1897 return M.getOrInsertGlobal("__guard_local", PtrTy); 1898 } 1899 return nullptr; 1900 } 1901 1902 // Currently only support "standard" __stack_chk_guard. 1903 // TODO: add LOAD_STACK_GUARD support. 1904 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1905 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext())); 1906 } 1907 1908 // Currently only support "standard" __stack_chk_guard. 1909 // TODO: add LOAD_STACK_GUARD support. 1910 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1911 return M.getGlobalVariable("__stack_chk_guard", true); 1912 } 1913 1914 Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1915 return nullptr; 1916 } 1917 1918 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const { 1919 return MinimumJumpTableEntries; 1920 } 1921 1922 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) { 1923 MinimumJumpTableEntries = Val; 1924 } 1925 1926 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const { 1927 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity; 1928 } 1929 1930 unsigned TargetLoweringBase::getMaximumJumpTableSize() const { 1931 return MaximumJumpTableSize; 1932 } 1933 1934 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) { 1935 MaximumJumpTableSize = Val; 1936 } 1937 1938 //===----------------------------------------------------------------------===// 1939 // Reciprocal Estimates 1940 //===----------------------------------------------------------------------===// 1941 1942 /// Get the reciprocal estimate attribute string for a function that will 1943 /// override the target defaults. 1944 static StringRef getRecipEstimateForFunc(MachineFunction &MF) { 1945 const Function *F = MF.getFunction(); 1946 return F->getFnAttribute("reciprocal-estimates").getValueAsString(); 1947 } 1948 1949 /// Construct a string for the given reciprocal operation of the given type. 1950 /// This string should match the corresponding option to the front-end's 1951 /// "-mrecip" flag assuming those strings have been passed through in an 1952 /// attribute string. For example, "vec-divf" for a division of a vXf32. 1953 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { 1954 std::string Name = VT.isVector() ? "vec-" : ""; 1955 1956 Name += IsSqrt ? "sqrt" : "div"; 1957 1958 // TODO: Handle "half" or other float types? 1959 if (VT.getScalarType() == MVT::f64) { 1960 Name += "d"; 1961 } else { 1962 assert(VT.getScalarType() == MVT::f32 && 1963 "Unexpected FP type for reciprocal estimate"); 1964 Name += "f"; 1965 } 1966 1967 return Name; 1968 } 1969 1970 /// Return the character position and value (a single numeric character) of a 1971 /// customized refinement operation in the input string if it exists. Return 1972 /// false if there is no customized refinement step count. 1973 static bool parseRefinementStep(StringRef In, size_t &Position, 1974 uint8_t &Value) { 1975 const char RefStepToken = ':'; 1976 Position = In.find(RefStepToken); 1977 if (Position == StringRef::npos) 1978 return false; 1979 1980 StringRef RefStepString = In.substr(Position + 1); 1981 // Allow exactly one numeric character for the additional refinement 1982 // step parameter. 1983 if (RefStepString.size() == 1) { 1984 char RefStepChar = RefStepString[0]; 1985 if (RefStepChar >= '0' && RefStepChar <= '9') { 1986 Value = RefStepChar - '0'; 1987 return true; 1988 } 1989 } 1990 report_fatal_error("Invalid refinement step for -recip."); 1991 } 1992 1993 /// For the input attribute string, return one of the ReciprocalEstimate enum 1994 /// status values (enabled, disabled, or not specified) for this operation on 1995 /// the specified data type. 1996 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { 1997 if (Override.empty()) 1998 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1999 2000 SmallVector<StringRef, 4> OverrideVector; 2001 SplitString(Override, OverrideVector, ","); 2002 unsigned NumArgs = OverrideVector.size(); 2003 2004 // Check if "all", "none", or "default" was specified. 2005 if (NumArgs == 1) { 2006 // Look for an optional setting of the number of refinement steps needed 2007 // for this type of reciprocal operation. 2008 size_t RefPos; 2009 uint8_t RefSteps; 2010 if (parseRefinementStep(Override, RefPos, RefSteps)) { 2011 // Split the string for further processing. 2012 Override = Override.substr(0, RefPos); 2013 } 2014 2015 // All reciprocal types are enabled. 2016 if (Override == "all") 2017 return TargetLoweringBase::ReciprocalEstimate::Enabled; 2018 2019 // All reciprocal types are disabled. 2020 if (Override == "none") 2021 return TargetLoweringBase::ReciprocalEstimate::Disabled; 2022 2023 // Target defaults for enablement are used. 2024 if (Override == "default") 2025 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2026 } 2027 2028 // The attribute string may omit the size suffix ('f'/'d'). 2029 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2030 std::string VTNameNoSize = VTName; 2031 VTNameNoSize.pop_back(); 2032 static const char DisabledPrefix = '!'; 2033 2034 for (StringRef RecipType : OverrideVector) { 2035 size_t RefPos; 2036 uint8_t RefSteps; 2037 if (parseRefinementStep(RecipType, RefPos, RefSteps)) 2038 RecipType = RecipType.substr(0, RefPos); 2039 2040 // Ignore the disablement token for string matching. 2041 bool IsDisabled = RecipType[0] == DisabledPrefix; 2042 if (IsDisabled) 2043 RecipType = RecipType.substr(1); 2044 2045 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2046 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled 2047 : TargetLoweringBase::ReciprocalEstimate::Enabled; 2048 } 2049 2050 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2051 } 2052 2053 /// For the input attribute string, return the customized refinement step count 2054 /// for this operation on the specified data type. If the step count does not 2055 /// exist, return the ReciprocalEstimate enum value for unspecified. 2056 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { 2057 if (Override.empty()) 2058 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2059 2060 SmallVector<StringRef, 4> OverrideVector; 2061 SplitString(Override, OverrideVector, ","); 2062 unsigned NumArgs = OverrideVector.size(); 2063 2064 // Check if "all", "default", or "none" was specified. 2065 if (NumArgs == 1) { 2066 // Look for an optional setting of the number of refinement steps needed 2067 // for this type of reciprocal operation. 2068 size_t RefPos; 2069 uint8_t RefSteps; 2070 if (!parseRefinementStep(Override, RefPos, RefSteps)) 2071 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2072 2073 // Split the string for further processing. 2074 Override = Override.substr(0, RefPos); 2075 assert(Override != "none" && 2076 "Disabled reciprocals, but specifed refinement steps?"); 2077 2078 // If this is a general override, return the specified number of steps. 2079 if (Override == "all" || Override == "default") 2080 return RefSteps; 2081 } 2082 2083 // The attribute string may omit the size suffix ('f'/'d'). 2084 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2085 std::string VTNameNoSize = VTName; 2086 VTNameNoSize.pop_back(); 2087 2088 for (StringRef RecipType : OverrideVector) { 2089 size_t RefPos; 2090 uint8_t RefSteps; 2091 if (!parseRefinementStep(RecipType, RefPos, RefSteps)) 2092 continue; 2093 2094 RecipType = RecipType.substr(0, RefPos); 2095 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2096 return RefSteps; 2097 } 2098 2099 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2100 } 2101 2102 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, 2103 MachineFunction &MF) const { 2104 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); 2105 } 2106 2107 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, 2108 MachineFunction &MF) const { 2109 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); 2110 } 2111 2112 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, 2113 MachineFunction &MF) const { 2114 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); 2115 } 2116 2117 int TargetLoweringBase::getDivRefinementSteps(EVT VT, 2118 MachineFunction &MF) const { 2119 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); 2120 } 2121 2122 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { 2123 MF.getRegInfo().freezeReservedRegs(MF); 2124 } 2125