1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/MC/MCAsmInfo.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/Target/TargetData.h" 18 #include "llvm/Target/TargetLoweringObjectFile.h" 19 #include "llvm/Target/TargetMachine.h" 20 #include "llvm/Target/TargetRegisterInfo.h" 21 #include "llvm/GlobalVariable.h" 22 #include "llvm/DerivedTypes.h" 23 #include "llvm/CodeGen/Analysis.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineJumpTableInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/SelectionDAG.h" 28 #include "llvm/ADT/STLExtras.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/MathExtras.h" 31 using namespace llvm; 32 33 namespace llvm { 34 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { 35 bool isLocal = GV->hasLocalLinkage(); 36 bool isDeclaration = GV->isDeclaration(); 37 // FIXME: what should we do for protected and internal visibility? 38 // For variables, is internal different from hidden? 39 bool isHidden = GV->hasHiddenVisibility(); 40 41 if (reloc == Reloc::PIC_) { 42 if (isLocal || isHidden) 43 return TLSModel::LocalDynamic; 44 else 45 return TLSModel::GeneralDynamic; 46 } else { 47 if (!isDeclaration || isHidden) 48 return TLSModel::LocalExec; 49 else 50 return TLSModel::InitialExec; 51 } 52 } 53 } 54 55 /// InitLibcallNames - Set default libcall names. 56 /// 57 static void InitLibcallNames(const char **Names) { 58 Names[RTLIB::SHL_I16] = "__ashlhi3"; 59 Names[RTLIB::SHL_I32] = "__ashlsi3"; 60 Names[RTLIB::SHL_I64] = "__ashldi3"; 61 Names[RTLIB::SHL_I128] = "__ashlti3"; 62 Names[RTLIB::SRL_I16] = "__lshrhi3"; 63 Names[RTLIB::SRL_I32] = "__lshrsi3"; 64 Names[RTLIB::SRL_I64] = "__lshrdi3"; 65 Names[RTLIB::SRL_I128] = "__lshrti3"; 66 Names[RTLIB::SRA_I16] = "__ashrhi3"; 67 Names[RTLIB::SRA_I32] = "__ashrsi3"; 68 Names[RTLIB::SRA_I64] = "__ashrdi3"; 69 Names[RTLIB::SRA_I128] = "__ashrti3"; 70 Names[RTLIB::MUL_I8] = "__mulqi3"; 71 Names[RTLIB::MUL_I16] = "__mulhi3"; 72 Names[RTLIB::MUL_I32] = "__mulsi3"; 73 Names[RTLIB::MUL_I64] = "__muldi3"; 74 Names[RTLIB::MUL_I128] = "__multi3"; 75 Names[RTLIB::SDIV_I8] = "__divqi3"; 76 Names[RTLIB::SDIV_I16] = "__divhi3"; 77 Names[RTLIB::SDIV_I32] = "__divsi3"; 78 Names[RTLIB::SDIV_I64] = "__divdi3"; 79 Names[RTLIB::SDIV_I128] = "__divti3"; 80 Names[RTLIB::UDIV_I8] = "__udivqi3"; 81 Names[RTLIB::UDIV_I16] = "__udivhi3"; 82 Names[RTLIB::UDIV_I32] = "__udivsi3"; 83 Names[RTLIB::UDIV_I64] = "__udivdi3"; 84 Names[RTLIB::UDIV_I128] = "__udivti3"; 85 Names[RTLIB::SREM_I8] = "__modqi3"; 86 Names[RTLIB::SREM_I16] = "__modhi3"; 87 Names[RTLIB::SREM_I32] = "__modsi3"; 88 Names[RTLIB::SREM_I64] = "__moddi3"; 89 Names[RTLIB::SREM_I128] = "__modti3"; 90 Names[RTLIB::UREM_I8] = "__umodqi3"; 91 Names[RTLIB::UREM_I16] = "__umodhi3"; 92 Names[RTLIB::UREM_I32] = "__umodsi3"; 93 Names[RTLIB::UREM_I64] = "__umoddi3"; 94 Names[RTLIB::UREM_I128] = "__umodti3"; 95 Names[RTLIB::NEG_I32] = "__negsi2"; 96 Names[RTLIB::NEG_I64] = "__negdi2"; 97 Names[RTLIB::ADD_F32] = "__addsf3"; 98 Names[RTLIB::ADD_F64] = "__adddf3"; 99 Names[RTLIB::ADD_F80] = "__addxf3"; 100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 101 Names[RTLIB::SUB_F32] = "__subsf3"; 102 Names[RTLIB::SUB_F64] = "__subdf3"; 103 Names[RTLIB::SUB_F80] = "__subxf3"; 104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 105 Names[RTLIB::MUL_F32] = "__mulsf3"; 106 Names[RTLIB::MUL_F64] = "__muldf3"; 107 Names[RTLIB::MUL_F80] = "__mulxf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 113 Names[RTLIB::REM_F32] = "fmodf"; 114 Names[RTLIB::REM_F64] = "fmod"; 115 Names[RTLIB::REM_F80] = "fmodl"; 116 Names[RTLIB::REM_PPCF128] = "fmodl"; 117 Names[RTLIB::POWI_F32] = "__powisf2"; 118 Names[RTLIB::POWI_F64] = "__powidf2"; 119 Names[RTLIB::POWI_F80] = "__powixf2"; 120 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 121 Names[RTLIB::SQRT_F32] = "sqrtf"; 122 Names[RTLIB::SQRT_F64] = "sqrt"; 123 Names[RTLIB::SQRT_F80] = "sqrtl"; 124 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 125 Names[RTLIB::LOG_F32] = "logf"; 126 Names[RTLIB::LOG_F64] = "log"; 127 Names[RTLIB::LOG_F80] = "logl"; 128 Names[RTLIB::LOG_PPCF128] = "logl"; 129 Names[RTLIB::LOG2_F32] = "log2f"; 130 Names[RTLIB::LOG2_F64] = "log2"; 131 Names[RTLIB::LOG2_F80] = "log2l"; 132 Names[RTLIB::LOG2_PPCF128] = "log2l"; 133 Names[RTLIB::LOG10_F32] = "log10f"; 134 Names[RTLIB::LOG10_F64] = "log10"; 135 Names[RTLIB::LOG10_F80] = "log10l"; 136 Names[RTLIB::LOG10_PPCF128] = "log10l"; 137 Names[RTLIB::EXP_F32] = "expf"; 138 Names[RTLIB::EXP_F64] = "exp"; 139 Names[RTLIB::EXP_F80] = "expl"; 140 Names[RTLIB::EXP_PPCF128] = "expl"; 141 Names[RTLIB::EXP2_F32] = "exp2f"; 142 Names[RTLIB::EXP2_F64] = "exp2"; 143 Names[RTLIB::EXP2_F80] = "exp2l"; 144 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 145 Names[RTLIB::SIN_F32] = "sinf"; 146 Names[RTLIB::SIN_F64] = "sin"; 147 Names[RTLIB::SIN_F80] = "sinl"; 148 Names[RTLIB::SIN_PPCF128] = "sinl"; 149 Names[RTLIB::COS_F32] = "cosf"; 150 Names[RTLIB::COS_F64] = "cos"; 151 Names[RTLIB::COS_F80] = "cosl"; 152 Names[RTLIB::COS_PPCF128] = "cosl"; 153 Names[RTLIB::POW_F32] = "powf"; 154 Names[RTLIB::POW_F64] = "pow"; 155 Names[RTLIB::POW_F80] = "powl"; 156 Names[RTLIB::POW_PPCF128] = "powl"; 157 Names[RTLIB::CEIL_F32] = "ceilf"; 158 Names[RTLIB::CEIL_F64] = "ceil"; 159 Names[RTLIB::CEIL_F80] = "ceill"; 160 Names[RTLIB::CEIL_PPCF128] = "ceill"; 161 Names[RTLIB::TRUNC_F32] = "truncf"; 162 Names[RTLIB::TRUNC_F64] = "trunc"; 163 Names[RTLIB::TRUNC_F80] = "truncl"; 164 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 165 Names[RTLIB::RINT_F32] = "rintf"; 166 Names[RTLIB::RINT_F64] = "rint"; 167 Names[RTLIB::RINT_F80] = "rintl"; 168 Names[RTLIB::RINT_PPCF128] = "rintl"; 169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 170 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 173 Names[RTLIB::FLOOR_F32] = "floorf"; 174 Names[RTLIB::FLOOR_F64] = "floor"; 175 Names[RTLIB::FLOOR_F80] = "floorl"; 176 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 177 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 178 Names[RTLIB::COPYSIGN_F64] = "copysign"; 179 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 245 Names[RTLIB::OEQ_F32] = "__eqsf2"; 246 Names[RTLIB::OEQ_F64] = "__eqdf2"; 247 Names[RTLIB::UNE_F32] = "__nesf2"; 248 Names[RTLIB::UNE_F64] = "__nedf2"; 249 Names[RTLIB::OGE_F32] = "__gesf2"; 250 Names[RTLIB::OGE_F64] = "__gedf2"; 251 Names[RTLIB::OLT_F32] = "__ltsf2"; 252 Names[RTLIB::OLT_F64] = "__ltdf2"; 253 Names[RTLIB::OLE_F32] = "__lesf2"; 254 Names[RTLIB::OLE_F64] = "__ledf2"; 255 Names[RTLIB::OGT_F32] = "__gtsf2"; 256 Names[RTLIB::OGT_F64] = "__gtdf2"; 257 Names[RTLIB::UO_F32] = "__unordsf2"; 258 Names[RTLIB::UO_F64] = "__unorddf2"; 259 Names[RTLIB::O_F32] = "__unordsf2"; 260 Names[RTLIB::O_F64] = "__unorddf2"; 261 Names[RTLIB::MEMCPY] = "memcpy"; 262 Names[RTLIB::MEMMOVE] = "memmove"; 263 Names[RTLIB::MEMSET] = "memset"; 264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 273 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 274 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 275 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 276 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 277 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 278 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 279 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 280 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 281 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 282 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 283 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 284 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 285 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 286 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 287 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 288 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 289 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 290 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 291 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4"; 292 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 293 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 294 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 295 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 296 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 297 } 298 299 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 300 /// 301 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 302 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 303 CCs[i] = CallingConv::C; 304 } 305 } 306 307 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 308 /// UNKNOWN_LIBCALL if there is none. 309 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 310 if (OpVT == MVT::f32) { 311 if (RetVT == MVT::f64) 312 return FPEXT_F32_F64; 313 } 314 315 return UNKNOWN_LIBCALL; 316 } 317 318 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 319 /// UNKNOWN_LIBCALL if there is none. 320 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 321 if (RetVT == MVT::f32) { 322 if (OpVT == MVT::f64) 323 return FPROUND_F64_F32; 324 if (OpVT == MVT::f80) 325 return FPROUND_F80_F32; 326 if (OpVT == MVT::ppcf128) 327 return FPROUND_PPCF128_F32; 328 } else if (RetVT == MVT::f64) { 329 if (OpVT == MVT::f80) 330 return FPROUND_F80_F64; 331 if (OpVT == MVT::ppcf128) 332 return FPROUND_PPCF128_F64; 333 } 334 335 return UNKNOWN_LIBCALL; 336 } 337 338 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 339 /// UNKNOWN_LIBCALL if there is none. 340 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 341 if (OpVT == MVT::f32) { 342 if (RetVT == MVT::i8) 343 return FPTOSINT_F32_I8; 344 if (RetVT == MVT::i16) 345 return FPTOSINT_F32_I16; 346 if (RetVT == MVT::i32) 347 return FPTOSINT_F32_I32; 348 if (RetVT == MVT::i64) 349 return FPTOSINT_F32_I64; 350 if (RetVT == MVT::i128) 351 return FPTOSINT_F32_I128; 352 } else if (OpVT == MVT::f64) { 353 if (RetVT == MVT::i8) 354 return FPTOSINT_F64_I8; 355 if (RetVT == MVT::i16) 356 return FPTOSINT_F64_I16; 357 if (RetVT == MVT::i32) 358 return FPTOSINT_F64_I32; 359 if (RetVT == MVT::i64) 360 return FPTOSINT_F64_I64; 361 if (RetVT == MVT::i128) 362 return FPTOSINT_F64_I128; 363 } else if (OpVT == MVT::f80) { 364 if (RetVT == MVT::i32) 365 return FPTOSINT_F80_I32; 366 if (RetVT == MVT::i64) 367 return FPTOSINT_F80_I64; 368 if (RetVT == MVT::i128) 369 return FPTOSINT_F80_I128; 370 } else if (OpVT == MVT::ppcf128) { 371 if (RetVT == MVT::i32) 372 return FPTOSINT_PPCF128_I32; 373 if (RetVT == MVT::i64) 374 return FPTOSINT_PPCF128_I64; 375 if (RetVT == MVT::i128) 376 return FPTOSINT_PPCF128_I128; 377 } 378 return UNKNOWN_LIBCALL; 379 } 380 381 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 382 /// UNKNOWN_LIBCALL if there is none. 383 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 384 if (OpVT == MVT::f32) { 385 if (RetVT == MVT::i8) 386 return FPTOUINT_F32_I8; 387 if (RetVT == MVT::i16) 388 return FPTOUINT_F32_I16; 389 if (RetVT == MVT::i32) 390 return FPTOUINT_F32_I32; 391 if (RetVT == MVT::i64) 392 return FPTOUINT_F32_I64; 393 if (RetVT == MVT::i128) 394 return FPTOUINT_F32_I128; 395 } else if (OpVT == MVT::f64) { 396 if (RetVT == MVT::i8) 397 return FPTOUINT_F64_I8; 398 if (RetVT == MVT::i16) 399 return FPTOUINT_F64_I16; 400 if (RetVT == MVT::i32) 401 return FPTOUINT_F64_I32; 402 if (RetVT == MVT::i64) 403 return FPTOUINT_F64_I64; 404 if (RetVT == MVT::i128) 405 return FPTOUINT_F64_I128; 406 } else if (OpVT == MVT::f80) { 407 if (RetVT == MVT::i32) 408 return FPTOUINT_F80_I32; 409 if (RetVT == MVT::i64) 410 return FPTOUINT_F80_I64; 411 if (RetVT == MVT::i128) 412 return FPTOUINT_F80_I128; 413 } else if (OpVT == MVT::ppcf128) { 414 if (RetVT == MVT::i32) 415 return FPTOUINT_PPCF128_I32; 416 if (RetVT == MVT::i64) 417 return FPTOUINT_PPCF128_I64; 418 if (RetVT == MVT::i128) 419 return FPTOUINT_PPCF128_I128; 420 } 421 return UNKNOWN_LIBCALL; 422 } 423 424 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 425 /// UNKNOWN_LIBCALL if there is none. 426 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 427 if (OpVT == MVT::i32) { 428 if (RetVT == MVT::f32) 429 return SINTTOFP_I32_F32; 430 else if (RetVT == MVT::f64) 431 return SINTTOFP_I32_F64; 432 else if (RetVT == MVT::f80) 433 return SINTTOFP_I32_F80; 434 else if (RetVT == MVT::ppcf128) 435 return SINTTOFP_I32_PPCF128; 436 } else if (OpVT == MVT::i64) { 437 if (RetVT == MVT::f32) 438 return SINTTOFP_I64_F32; 439 else if (RetVT == MVT::f64) 440 return SINTTOFP_I64_F64; 441 else if (RetVT == MVT::f80) 442 return SINTTOFP_I64_F80; 443 else if (RetVT == MVT::ppcf128) 444 return SINTTOFP_I64_PPCF128; 445 } else if (OpVT == MVT::i128) { 446 if (RetVT == MVT::f32) 447 return SINTTOFP_I128_F32; 448 else if (RetVT == MVT::f64) 449 return SINTTOFP_I128_F64; 450 else if (RetVT == MVT::f80) 451 return SINTTOFP_I128_F80; 452 else if (RetVT == MVT::ppcf128) 453 return SINTTOFP_I128_PPCF128; 454 } 455 return UNKNOWN_LIBCALL; 456 } 457 458 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 459 /// UNKNOWN_LIBCALL if there is none. 460 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 461 if (OpVT == MVT::i32) { 462 if (RetVT == MVT::f32) 463 return UINTTOFP_I32_F32; 464 else if (RetVT == MVT::f64) 465 return UINTTOFP_I32_F64; 466 else if (RetVT == MVT::f80) 467 return UINTTOFP_I32_F80; 468 else if (RetVT == MVT::ppcf128) 469 return UINTTOFP_I32_PPCF128; 470 } else if (OpVT == MVT::i64) { 471 if (RetVT == MVT::f32) 472 return UINTTOFP_I64_F32; 473 else if (RetVT == MVT::f64) 474 return UINTTOFP_I64_F64; 475 else if (RetVT == MVT::f80) 476 return UINTTOFP_I64_F80; 477 else if (RetVT == MVT::ppcf128) 478 return UINTTOFP_I64_PPCF128; 479 } else if (OpVT == MVT::i128) { 480 if (RetVT == MVT::f32) 481 return UINTTOFP_I128_F32; 482 else if (RetVT == MVT::f64) 483 return UINTTOFP_I128_F64; 484 else if (RetVT == MVT::f80) 485 return UINTTOFP_I128_F80; 486 else if (RetVT == MVT::ppcf128) 487 return UINTTOFP_I128_PPCF128; 488 } 489 return UNKNOWN_LIBCALL; 490 } 491 492 /// InitCmpLibcallCCs - Set default comparison libcall CC. 493 /// 494 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 495 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 496 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 497 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 498 CCs[RTLIB::UNE_F32] = ISD::SETNE; 499 CCs[RTLIB::UNE_F64] = ISD::SETNE; 500 CCs[RTLIB::OGE_F32] = ISD::SETGE; 501 CCs[RTLIB::OGE_F64] = ISD::SETGE; 502 CCs[RTLIB::OLT_F32] = ISD::SETLT; 503 CCs[RTLIB::OLT_F64] = ISD::SETLT; 504 CCs[RTLIB::OLE_F32] = ISD::SETLE; 505 CCs[RTLIB::OLE_F64] = ISD::SETLE; 506 CCs[RTLIB::OGT_F32] = ISD::SETGT; 507 CCs[RTLIB::OGT_F64] = ISD::SETGT; 508 CCs[RTLIB::UO_F32] = ISD::SETNE; 509 CCs[RTLIB::UO_F64] = ISD::SETNE; 510 CCs[RTLIB::O_F32] = ISD::SETEQ; 511 CCs[RTLIB::O_F64] = ISD::SETEQ; 512 } 513 514 /// NOTE: The constructor takes ownership of TLOF. 515 TargetLowering::TargetLowering(const TargetMachine &tm, 516 const TargetLoweringObjectFile *tlof) 517 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { 518 // All operations default to being supported. 519 memset(OpActions, 0, sizeof(OpActions)); 520 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 521 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 522 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 523 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 524 525 // Set default actions for various operations. 526 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 527 // Default all indexed load / store to expand. 528 for (unsigned IM = (unsigned)ISD::PRE_INC; 529 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 530 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 531 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 532 } 533 534 // These operations default to expand. 535 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 536 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 537 } 538 539 // Most targets ignore the @llvm.prefetch intrinsic. 540 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 541 542 // ConstantFP nodes default to expand. Targets can either change this to 543 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 544 // to optimize expansions for certain constants. 545 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 546 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 547 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 548 549 // These library functions default to expand. 550 setOperationAction(ISD::FLOG , MVT::f64, Expand); 551 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 552 setOperationAction(ISD::FLOG10,MVT::f64, Expand); 553 setOperationAction(ISD::FEXP , MVT::f64, Expand); 554 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 555 setOperationAction(ISD::FLOG , MVT::f32, Expand); 556 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 557 setOperationAction(ISD::FLOG10,MVT::f32, Expand); 558 setOperationAction(ISD::FEXP , MVT::f32, Expand); 559 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 560 561 // Default ISD::TRAP to expand (which turns it into abort). 562 setOperationAction(ISD::TRAP, MVT::Other, Expand); 563 564 IsLittleEndian = TD->isLittleEndian(); 565 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize()); 566 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 567 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 568 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 569 benefitFromCodePlacementOpt = false; 570 UseUnderscoreSetJmp = false; 571 UseUnderscoreLongJmp = false; 572 SelectIsExpensive = false; 573 IntDivIsCheap = false; 574 Pow2DivIsCheap = false; 575 StackPointerRegisterToSaveRestore = 0; 576 ExceptionPointerRegister = 0; 577 ExceptionSelectorRegister = 0; 578 BooleanContents = UndefinedBooleanContent; 579 SchedPreferenceInfo = Sched::Latency; 580 JumpBufSize = 0; 581 JumpBufAlignment = 0; 582 PrefLoopAlignment = 0; 583 MinStackArgumentAlignment = 1; 584 ShouldFoldAtomicFences = false; 585 586 InitLibcallNames(LibcallRoutineNames); 587 InitCmpLibcallCCs(CmpLibcallCCs); 588 InitLibcallCallingConvs(LibcallCallingConvs); 589 } 590 591 TargetLowering::~TargetLowering() { 592 delete &TLOF; 593 } 594 595 /// canOpTrap - Returns true if the operation can trap for the value type. 596 /// VT must be a legal type. 597 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const { 598 assert(isTypeLegal(VT)); 599 switch (Op) { 600 default: 601 return false; 602 case ISD::FDIV: 603 case ISD::FREM: 604 case ISD::SDIV: 605 case ISD::UDIV: 606 case ISD::SREM: 607 case ISD::UREM: 608 return true; 609 } 610 } 611 612 613 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 614 unsigned &NumIntermediates, 615 EVT &RegisterVT, 616 TargetLowering *TLI) { 617 // Figure out the right, legal destination reg to copy into. 618 unsigned NumElts = VT.getVectorNumElements(); 619 MVT EltTy = VT.getVectorElementType(); 620 621 unsigned NumVectorRegs = 1; 622 623 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 624 // could break down into LHS/RHS like LegalizeDAG does. 625 if (!isPowerOf2_32(NumElts)) { 626 NumVectorRegs = NumElts; 627 NumElts = 1; 628 } 629 630 // Divide the input until we get to a supported size. This will always 631 // end with a scalar if the target doesn't support vectors. 632 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 633 NumElts >>= 1; 634 NumVectorRegs <<= 1; 635 } 636 637 NumIntermediates = NumVectorRegs; 638 639 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 640 if (!TLI->isTypeLegal(NewVT)) 641 NewVT = EltTy; 642 IntermediateVT = NewVT; 643 644 EVT DestVT = TLI->getRegisterType(NewVT); 645 RegisterVT = DestVT; 646 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 647 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 648 649 // Otherwise, promotion or legal types use the same number of registers as 650 // the vector decimated to the appropriate level. 651 return NumVectorRegs; 652 } 653 654 /// computeRegisterProperties - Once all of the register classes are added, 655 /// this allows us to compute derived properties we expose. 656 void TargetLowering::computeRegisterProperties() { 657 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 658 "Too many value types for ValueTypeActions to hold!"); 659 660 // Everything defaults to needing one register. 661 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 662 NumRegistersForVT[i] = 1; 663 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 664 } 665 // ...except isVoid, which doesn't need any registers. 666 NumRegistersForVT[MVT::isVoid] = 0; 667 668 // Find the largest integer register class. 669 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 670 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 671 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 672 673 // Every integer value type larger than this largest register takes twice as 674 // many registers to represent as the previous ValueType. 675 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { 676 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg; 677 if (!ExpandedVT.isInteger()) 678 break; 679 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 680 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 681 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 682 ValueTypeActions.setTypeAction(ExpandedVT, Expand); 683 } 684 685 // Inspect all of the ValueType's smaller than the largest integer 686 // register to see which ones need promotion. 687 unsigned LegalIntReg = LargestIntReg; 688 for (unsigned IntReg = LargestIntReg - 1; 689 IntReg >= (unsigned)MVT::i1; --IntReg) { 690 EVT IVT = (MVT::SimpleValueType)IntReg; 691 if (isTypeLegal(IVT)) { 692 LegalIntReg = IntReg; 693 } else { 694 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 695 (MVT::SimpleValueType)LegalIntReg; 696 ValueTypeActions.setTypeAction(IVT, Promote); 697 } 698 } 699 700 // ppcf128 type is really two f64's. 701 if (!isTypeLegal(MVT::ppcf128)) { 702 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 703 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 704 TransformToType[MVT::ppcf128] = MVT::f64; 705 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); 706 } 707 708 // Decide how to handle f64. If the target does not have native f64 support, 709 // expand it to i64 and we will be generating soft float library calls. 710 if (!isTypeLegal(MVT::f64)) { 711 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 712 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 713 TransformToType[MVT::f64] = MVT::i64; 714 ValueTypeActions.setTypeAction(MVT::f64, Expand); 715 } 716 717 // Decide how to handle f32. If the target does not have native support for 718 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 719 if (!isTypeLegal(MVT::f32)) { 720 if (isTypeLegal(MVT::f64)) { 721 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 722 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 723 TransformToType[MVT::f32] = MVT::f64; 724 ValueTypeActions.setTypeAction(MVT::f32, Promote); 725 } else { 726 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 727 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 728 TransformToType[MVT::f32] = MVT::i32; 729 ValueTypeActions.setTypeAction(MVT::f32, Expand); 730 } 731 } 732 733 // Loop over all of the vector value types to see which need transformations. 734 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 735 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 736 MVT VT = (MVT::SimpleValueType)i; 737 if (isTypeLegal(VT)) continue; 738 739 MVT IntermediateVT; 740 EVT RegisterVT; 741 unsigned NumIntermediates; 742 NumRegistersForVT[i] = 743 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 744 RegisterVT, this); 745 RegisterTypeForVT[i] = RegisterVT; 746 747 // Determine if there is a legal wider type. 748 bool IsLegalWiderType = false; 749 EVT EltVT = VT.getVectorElementType(); 750 unsigned NElts = VT.getVectorNumElements(); 751 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 752 EVT SVT = (MVT::SimpleValueType)nVT; 753 if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && 754 SVT.getVectorNumElements() > NElts && NElts != 1) { 755 TransformToType[i] = SVT; 756 ValueTypeActions.setTypeAction(VT, Promote); 757 IsLegalWiderType = true; 758 break; 759 } 760 } 761 if (!IsLegalWiderType) { 762 EVT NVT = VT.getPow2VectorType(); 763 if (NVT == VT) { 764 // Type is already a power of 2. The default action is to split. 765 TransformToType[i] = MVT::Other; 766 ValueTypeActions.setTypeAction(VT, Expand); 767 } else { 768 TransformToType[i] = NVT; 769 ValueTypeActions.setTypeAction(VT, Promote); 770 } 771 } 772 } 773 } 774 775 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { 776 return NULL; 777 } 778 779 780 MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { 781 return PointerTy.SimpleTy; 782 } 783 784 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const { 785 return MVT::i32; // return the default value 786 } 787 788 /// getVectorTypeBreakdown - Vector types are broken down into some number of 789 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 790 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 791 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 792 /// 793 /// This method returns the number of registers needed, and the VT for each 794 /// register. It also returns the VT and quantity of the intermediate values 795 /// before they are promoted/expanded. 796 /// 797 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 798 EVT &IntermediateVT, 799 unsigned &NumIntermediates, 800 EVT &RegisterVT) const { 801 // Figure out the right, legal destination reg to copy into. 802 unsigned NumElts = VT.getVectorNumElements(); 803 EVT EltTy = VT.getVectorElementType(); 804 805 unsigned NumVectorRegs = 1; 806 807 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 808 // could break down into LHS/RHS like LegalizeDAG does. 809 if (!isPowerOf2_32(NumElts)) { 810 NumVectorRegs = NumElts; 811 NumElts = 1; 812 } 813 814 // Divide the input until we get to a supported size. This will always 815 // end with a scalar if the target doesn't support vectors. 816 while (NumElts > 1 && !isTypeLegal( 817 EVT::getVectorVT(Context, EltTy, NumElts))) { 818 NumElts >>= 1; 819 NumVectorRegs <<= 1; 820 } 821 822 NumIntermediates = NumVectorRegs; 823 824 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 825 if (!isTypeLegal(NewVT)) 826 NewVT = EltTy; 827 IntermediateVT = NewVT; 828 829 EVT DestVT = getRegisterType(Context, NewVT); 830 RegisterVT = DestVT; 831 if (DestVT.bitsLT(NewVT)) { 832 // Value is expanded, e.g. i64 -> i16. 833 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits()); 834 } else { 835 // Otherwise, promotion or legal types use the same number of registers as 836 // the vector decimated to the appropriate level. 837 return NumVectorRegs; 838 } 839 840 return 1; 841 } 842 843 /// Get the EVTs and ArgFlags collections that represent the legalized return 844 /// type of the given function. This does not require a DAG or a return value, 845 /// and is suitable for use before any DAGs for the function are constructed. 846 /// TODO: Move this out of TargetLowering.cpp. 847 void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr, 848 SmallVectorImpl<ISD::OutputArg> &Outs, 849 const TargetLowering &TLI, 850 SmallVectorImpl<uint64_t> *Offsets) { 851 SmallVector<EVT, 4> ValueVTs; 852 ComputeValueVTs(TLI, ReturnType, ValueVTs); 853 unsigned NumValues = ValueVTs.size(); 854 if (NumValues == 0) return; 855 unsigned Offset = 0; 856 857 for (unsigned j = 0, f = NumValues; j != f; ++j) { 858 EVT VT = ValueVTs[j]; 859 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 860 861 if (attr & Attribute::SExt) 862 ExtendKind = ISD::SIGN_EXTEND; 863 else if (attr & Attribute::ZExt) 864 ExtendKind = ISD::ZERO_EXTEND; 865 866 // FIXME: C calling convention requires the return type to be promoted to 867 // at least 32-bit. But this is not necessary for non-C calling 868 // conventions. The frontend should mark functions whose return values 869 // require promoting with signext or zeroext attributes. 870 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 871 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 872 if (VT.bitsLT(MinVT)) 873 VT = MinVT; 874 } 875 876 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 877 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 878 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize( 879 PartVT.getTypeForEVT(ReturnType->getContext())); 880 881 // 'inreg' on function refers to return value 882 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 883 if (attr & Attribute::InReg) 884 Flags.setInReg(); 885 886 // Propagate extension type if any 887 if (attr & Attribute::SExt) 888 Flags.setSExt(); 889 else if (attr & Attribute::ZExt) 890 Flags.setZExt(); 891 892 for (unsigned i = 0; i < NumParts; ++i) { 893 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true)); 894 if (Offsets) { 895 Offsets->push_back(Offset); 896 Offset += PartSize; 897 } 898 } 899 } 900 } 901 902 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 903 /// function arguments in the caller parameter area. This is the actual 904 /// alignment, not its logarithm. 905 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const { 906 return TD->getCallFrameTypeAlignment(Ty); 907 } 908 909 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 910 /// current function. The returned value is a member of the 911 /// MachineJumpTableInfo::JTEntryKind enum. 912 unsigned TargetLowering::getJumpTableEncoding() const { 913 // In non-pic modes, just use the address of a block. 914 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 915 return MachineJumpTableInfo::EK_BlockAddress; 916 917 // In PIC mode, if the target supports a GPRel32 directive, use it. 918 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0) 919 return MachineJumpTableInfo::EK_GPRel32BlockAddress; 920 921 // Otherwise, use a label difference. 922 return MachineJumpTableInfo::EK_LabelDifference32; 923 } 924 925 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table, 926 SelectionDAG &DAG) const { 927 // If our PIC model is GP relative, use the global offset table as the base. 928 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress) 929 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy()); 930 return Table; 931 } 932 933 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 934 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 935 /// MCExpr. 936 const MCExpr * 937 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 938 unsigned JTI,MCContext &Ctx) const{ 939 // The normal PIC reloc base is the label at the start of the jump table. 940 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx); 941 } 942 943 bool 944 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 945 // Assume that everything is safe in static mode. 946 if (getTargetMachine().getRelocationModel() == Reloc::Static) 947 return true; 948 949 // In dynamic-no-pic mode, assume that known defined values are safe. 950 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC && 951 GA && 952 !GA->getGlobal()->isDeclaration() && 953 !GA->getGlobal()->isWeakForLinker()) 954 return true; 955 956 // Otherwise assume nothing is safe. 957 return false; 958 } 959 960 //===----------------------------------------------------------------------===// 961 // Optimization Methods 962 //===----------------------------------------------------------------------===// 963 964 /// ShrinkDemandedConstant - Check to see if the specified operand of the 965 /// specified instruction is a constant integer. If so, check to see if there 966 /// are any bits set in the constant that are not demanded. If so, shrink the 967 /// constant and return true. 968 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, 969 const APInt &Demanded) { 970 DebugLoc dl = Op.getDebugLoc(); 971 972 // FIXME: ISD::SELECT, ISD::SELECT_CC 973 switch (Op.getOpcode()) { 974 default: break; 975 case ISD::XOR: 976 case ISD::AND: 977 case ISD::OR: { 978 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 979 if (!C) return false; 980 981 if (Op.getOpcode() == ISD::XOR && 982 (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) 983 return false; 984 985 // if we can expand it to have all bits set, do it 986 if (C->getAPIntValue().intersects(~Demanded)) { 987 EVT VT = Op.getValueType(); 988 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), 989 DAG.getConstant(Demanded & 990 C->getAPIntValue(), 991 VT)); 992 return CombineTo(Op, New); 993 } 994 995 break; 996 } 997 } 998 999 return false; 1000 } 1001 1002 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the 1003 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening 1004 /// cast, but it could be generalized for targets with other types of 1005 /// implicit widening casts. 1006 bool 1007 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, 1008 unsigned BitWidth, 1009 const APInt &Demanded, 1010 DebugLoc dl) { 1011 assert(Op.getNumOperands() == 2 && 1012 "ShrinkDemandedOp only supports binary operators!"); 1013 assert(Op.getNode()->getNumValues() == 1 && 1014 "ShrinkDemandedOp only supports nodes with one result!"); 1015 1016 // Don't do this if the node has another user, which may require the 1017 // full value. 1018 if (!Op.getNode()->hasOneUse()) 1019 return false; 1020 1021 // Search for the smallest integer type with free casts to and from 1022 // Op's type. For expedience, just check power-of-2 integer types. 1023 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1024 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros(); 1025 if (!isPowerOf2_32(SmallVTBits)) 1026 SmallVTBits = NextPowerOf2(SmallVTBits); 1027 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { 1028 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); 1029 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && 1030 TLI.isZExtFree(SmallVT, Op.getValueType())) { 1031 // We found a type with free casts. 1032 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, 1033 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1034 Op.getNode()->getOperand(0)), 1035 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, 1036 Op.getNode()->getOperand(1))); 1037 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); 1038 return CombineTo(Op, Z); 1039 } 1040 } 1041 return false; 1042 } 1043 1044 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the 1045 /// DemandedMask bits of the result of Op are ever used downstream. If we can 1046 /// use this information to simplify Op, create a new simplified DAG node and 1047 /// return true, returning the original and new nodes in Old and New. Otherwise, 1048 /// analyze the expression and return a mask of KnownOne and KnownZero bits for 1049 /// the expression (used to simplify the caller). The KnownZero/One bits may 1050 /// only be accurate for those bits in the DemandedMask. 1051 bool TargetLowering::SimplifyDemandedBits(SDValue Op, 1052 const APInt &DemandedMask, 1053 APInt &KnownZero, 1054 APInt &KnownOne, 1055 TargetLoweringOpt &TLO, 1056 unsigned Depth) const { 1057 unsigned BitWidth = DemandedMask.getBitWidth(); 1058 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth && 1059 "Mask size mismatches value type size!"); 1060 APInt NewMask = DemandedMask; 1061 DebugLoc dl = Op.getDebugLoc(); 1062 1063 // Don't know anything. 1064 KnownZero = KnownOne = APInt(BitWidth, 0); 1065 1066 // Other users may use these bits. 1067 if (!Op.getNode()->hasOneUse()) { 1068 if (Depth != 0) { 1069 // If not at the root, Just compute the KnownZero/KnownOne bits to 1070 // simplify things downstream. 1071 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth); 1072 return false; 1073 } 1074 // If this is the root being simplified, allow it to have multiple uses, 1075 // just set the NewMask to all bits. 1076 NewMask = APInt::getAllOnesValue(BitWidth); 1077 } else if (DemandedMask == 0) { 1078 // Not demanding any bits from Op. 1079 if (Op.getOpcode() != ISD::UNDEF) 1080 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); 1081 return false; 1082 } else if (Depth == 6) { // Limit search depth. 1083 return false; 1084 } 1085 1086 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut; 1087 switch (Op.getOpcode()) { 1088 case ISD::Constant: 1089 // We know all of the bits for a constant! 1090 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask; 1091 KnownZero = ~KnownOne & NewMask; 1092 return false; // Don't fall through, will infinitely loop. 1093 case ISD::AND: 1094 // If the RHS is a constant, check to see if the LHS would be zero without 1095 // using the bits from the RHS. Below, we use knowledge about the RHS to 1096 // simplify the LHS, here we're using information from the LHS to simplify 1097 // the RHS. 1098 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1099 APInt LHSZero, LHSOne; 1100 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, 1101 LHSZero, LHSOne, Depth+1); 1102 // If the LHS already has zeros where RHSC does, this and is dead. 1103 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) 1104 return TLO.CombineTo(Op, Op.getOperand(0)); 1105 // If any of the set bits in the RHS are known zero on the LHS, shrink 1106 // the constant. 1107 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask)) 1108 return true; 1109 } 1110 1111 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1112 KnownOne, TLO, Depth+1)) 1113 return true; 1114 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1115 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, 1116 KnownZero2, KnownOne2, TLO, Depth+1)) 1117 return true; 1118 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1119 1120 // If all of the demanded bits are known one on one side, return the other. 1121 // These bits cannot contribute to the result of the 'and'. 1122 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1123 return TLO.CombineTo(Op, Op.getOperand(0)); 1124 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1125 return TLO.CombineTo(Op, Op.getOperand(1)); 1126 // If all of the demanded bits in the inputs are known zeros, return zero. 1127 if ((NewMask & (KnownZero|KnownZero2)) == NewMask) 1128 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType())); 1129 // If the RHS is a constant, see if we can simplify it. 1130 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) 1131 return true; 1132 // If the operation can be done in a smaller type, do so. 1133 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1134 return true; 1135 1136 // Output known-1 bits are only known if set in both the LHS & RHS. 1137 KnownOne &= KnownOne2; 1138 // Output known-0 are known to be clear if zero in either the LHS | RHS. 1139 KnownZero |= KnownZero2; 1140 break; 1141 case ISD::OR: 1142 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1143 KnownOne, TLO, Depth+1)) 1144 return true; 1145 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1146 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, 1147 KnownZero2, KnownOne2, TLO, Depth+1)) 1148 return true; 1149 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1150 1151 // If all of the demanded bits are known zero on one side, return the other. 1152 // These bits cannot contribute to the result of the 'or'. 1153 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask)) 1154 return TLO.CombineTo(Op, Op.getOperand(0)); 1155 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask)) 1156 return TLO.CombineTo(Op, Op.getOperand(1)); 1157 // If all of the potentially set bits on one side are known to be set on 1158 // the other side, just use the 'other' side. 1159 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) 1160 return TLO.CombineTo(Op, Op.getOperand(0)); 1161 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask)) 1162 return TLO.CombineTo(Op, Op.getOperand(1)); 1163 // If the RHS is a constant, see if we can simplify it. 1164 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1165 return true; 1166 // If the operation can be done in a smaller type, do so. 1167 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1168 return true; 1169 1170 // Output known-0 bits are only known if clear in both the LHS & RHS. 1171 KnownZero &= KnownZero2; 1172 // Output known-1 are known to be set if set in either the LHS | RHS. 1173 KnownOne |= KnownOne2; 1174 break; 1175 case ISD::XOR: 1176 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, 1177 KnownOne, TLO, Depth+1)) 1178 return true; 1179 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1180 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, 1181 KnownOne2, TLO, Depth+1)) 1182 return true; 1183 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1184 1185 // If all of the demanded bits are known zero on one side, return the other. 1186 // These bits cannot contribute to the result of the 'xor'. 1187 if ((KnownZero & NewMask) == NewMask) 1188 return TLO.CombineTo(Op, Op.getOperand(0)); 1189 if ((KnownZero2 & NewMask) == NewMask) 1190 return TLO.CombineTo(Op, Op.getOperand(1)); 1191 // If the operation can be done in a smaller type, do so. 1192 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1193 return true; 1194 1195 // If all of the unknown bits are known to be zero on one side or the other 1196 // (but not both) turn this into an *inclusive* or. 1197 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 1198 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) 1199 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), 1200 Op.getOperand(0), 1201 Op.getOperand(1))); 1202 1203 // Output known-0 bits are known if clear or set in both the LHS & RHS. 1204 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); 1205 // Output known-1 are known to be set if set in only one of the LHS, RHS. 1206 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2); 1207 1208 // If all of the demanded bits on one side are known, and all of the set 1209 // bits on that side are also known to be set on the other side, turn this 1210 // into an AND, as we know the bits will be cleared. 1211 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 1212 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known 1213 if ((KnownOne & KnownOne2) == KnownOne) { 1214 EVT VT = Op.getValueType(); 1215 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); 1216 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, 1217 Op.getOperand(0), ANDC)); 1218 } 1219 } 1220 1221 // If the RHS is a constant, see if we can simplify it. 1222 // for XOR, we prefer to force bits to 1 if they will make a -1. 1223 // if we can't force bits, try to shrink constant 1224 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1225 APInt Expanded = C->getAPIntValue() | (~NewMask); 1226 // if we can expand it to have all bits set, do it 1227 if (Expanded.isAllOnesValue()) { 1228 if (Expanded != C->getAPIntValue()) { 1229 EVT VT = Op.getValueType(); 1230 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), 1231 TLO.DAG.getConstant(Expanded, VT)); 1232 return TLO.CombineTo(Op, New); 1233 } 1234 // if it already has all the bits set, nothing to change 1235 // but don't shrink either! 1236 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) { 1237 return true; 1238 } 1239 } 1240 1241 KnownZero = KnownZeroOut; 1242 KnownOne = KnownOneOut; 1243 break; 1244 case ISD::SELECT: 1245 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, 1246 KnownOne, TLO, Depth+1)) 1247 return true; 1248 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, 1249 KnownOne2, TLO, Depth+1)) 1250 return true; 1251 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1252 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1253 1254 // If the operands are constants, see if we can simplify them. 1255 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1256 return true; 1257 1258 // Only known if known in both the LHS and RHS. 1259 KnownOne &= KnownOne2; 1260 KnownZero &= KnownZero2; 1261 break; 1262 case ISD::SELECT_CC: 1263 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, 1264 KnownOne, TLO, Depth+1)) 1265 return true; 1266 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, 1267 KnownOne2, TLO, Depth+1)) 1268 return true; 1269 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1270 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1271 1272 // If the operands are constants, see if we can simplify them. 1273 if (TLO.ShrinkDemandedConstant(Op, NewMask)) 1274 return true; 1275 1276 // Only known if known in both the LHS and RHS. 1277 KnownOne &= KnownOne2; 1278 KnownZero &= KnownZero2; 1279 break; 1280 case ISD::SHL: 1281 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1282 unsigned ShAmt = SA->getZExtValue(); 1283 SDValue InOp = Op.getOperand(0); 1284 1285 // If the shift count is an invalid immediate, don't do anything. 1286 if (ShAmt >= BitWidth) 1287 break; 1288 1289 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a 1290 // single shift. We can do this if the bottom bits (which are shifted 1291 // out) are never demanded. 1292 if (InOp.getOpcode() == ISD::SRL && 1293 isa<ConstantSDNode>(InOp.getOperand(1))) { 1294 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { 1295 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1296 unsigned Opc = ISD::SHL; 1297 int Diff = ShAmt-C1; 1298 if (Diff < 0) { 1299 Diff = -Diff; 1300 Opc = ISD::SRL; 1301 } 1302 1303 SDValue NewSA = 1304 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1305 EVT VT = Op.getValueType(); 1306 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1307 InOp.getOperand(0), NewSA)); 1308 } 1309 } 1310 1311 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt), 1312 KnownZero, KnownOne, TLO, Depth+1)) 1313 return true; 1314 KnownZero <<= SA->getZExtValue(); 1315 KnownOne <<= SA->getZExtValue(); 1316 // low bits known zero. 1317 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); 1318 } 1319 break; 1320 case ISD::SRL: 1321 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1322 EVT VT = Op.getValueType(); 1323 unsigned ShAmt = SA->getZExtValue(); 1324 unsigned VTSize = VT.getSizeInBits(); 1325 SDValue InOp = Op.getOperand(0); 1326 1327 // If the shift count is an invalid immediate, don't do anything. 1328 if (ShAmt >= BitWidth) 1329 break; 1330 1331 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a 1332 // single shift. We can do this if the top bits (which are shifted out) 1333 // are never demanded. 1334 if (InOp.getOpcode() == ISD::SHL && 1335 isa<ConstantSDNode>(InOp.getOperand(1))) { 1336 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { 1337 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue(); 1338 unsigned Opc = ISD::SRL; 1339 int Diff = ShAmt-C1; 1340 if (Diff < 0) { 1341 Diff = -Diff; 1342 Opc = ISD::SHL; 1343 } 1344 1345 SDValue NewSA = 1346 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); 1347 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, 1348 InOp.getOperand(0), NewSA)); 1349 } 1350 } 1351 1352 // Compute the new bits that are at the top now. 1353 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt), 1354 KnownZero, KnownOne, TLO, Depth+1)) 1355 return true; 1356 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1357 KnownZero = KnownZero.lshr(ShAmt); 1358 KnownOne = KnownOne.lshr(ShAmt); 1359 1360 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1361 KnownZero |= HighBits; // High bits known zero. 1362 } 1363 break; 1364 case ISD::SRA: 1365 // If this is an arithmetic shift right and only the low-bit is set, we can 1366 // always convert this into a logical shr, even if the shift amount is 1367 // variable. The low bit of the shift cannot be an input sign bit unless 1368 // the shift amount is >= the size of the datatype, which is undefined. 1369 if (DemandedMask == 1) 1370 return TLO.CombineTo(Op, 1371 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1372 Op.getOperand(0), Op.getOperand(1))); 1373 1374 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1375 EVT VT = Op.getValueType(); 1376 unsigned ShAmt = SA->getZExtValue(); 1377 1378 // If the shift count is an invalid immediate, don't do anything. 1379 if (ShAmt >= BitWidth) 1380 break; 1381 1382 APInt InDemandedMask = (NewMask << ShAmt); 1383 1384 // If any of the demanded bits are produced by the sign extension, we also 1385 // demand the input sign bit. 1386 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); 1387 if (HighBits.intersects(NewMask)) 1388 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); 1389 1390 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, 1391 KnownZero, KnownOne, TLO, Depth+1)) 1392 return true; 1393 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1394 KnownZero = KnownZero.lshr(ShAmt); 1395 KnownOne = KnownOne.lshr(ShAmt); 1396 1397 // Handle the sign bit, adjusted to where it is now in the mask. 1398 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); 1399 1400 // If the input sign bit is known to be zero, or if none of the top bits 1401 // are demanded, turn this into an unsigned shift right. 1402 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) { 1403 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1404 Op.getOperand(0), 1405 Op.getOperand(1))); 1406 } else if (KnownOne.intersects(SignBit)) { // New bits are known one. 1407 KnownOne |= HighBits; 1408 } 1409 } 1410 break; 1411 case ISD::SIGN_EXTEND_INREG: { 1412 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1413 1414 // Sign extension. Compute the demanded bits in the result that are not 1415 // present in the input. 1416 APInt NewBits = 1417 APInt::getHighBitsSet(BitWidth, 1418 BitWidth - EVT.getScalarType().getSizeInBits()) & 1419 NewMask; 1420 1421 // If none of the extended bits are demanded, eliminate the sextinreg. 1422 if (NewBits == 0) 1423 return TLO.CombineTo(Op, Op.getOperand(0)); 1424 1425 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits()); 1426 InSignBit.zext(BitWidth); 1427 APInt InputDemandedBits = 1428 APInt::getLowBitsSet(BitWidth, 1429 EVT.getScalarType().getSizeInBits()) & 1430 NewMask; 1431 1432 // Since the sign extended bits are demanded, we know that the sign 1433 // bit is demanded. 1434 InputDemandedBits |= InSignBit; 1435 1436 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, 1437 KnownZero, KnownOne, TLO, Depth+1)) 1438 return true; 1439 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1440 1441 // If the sign bit of the input is known set or clear, then we know the 1442 // top bits of the result. 1443 1444 // If the input sign bit is known zero, convert this into a zero extension. 1445 if (KnownZero.intersects(InSignBit)) 1446 return TLO.CombineTo(Op, 1447 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT)); 1448 1449 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set 1450 KnownOne |= NewBits; 1451 KnownZero &= ~NewBits; 1452 } else { // Input sign bit unknown 1453 KnownZero &= ~NewBits; 1454 KnownOne &= ~NewBits; 1455 } 1456 break; 1457 } 1458 case ISD::ZERO_EXTEND: { 1459 unsigned OperandBitWidth = 1460 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1461 APInt InMask = NewMask; 1462 InMask.trunc(OperandBitWidth); 1463 1464 // If none of the top bits are demanded, convert this into an any_extend. 1465 APInt NewBits = 1466 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; 1467 if (!NewBits.intersects(NewMask)) 1468 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1469 Op.getValueType(), 1470 Op.getOperand(0))); 1471 1472 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1473 KnownZero, KnownOne, TLO, Depth+1)) 1474 return true; 1475 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1476 KnownZero.zext(BitWidth); 1477 KnownOne.zext(BitWidth); 1478 KnownZero |= NewBits; 1479 break; 1480 } 1481 case ISD::SIGN_EXTEND: { 1482 EVT InVT = Op.getOperand(0).getValueType(); 1483 unsigned InBits = InVT.getScalarType().getSizeInBits(); 1484 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); 1485 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); 1486 APInt NewBits = ~InMask & NewMask; 1487 1488 // If none of the top bits are demanded, convert this into an any_extend. 1489 if (NewBits == 0) 1490 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, 1491 Op.getValueType(), 1492 Op.getOperand(0))); 1493 1494 // Since some of the sign extended bits are demanded, we know that the sign 1495 // bit is demanded. 1496 APInt InDemandedBits = InMask & NewMask; 1497 InDemandedBits |= InSignBit; 1498 InDemandedBits.trunc(InBits); 1499 1500 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, 1501 KnownOne, TLO, Depth+1)) 1502 return true; 1503 KnownZero.zext(BitWidth); 1504 KnownOne.zext(BitWidth); 1505 1506 // If the sign bit is known zero, convert this to a zero extend. 1507 if (KnownZero.intersects(InSignBit)) 1508 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, 1509 Op.getValueType(), 1510 Op.getOperand(0))); 1511 1512 // If the sign bit is known one, the top bits match. 1513 if (KnownOne.intersects(InSignBit)) { 1514 KnownOne |= NewBits; 1515 KnownZero &= ~NewBits; 1516 } else { // Otherwise, top bits aren't known. 1517 KnownOne &= ~NewBits; 1518 KnownZero &= ~NewBits; 1519 } 1520 break; 1521 } 1522 case ISD::ANY_EXTEND: { 1523 unsigned OperandBitWidth = 1524 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1525 APInt InMask = NewMask; 1526 InMask.trunc(OperandBitWidth); 1527 if (SimplifyDemandedBits(Op.getOperand(0), InMask, 1528 KnownZero, KnownOne, TLO, Depth+1)) 1529 return true; 1530 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1531 KnownZero.zext(BitWidth); 1532 KnownOne.zext(BitWidth); 1533 break; 1534 } 1535 case ISD::TRUNCATE: { 1536 // Simplify the input, using demanded bit information, and compute the known 1537 // zero/one bits live out. 1538 unsigned OperandBitWidth = 1539 Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); 1540 APInt TruncMask = NewMask; 1541 TruncMask.zext(OperandBitWidth); 1542 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, 1543 KnownZero, KnownOne, TLO, Depth+1)) 1544 return true; 1545 KnownZero.trunc(BitWidth); 1546 KnownOne.trunc(BitWidth); 1547 1548 // If the input is only used by this truncate, see if we can shrink it based 1549 // on the known demanded bits. 1550 if (Op.getOperand(0).getNode()->hasOneUse()) { 1551 SDValue In = Op.getOperand(0); 1552 switch (In.getOpcode()) { 1553 default: break; 1554 case ISD::SRL: 1555 // Shrink SRL by a constant if none of the high bits shifted in are 1556 // demanded. 1557 if (TLO.LegalTypes() && 1558 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1559 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is 1560 // undesirable. 1561 break; 1562 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1)); 1563 if (!ShAmt) 1564 break; 1565 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, 1566 OperandBitWidth - BitWidth); 1567 HighBits = HighBits.lshr(ShAmt->getZExtValue()); 1568 HighBits.trunc(BitWidth); 1569 1570 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { 1571 // None of the shifted in bits are needed. Add a truncate of the 1572 // shift input, then shift it. 1573 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, 1574 Op.getValueType(), 1575 In.getOperand(0)); 1576 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, 1577 Op.getValueType(), 1578 NewTrunc, 1579 In.getOperand(1))); 1580 } 1581 break; 1582 } 1583 } 1584 1585 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1586 break; 1587 } 1588 case ISD::AssertZext: { 1589 // Demand all the bits of the input that are demanded in the output. 1590 // The low bits are obvious; the high bits are demanded because we're 1591 // asserting that they're zero here. 1592 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, 1593 KnownZero, KnownOne, TLO, Depth+1)) 1594 return true; 1595 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1596 1597 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); 1598 APInt InMask = APInt::getLowBitsSet(BitWidth, 1599 VT.getSizeInBits()); 1600 KnownZero |= ~InMask & NewMask; 1601 break; 1602 } 1603 case ISD::BIT_CONVERT: 1604 #if 0 1605 // If this is an FP->Int bitcast and if the sign bit is the only thing that 1606 // is demanded, turn this into a FGETSIGN. 1607 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && 1608 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && 1609 !MVT::isVector(Op.getOperand(0).getValueType())) { 1610 // Only do this xform if FGETSIGN is valid or if before legalize. 1611 if (!TLO.AfterLegalize || 1612 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { 1613 // Make a FGETSIGN + SHL to move the sign bit into the appropriate 1614 // place. We expect the SHL to be eliminated by other optimizations. 1615 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(), 1616 Op.getOperand(0)); 1617 unsigned ShVal = Op.getValueType().getSizeInBits()-1; 1618 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); 1619 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(), 1620 Sign, ShAmt)); 1621 } 1622 } 1623 #endif 1624 break; 1625 case ISD::ADD: 1626 case ISD::MUL: 1627 case ISD::SUB: { 1628 // Add, Sub, and Mul don't demand any bits in positions beyond that 1629 // of the highest bit demanded of them. 1630 APInt LoMask = APInt::getLowBitsSet(BitWidth, 1631 BitWidth - NewMask.countLeadingZeros()); 1632 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, 1633 KnownOne2, TLO, Depth+1)) 1634 return true; 1635 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, 1636 KnownOne2, TLO, Depth+1)) 1637 return true; 1638 // See if the operation should be performed at a smaller bit width. 1639 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) 1640 return true; 1641 } 1642 // FALL THROUGH 1643 default: 1644 // Just use ComputeMaskedBits to compute output bits. 1645 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth); 1646 break; 1647 } 1648 1649 // If we know the value of all of the demanded bits, return this as a 1650 // constant. 1651 if ((NewMask & (KnownZero|KnownOne)) == NewMask) 1652 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType())); 1653 1654 return false; 1655 } 1656 1657 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 1658 /// in Mask are known to be either zero or one and return them in the 1659 /// KnownZero/KnownOne bitsets. 1660 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1661 const APInt &Mask, 1662 APInt &KnownZero, 1663 APInt &KnownOne, 1664 const SelectionDAG &DAG, 1665 unsigned Depth) const { 1666 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1667 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1668 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1669 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1670 "Should use MaskedValueIsZero if you don't know whether Op" 1671 " is a target node!"); 1672 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1673 } 1674 1675 /// ComputeNumSignBitsForTargetNode - This method can be implemented by 1676 /// targets that want to expose additional information about sign bits to the 1677 /// DAG Combiner. 1678 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 1679 unsigned Depth) const { 1680 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END || 1681 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN || 1682 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN || 1683 Op.getOpcode() == ISD::INTRINSIC_VOID) && 1684 "Should use ComputeNumSignBits if you don't know whether Op" 1685 " is a target node!"); 1686 return 1; 1687 } 1688 1689 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly 1690 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to 1691 /// determine which bit is set. 1692 /// 1693 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { 1694 // A left-shift of a constant one will have exactly one bit set, because 1695 // shifting the bit off the end is undefined. 1696 if (Val.getOpcode() == ISD::SHL) 1697 if (ConstantSDNode *C = 1698 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1699 if (C->getAPIntValue() == 1) 1700 return true; 1701 1702 // Similarly, a right-shift of a constant sign-bit will have exactly 1703 // one bit set. 1704 if (Val.getOpcode() == ISD::SRL) 1705 if (ConstantSDNode *C = 1706 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0))) 1707 if (C->getAPIntValue().isSignBit()) 1708 return true; 1709 1710 // More could be done here, though the above checks are enough 1711 // to handle some common cases. 1712 1713 // Fall back to ComputeMaskedBits to catch other known cases. 1714 EVT OpVT = Val.getValueType(); 1715 unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); 1716 APInt Mask = APInt::getAllOnesValue(BitWidth); 1717 APInt KnownZero, KnownOne; 1718 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne); 1719 return (KnownZero.countPopulation() == BitWidth - 1) && 1720 (KnownOne.countPopulation() == 1); 1721 } 1722 1723 /// SimplifySetCC - Try to simplify a setcc built with the specified operands 1724 /// and cc. If it is unable to simplify it, return a null SDValue. 1725 SDValue 1726 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, 1727 ISD::CondCode Cond, bool foldBooleans, 1728 DAGCombinerInfo &DCI, DebugLoc dl) const { 1729 SelectionDAG &DAG = DCI.DAG; 1730 LLVMContext &Context = *DAG.getContext(); 1731 1732 // These setcc operations always fold. 1733 switch (Cond) { 1734 default: break; 1735 case ISD::SETFALSE: 1736 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1737 case ISD::SETTRUE: 1738 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1739 } 1740 1741 if (isa<ConstantSDNode>(N0.getNode())) { 1742 // Ensure that the constant occurs on the RHS, and fold constant 1743 // comparisons. 1744 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 1745 } 1746 1747 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) { 1748 const APInt &C1 = N1C->getAPIntValue(); 1749 1750 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an 1751 // equality comparison, then we're just comparing whether X itself is 1752 // zero. 1753 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && 1754 N0.getOperand(0).getOpcode() == ISD::CTLZ && 1755 N0.getOperand(1).getOpcode() == ISD::Constant) { 1756 const APInt &ShAmt 1757 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1758 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1759 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { 1760 if ((C1 == 0) == (Cond == ISD::SETEQ)) { 1761 // (srl (ctlz x), 5) == 0 -> X != 0 1762 // (srl (ctlz x), 5) != 1 -> X != 0 1763 Cond = ISD::SETNE; 1764 } else { 1765 // (srl (ctlz x), 5) != 0 -> X == 0 1766 // (srl (ctlz x), 5) == 1 -> X == 0 1767 Cond = ISD::SETEQ; 1768 } 1769 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 1770 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), 1771 Zero, Cond); 1772 } 1773 } 1774 1775 // If the LHS is '(and load, const)', the RHS is 0, 1776 // the test is for equality or unsigned, and all 1 bits of the const are 1777 // in the same partial word, see if we can shorten the load. 1778 if (DCI.isBeforeLegalize() && 1779 N0.getOpcode() == ISD::AND && C1 == 0 && 1780 N0.getNode()->hasOneUse() && 1781 isa<LoadSDNode>(N0.getOperand(0)) && 1782 N0.getOperand(0).getNode()->hasOneUse() && 1783 isa<ConstantSDNode>(N0.getOperand(1))) { 1784 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0)); 1785 APInt bestMask; 1786 unsigned bestWidth = 0, bestOffset = 0; 1787 if (!Lod->isVolatile() && Lod->isUnindexed()) { 1788 unsigned origWidth = N0.getValueType().getSizeInBits(); 1789 unsigned maskWidth = origWidth; 1790 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to 1791 // 8 bits, but have to be careful... 1792 if (Lod->getExtensionType() != ISD::NON_EXTLOAD) 1793 origWidth = Lod->getMemoryVT().getSizeInBits(); 1794 const APInt &Mask = 1795 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1796 for (unsigned width = origWidth / 2; width>=8; width /= 2) { 1797 APInt newMask = APInt::getLowBitsSet(maskWidth, width); 1798 for (unsigned offset=0; offset<origWidth/width; offset++) { 1799 if ((newMask & Mask) == Mask) { 1800 if (!TD->isLittleEndian()) 1801 bestOffset = (origWidth/width - offset - 1) * (width/8); 1802 else 1803 bestOffset = (uint64_t)offset * (width/8); 1804 bestMask = Mask.lshr(offset * (width/8) * 8); 1805 bestWidth = width; 1806 break; 1807 } 1808 newMask = newMask << width; 1809 } 1810 } 1811 } 1812 if (bestWidth) { 1813 EVT newVT = EVT::getIntegerVT(Context, bestWidth); 1814 if (newVT.isRound()) { 1815 EVT PtrType = Lod->getOperand(1).getValueType(); 1816 SDValue Ptr = Lod->getBasePtr(); 1817 if (bestOffset != 0) 1818 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), 1819 DAG.getConstant(bestOffset, PtrType)); 1820 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset); 1821 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr, 1822 Lod->getSrcValue(), 1823 Lod->getSrcValueOffset() + bestOffset, 1824 false, false, NewAlign); 1825 return DAG.getSetCC(dl, VT, 1826 DAG.getNode(ISD::AND, dl, newVT, NewLoad, 1827 DAG.getConstant(bestMask.trunc(bestWidth), 1828 newVT)), 1829 DAG.getConstant(0LL, newVT), Cond); 1830 } 1831 } 1832 } 1833 1834 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1835 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1836 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits(); 1837 1838 // If the comparison constant has bits in the upper part, the 1839 // zero-extended value could never match. 1840 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(), 1841 C1.getBitWidth() - InSize))) { 1842 switch (Cond) { 1843 case ISD::SETUGT: 1844 case ISD::SETUGE: 1845 case ISD::SETEQ: return DAG.getConstant(0, VT); 1846 case ISD::SETULT: 1847 case ISD::SETULE: 1848 case ISD::SETNE: return DAG.getConstant(1, VT); 1849 case ISD::SETGT: 1850 case ISD::SETGE: 1851 // True if the sign bit of C1 is set. 1852 return DAG.getConstant(C1.isNegative(), VT); 1853 case ISD::SETLT: 1854 case ISD::SETLE: 1855 // True if the sign bit of C1 isn't set. 1856 return DAG.getConstant(C1.isNonNegative(), VT); 1857 default: 1858 break; 1859 } 1860 } 1861 1862 // Otherwise, we can perform the comparison with the low bits. 1863 switch (Cond) { 1864 case ISD::SETEQ: 1865 case ISD::SETNE: 1866 case ISD::SETUGT: 1867 case ISD::SETUGE: 1868 case ISD::SETULT: 1869 case ISD::SETULE: { 1870 EVT newVT = N0.getOperand(0).getValueType(); 1871 if (DCI.isBeforeLegalizeOps() || 1872 (isOperationLegal(ISD::SETCC, newVT) && 1873 getCondCodeAction(Cond, newVT)==Legal)) 1874 return DAG.getSetCC(dl, VT, N0.getOperand(0), 1875 DAG.getConstant(APInt(C1).trunc(InSize), newVT), 1876 Cond); 1877 break; 1878 } 1879 default: 1880 break; // todo, be more careful with signed comparisons 1881 } 1882 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1883 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1884 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1885 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); 1886 EVT ExtDstTy = N0.getValueType(); 1887 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); 1888 1889 // If the extended part has any inconsistent bits, it cannot ever 1890 // compare equal. In other words, they have to be all ones or all 1891 // zeros. 1892 APInt ExtBits = 1893 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits); 1894 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1895 return DAG.getConstant(Cond == ISD::SETNE, VT); 1896 1897 SDValue ZextOp; 1898 EVT Op0Ty = N0.getOperand(0).getValueType(); 1899 if (Op0Ty == ExtSrcTy) { 1900 ZextOp = N0.getOperand(0); 1901 } else { 1902 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); 1903 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), 1904 DAG.getConstant(Imm, Op0Ty)); 1905 } 1906 if (!DCI.isCalledByLegalizer()) 1907 DCI.AddToWorklist(ZextOp.getNode()); 1908 // Otherwise, make this a use of a zext. 1909 return DAG.getSetCC(dl, VT, ZextOp, 1910 DAG.getConstant(C1 & APInt::getLowBitsSet( 1911 ExtDstTyBits, 1912 ExtSrcTyBits), 1913 ExtDstTy), 1914 Cond); 1915 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && 1916 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1917 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC 1918 if (N0.getOpcode() == ISD::SETCC && 1919 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { 1920 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); 1921 if (TrueWhenTrue) 1922 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); 1923 // Invert the condition. 1924 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 1925 CC = ISD::getSetCCInverse(CC, 1926 N0.getOperand(0).getValueType().isInteger()); 1927 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); 1928 } 1929 1930 if ((N0.getOpcode() == ISD::XOR || 1931 (N0.getOpcode() == ISD::AND && 1932 N0.getOperand(0).getOpcode() == ISD::XOR && 1933 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 1934 isa<ConstantSDNode>(N0.getOperand(1)) && 1935 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) { 1936 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We 1937 // can only do this if the top bits are known zero. 1938 unsigned BitWidth = N0.getValueSizeInBits(); 1939 if (DAG.MaskedValueIsZero(N0, 1940 APInt::getHighBitsSet(BitWidth, 1941 BitWidth-1))) { 1942 // Okay, get the un-inverted input value. 1943 SDValue Val; 1944 if (N0.getOpcode() == ISD::XOR) 1945 Val = N0.getOperand(0); 1946 else { 1947 assert(N0.getOpcode() == ISD::AND && 1948 N0.getOperand(0).getOpcode() == ISD::XOR); 1949 // ((X^1)&1)^1 -> X & 1 1950 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), 1951 N0.getOperand(0).getOperand(0), 1952 N0.getOperand(1)); 1953 } 1954 1955 return DAG.getSetCC(dl, VT, Val, N1, 1956 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1957 } 1958 } else if (N1C->getAPIntValue() == 1 && 1959 (VT == MVT::i1 || 1960 getBooleanContents() == ZeroOrOneBooleanContent)) { 1961 SDValue Op0 = N0; 1962 if (Op0.getOpcode() == ISD::TRUNCATE) 1963 Op0 = Op0.getOperand(0); 1964 1965 if ((Op0.getOpcode() == ISD::XOR) && 1966 Op0.getOperand(0).getOpcode() == ISD::SETCC && 1967 Op0.getOperand(1).getOpcode() == ISD::SETCC) { 1968 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc) 1969 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; 1970 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), 1971 Cond); 1972 } else if (Op0.getOpcode() == ISD::AND && 1973 isa<ConstantSDNode>(Op0.getOperand(1)) && 1974 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { 1975 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. 1976 if (Op0.getValueType().bitsGT(VT)) 1977 Op0 = DAG.getNode(ISD::AND, dl, VT, 1978 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), 1979 DAG.getConstant(1, VT)); 1980 else if (Op0.getValueType().bitsLT(VT)) 1981 Op0 = DAG.getNode(ISD::AND, dl, VT, 1982 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), 1983 DAG.getConstant(1, VT)); 1984 1985 return DAG.getSetCC(dl, VT, Op0, 1986 DAG.getConstant(0, Op0.getValueType()), 1987 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 1988 } 1989 } 1990 } 1991 1992 APInt MinVal, MaxVal; 1993 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits(); 1994 if (ISD::isSignedIntSetCC(Cond)) { 1995 MinVal = APInt::getSignedMinValue(OperandBitSize); 1996 MaxVal = APInt::getSignedMaxValue(OperandBitSize); 1997 } else { 1998 MinVal = APInt::getMinValue(OperandBitSize); 1999 MaxVal = APInt::getMaxValue(OperandBitSize); 2000 } 2001 2002 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2003 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2004 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2005 // X >= C0 --> X > (C0-1) 2006 return DAG.getSetCC(dl, VT, N0, 2007 DAG.getConstant(C1-1, N1.getValueType()), 2008 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2009 } 2010 2011 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2012 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2013 // X <= C0 --> X < (C0+1) 2014 return DAG.getSetCC(dl, VT, N0, 2015 DAG.getConstant(C1+1, N1.getValueType()), 2016 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2017 } 2018 2019 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2020 return DAG.getConstant(0, VT); // X < MIN --> false 2021 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) 2022 return DAG.getConstant(1, VT); // X >= MIN --> true 2023 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) 2024 return DAG.getConstant(0, VT); // X > MAX --> false 2025 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) 2026 return DAG.getConstant(1, VT); // X <= MAX --> true 2027 2028 // Canonicalize setgt X, Min --> setne X, Min 2029 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2030 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2031 // Canonicalize setlt X, Max --> setne X, Max 2032 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2033 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); 2034 2035 // If we have setult X, 1, turn it into seteq X, 0 2036 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2037 return DAG.getSetCC(dl, VT, N0, 2038 DAG.getConstant(MinVal, N0.getValueType()), 2039 ISD::SETEQ); 2040 // If we have setugt X, Max-1, turn it into seteq X, Max 2041 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2042 return DAG.getSetCC(dl, VT, N0, 2043 DAG.getConstant(MaxVal, N0.getValueType()), 2044 ISD::SETEQ); 2045 2046 // If we have "setcc X, C0", check to see if we can shrink the immediate 2047 // by changing cc. 2048 2049 // SETUGT X, SINTMAX -> SETLT X, 0 2050 if (Cond == ISD::SETUGT && 2051 C1 == APInt::getSignedMaxValue(OperandBitSize)) 2052 return DAG.getSetCC(dl, VT, N0, 2053 DAG.getConstant(0, N1.getValueType()), 2054 ISD::SETLT); 2055 2056 // SETULT X, SINTMIN -> SETGT X, -1 2057 if (Cond == ISD::SETULT && 2058 C1 == APInt::getSignedMinValue(OperandBitSize)) { 2059 SDValue ConstMinusOne = 2060 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), 2061 N1.getValueType()); 2062 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); 2063 } 2064 2065 // Fold bit comparisons when we can. 2066 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2067 (VT == N0.getValueType() || 2068 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) && 2069 N0.getOpcode() == ISD::AND) 2070 if (ConstantSDNode *AndRHS = 2071 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2072 EVT ShiftTy = DCI.isBeforeLegalize() ? 2073 getPointerTy() : getShiftAmountTy(); 2074 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2075 // Perform the xform if the AND RHS is a single bit. 2076 if (AndRHS->getAPIntValue().isPowerOf2()) { 2077 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2078 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2079 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy))); 2080 } 2081 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { 2082 // (X & 8) == 8 --> (X & 8) >> 3 2083 // Perform the xform if C1 is a single bit. 2084 if (C1.isPowerOf2()) { 2085 return DAG.getNode(ISD::TRUNCATE, dl, VT, 2086 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, 2087 DAG.getConstant(C1.logBase2(), ShiftTy))); 2088 } 2089 } 2090 } 2091 } 2092 2093 if (isa<ConstantFPSDNode>(N0.getNode())) { 2094 // Constant fold or commute setcc. 2095 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); 2096 if (O.getNode()) return O; 2097 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) { 2098 // If the RHS of an FP comparison is a constant, simplify it away in 2099 // some cases. 2100 if (CFP->getValueAPF().isNaN()) { 2101 // If an operand is known to be a nan, we can fold it. 2102 switch (ISD::getUnorderedFlavor(Cond)) { 2103 default: llvm_unreachable("Unknown flavor!"); 2104 case 0: // Known false. 2105 return DAG.getConstant(0, VT); 2106 case 1: // Known true. 2107 return DAG.getConstant(1, VT); 2108 case 2: // Undefined. 2109 return DAG.getUNDEF(VT); 2110 } 2111 } 2112 2113 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the 2114 // constant if knowing that the operand is non-nan is enough. We prefer to 2115 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to 2116 // materialize 0.0. 2117 if (Cond == ISD::SETO || Cond == ISD::SETUO) 2118 return DAG.getSetCC(dl, VT, N0, N0, Cond); 2119 2120 // If the condition is not legal, see if we can find an equivalent one 2121 // which is legal. 2122 if (!isCondCodeLegal(Cond, N0.getValueType())) { 2123 // If the comparison was an awkward floating-point == or != and one of 2124 // the comparison operands is infinity or negative infinity, convert the 2125 // condition to a less-awkward <= or >=. 2126 if (CFP->getValueAPF().isInfinity()) { 2127 if (CFP->getValueAPF().isNegative()) { 2128 if (Cond == ISD::SETOEQ && 2129 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2130 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); 2131 if (Cond == ISD::SETUEQ && 2132 isCondCodeLegal(ISD::SETOLE, N0.getValueType())) 2133 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE); 2134 if (Cond == ISD::SETUNE && 2135 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2136 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT); 2137 if (Cond == ISD::SETONE && 2138 isCondCodeLegal(ISD::SETUGT, N0.getValueType())) 2139 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT); 2140 } else { 2141 if (Cond == ISD::SETOEQ && 2142 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2143 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); 2144 if (Cond == ISD::SETUEQ && 2145 isCondCodeLegal(ISD::SETOGE, N0.getValueType())) 2146 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE); 2147 if (Cond == ISD::SETUNE && 2148 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2149 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT); 2150 if (Cond == ISD::SETONE && 2151 isCondCodeLegal(ISD::SETULT, N0.getValueType())) 2152 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT); 2153 } 2154 } 2155 } 2156 } 2157 2158 if (N0 == N1) { 2159 // We can always fold X == X for integer setcc's. 2160 if (N0.getValueType().isInteger()) 2161 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2162 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2163 if (UOF == 2) // FP operators that are undefined on NaNs. 2164 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2165 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2166 return DAG.getConstant(UOF, VT); 2167 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2168 // if it is not already. 2169 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2170 if (NewCond != Cond) 2171 return DAG.getSetCC(dl, VT, N0, N1, NewCond); 2172 } 2173 2174 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2175 N0.getValueType().isInteger()) { 2176 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2177 N0.getOpcode() == ISD::XOR) { 2178 // Simplify (X+Y) == (X+Z) --> Y == Z 2179 if (N0.getOpcode() == N1.getOpcode()) { 2180 if (N0.getOperand(0) == N1.getOperand(0)) 2181 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond); 2182 if (N0.getOperand(1) == N1.getOperand(1)) 2183 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond); 2184 if (DAG.isCommutativeBinOp(N0.getOpcode())) { 2185 // If X op Y == Y op X, try other combinations. 2186 if (N0.getOperand(0) == N1.getOperand(1)) 2187 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0), 2188 Cond); 2189 if (N0.getOperand(1) == N1.getOperand(0)) 2190 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1), 2191 Cond); 2192 } 2193 } 2194 2195 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2196 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2197 // Turn (X+C1) == C2 --> X == C2-C1 2198 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { 2199 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2200 DAG.getConstant(RHSC->getAPIntValue()- 2201 LHSR->getAPIntValue(), 2202 N0.getValueType()), Cond); 2203 } 2204 2205 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2206 if (N0.getOpcode() == ISD::XOR) 2207 // If we know that all of the inverted bits are zero, don't bother 2208 // performing the inversion. 2209 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) 2210 return 2211 DAG.getSetCC(dl, VT, N0.getOperand(0), 2212 DAG.getConstant(LHSR->getAPIntValue() ^ 2213 RHSC->getAPIntValue(), 2214 N0.getValueType()), 2215 Cond); 2216 } 2217 2218 // Turn (C1-X) == C2 --> X == C1-C2 2219 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2220 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2221 return 2222 DAG.getSetCC(dl, VT, N0.getOperand(1), 2223 DAG.getConstant(SUBC->getAPIntValue() - 2224 RHSC->getAPIntValue(), 2225 N0.getValueType()), 2226 Cond); 2227 } 2228 } 2229 } 2230 2231 // Simplify (X+Z) == X --> Z == 0 2232 if (N0.getOperand(0) == N1) 2233 return DAG.getSetCC(dl, VT, N0.getOperand(1), 2234 DAG.getConstant(0, N0.getValueType()), Cond); 2235 if (N0.getOperand(1) == N1) { 2236 if (DAG.isCommutativeBinOp(N0.getOpcode())) 2237 return DAG.getSetCC(dl, VT, N0.getOperand(0), 2238 DAG.getConstant(0, N0.getValueType()), Cond); 2239 else if (N0.getNode()->hasOneUse()) { 2240 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2241 // (Z-X) == X --> Z == X<<1 2242 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), 2243 N1, 2244 DAG.getConstant(1, getShiftAmountTy())); 2245 if (!DCI.isCalledByLegalizer()) 2246 DCI.AddToWorklist(SH.getNode()); 2247 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond); 2248 } 2249 } 2250 } 2251 2252 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2253 N1.getOpcode() == ISD::XOR) { 2254 // Simplify X == (X+Z) --> Z == 0 2255 if (N1.getOperand(0) == N0) { 2256 return DAG.getSetCC(dl, VT, N1.getOperand(1), 2257 DAG.getConstant(0, N1.getValueType()), Cond); 2258 } else if (N1.getOperand(1) == N0) { 2259 if (DAG.isCommutativeBinOp(N1.getOpcode())) { 2260 return DAG.getSetCC(dl, VT, N1.getOperand(0), 2261 DAG.getConstant(0, N1.getValueType()), Cond); 2262 } else if (N1.getNode()->hasOneUse()) { 2263 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2264 // X == (Z-X) --> X<<1 == Z 2265 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0, 2266 DAG.getConstant(1, getShiftAmountTy())); 2267 if (!DCI.isCalledByLegalizer()) 2268 DCI.AddToWorklist(SH.getNode()); 2269 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond); 2270 } 2271 } 2272 } 2273 2274 // Simplify x&y == y to x&y != 0 if y has exactly one bit set. 2275 // Note that where y is variable and is known to have at most 2276 // one bit set (for example, if it is z&1) we cannot do this; 2277 // the expressions are not equivalent when y==0. 2278 if (N0.getOpcode() == ISD::AND) 2279 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) { 2280 if (ValueHasExactlyOneBitSet(N1, DAG)) { 2281 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2282 SDValue Zero = DAG.getConstant(0, N1.getValueType()); 2283 return DAG.getSetCC(dl, VT, N0, Zero, Cond); 2284 } 2285 } 2286 if (N1.getOpcode() == ISD::AND) 2287 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) { 2288 if (ValueHasExactlyOneBitSet(N0, DAG)) { 2289 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true); 2290 SDValue Zero = DAG.getConstant(0, N0.getValueType()); 2291 return DAG.getSetCC(dl, VT, N1, Zero, Cond); 2292 } 2293 } 2294 } 2295 2296 // Fold away ALL boolean setcc's. 2297 SDValue Temp; 2298 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2299 switch (Cond) { 2300 default: llvm_unreachable("Unknown integer setcc!"); 2301 case ISD::SETEQ: // X == Y -> ~(X^Y) 2302 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2303 N0 = DAG.getNOT(dl, Temp, MVT::i1); 2304 if (!DCI.isCalledByLegalizer()) 2305 DCI.AddToWorklist(Temp.getNode()); 2306 break; 2307 case ISD::SETNE: // X != Y --> (X^Y) 2308 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); 2309 break; 2310 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y 2311 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y 2312 Temp = DAG.getNOT(dl, N0, MVT::i1); 2313 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); 2314 if (!DCI.isCalledByLegalizer()) 2315 DCI.AddToWorklist(Temp.getNode()); 2316 break; 2317 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 2318 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X 2319 Temp = DAG.getNOT(dl, N1, MVT::i1); 2320 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); 2321 if (!DCI.isCalledByLegalizer()) 2322 DCI.AddToWorklist(Temp.getNode()); 2323 break; 2324 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y 2325 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y 2326 Temp = DAG.getNOT(dl, N0, MVT::i1); 2327 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); 2328 if (!DCI.isCalledByLegalizer()) 2329 DCI.AddToWorklist(Temp.getNode()); 2330 break; 2331 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X 2332 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X 2333 Temp = DAG.getNOT(dl, N1, MVT::i1); 2334 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); 2335 break; 2336 } 2337 if (VT != MVT::i1) { 2338 if (!DCI.isCalledByLegalizer()) 2339 DCI.AddToWorklist(N0.getNode()); 2340 // FIXME: If running after legalize, we probably can't do this. 2341 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); 2342 } 2343 return N0; 2344 } 2345 2346 // Could not fold it. 2347 return SDValue(); 2348 } 2349 2350 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 2351 /// node is a GlobalAddress + offset. 2352 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 2353 int64_t &Offset) const { 2354 if (isa<GlobalAddressSDNode>(N)) { 2355 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N); 2356 GA = GASD->getGlobal(); 2357 Offset += GASD->getOffset(); 2358 return true; 2359 } 2360 2361 if (N->getOpcode() == ISD::ADD) { 2362 SDValue N1 = N->getOperand(0); 2363 SDValue N2 = N->getOperand(1); 2364 if (isGAPlusOffset(N1.getNode(), GA, Offset)) { 2365 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); 2366 if (V) { 2367 Offset += V->getSExtValue(); 2368 return true; 2369 } 2370 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { 2371 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1); 2372 if (V) { 2373 Offset += V->getSExtValue(); 2374 return true; 2375 } 2376 } 2377 } 2378 return false; 2379 } 2380 2381 2382 SDValue TargetLowering:: 2383 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 2384 // Default implementation: no optimization. 2385 return SDValue(); 2386 } 2387 2388 //===----------------------------------------------------------------------===// 2389 // Inline Assembler Implementation Methods 2390 //===----------------------------------------------------------------------===// 2391 2392 2393 TargetLowering::ConstraintType 2394 TargetLowering::getConstraintType(const std::string &Constraint) const { 2395 // FIXME: lots more standard ones to handle. 2396 if (Constraint.size() == 1) { 2397 switch (Constraint[0]) { 2398 default: break; 2399 case 'r': return C_RegisterClass; 2400 case 'm': // memory 2401 case 'o': // offsetable 2402 case 'V': // not offsetable 2403 return C_Memory; 2404 case 'i': // Simple Integer or Relocatable Constant 2405 case 'n': // Simple Integer 2406 case 's': // Relocatable Constant 2407 case 'X': // Allow ANY value. 2408 case 'I': // Target registers. 2409 case 'J': 2410 case 'K': 2411 case 'L': 2412 case 'M': 2413 case 'N': 2414 case 'O': 2415 case 'P': 2416 return C_Other; 2417 } 2418 } 2419 2420 if (Constraint.size() > 1 && Constraint[0] == '{' && 2421 Constraint[Constraint.size()-1] == '}') 2422 return C_Register; 2423 return C_Unknown; 2424 } 2425 2426 /// LowerXConstraint - try to replace an X constraint, which matches anything, 2427 /// with another that has more specific requirements based on the type of the 2428 /// corresponding operand. 2429 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ 2430 if (ConstraintVT.isInteger()) 2431 return "r"; 2432 if (ConstraintVT.isFloatingPoint()) 2433 return "f"; // works for many targets 2434 return 0; 2435 } 2436 2437 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2438 /// vector. If it is invalid, don't add anything to Ops. 2439 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2440 char ConstraintLetter, 2441 std::vector<SDValue> &Ops, 2442 SelectionDAG &DAG) const { 2443 switch (ConstraintLetter) { 2444 default: break; 2445 case 'X': // Allows any operand; labels (basic block) use this. 2446 if (Op.getOpcode() == ISD::BasicBlock) { 2447 Ops.push_back(Op); 2448 return; 2449 } 2450 // fall through 2451 case 'i': // Simple Integer or Relocatable Constant 2452 case 'n': // Simple Integer 2453 case 's': { // Relocatable Constant 2454 // These operands are interested in values of the form (GV+C), where C may 2455 // be folded in as an offset of GV, or it may be explicitly added. Also, it 2456 // is possible and fine if either GV or C are missing. 2457 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2458 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op); 2459 2460 // If we have "(add GV, C)", pull out GV/C 2461 if (Op.getOpcode() == ISD::ADD) { 2462 C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 2463 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0)); 2464 if (C == 0 || GA == 0) { 2465 C = dyn_cast<ConstantSDNode>(Op.getOperand(0)); 2466 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1)); 2467 } 2468 if (C == 0 || GA == 0) 2469 C = 0, GA = 0; 2470 } 2471 2472 // If we find a valid operand, map to the TargetXXX version so that the 2473 // value itself doesn't get selected. 2474 if (GA) { // Either &GV or &GV+C 2475 if (ConstraintLetter != 'n') { 2476 int64_t Offs = GA->getOffset(); 2477 if (C) Offs += C->getZExtValue(); 2478 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), 2479 C->getDebugLoc(), 2480 Op.getValueType(), Offs)); 2481 return; 2482 } 2483 } 2484 if (C) { // just C, no GV. 2485 // Simple constants are not allowed for 's'. 2486 if (ConstraintLetter != 's') { 2487 // gcc prints these as sign extended. Sign extend value to 64 bits 2488 // now; without this it would get ZExt'd later in 2489 // ScheduleDAGSDNodes::EmitNode, which is very generic. 2490 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), 2491 MVT::i64)); 2492 return; 2493 } 2494 } 2495 break; 2496 } 2497 } 2498 } 2499 2500 std::vector<unsigned> TargetLowering:: 2501 getRegClassForInlineAsmConstraint(const std::string &Constraint, 2502 EVT VT) const { 2503 return std::vector<unsigned>(); 2504 } 2505 2506 2507 std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: 2508 getRegForInlineAsmConstraint(const std::string &Constraint, 2509 EVT VT) const { 2510 if (Constraint[0] != '{') 2511 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0)); 2512 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); 2513 2514 // Remove the braces from around the name. 2515 StringRef RegName(Constraint.data()+1, Constraint.size()-2); 2516 2517 // Figure out which register class contains this reg. 2518 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 2519 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), 2520 E = RI->regclass_end(); RCI != E; ++RCI) { 2521 const TargetRegisterClass *RC = *RCI; 2522 2523 // If none of the value types for this register class are valid, we 2524 // can't use it. For example, 64-bit reg classes on 32-bit targets. 2525 bool isLegal = false; 2526 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 2527 I != E; ++I) { 2528 if (isTypeLegal(*I)) { 2529 isLegal = true; 2530 break; 2531 } 2532 } 2533 2534 if (!isLegal) continue; 2535 2536 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 2537 I != E; ++I) { 2538 if (RegName.equals_lower(RI->getName(*I))) 2539 return std::make_pair(*I, RC); 2540 } 2541 } 2542 2543 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2544 } 2545 2546 //===----------------------------------------------------------------------===// 2547 // Constraint Selection. 2548 2549 /// isMatchingInputConstraint - Return true of this is an input operand that is 2550 /// a matching constraint like "4". 2551 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const { 2552 assert(!ConstraintCode.empty() && "No known constraint!"); 2553 return isdigit(ConstraintCode[0]); 2554 } 2555 2556 /// getMatchedOperand - If this is an input matching constraint, this method 2557 /// returns the output operand it matches. 2558 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const { 2559 assert(!ConstraintCode.empty() && "No known constraint!"); 2560 return atoi(ConstraintCode.c_str()); 2561 } 2562 2563 2564 /// getConstraintGenerality - Return an integer indicating how general CT 2565 /// is. 2566 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { 2567 switch (CT) { 2568 default: llvm_unreachable("Unknown constraint type!"); 2569 case TargetLowering::C_Other: 2570 case TargetLowering::C_Unknown: 2571 return 0; 2572 case TargetLowering::C_Register: 2573 return 1; 2574 case TargetLowering::C_RegisterClass: 2575 return 2; 2576 case TargetLowering::C_Memory: 2577 return 3; 2578 } 2579 } 2580 2581 /// ChooseConstraint - If there are multiple different constraints that we 2582 /// could pick for this operand (e.g. "imr") try to pick the 'best' one. 2583 /// This is somewhat tricky: constraints fall into four classes: 2584 /// Other -> immediates and magic values 2585 /// Register -> one specific register 2586 /// RegisterClass -> a group of regs 2587 /// Memory -> memory 2588 /// Ideally, we would pick the most specific constraint possible: if we have 2589 /// something that fits into a register, we would pick it. The problem here 2590 /// is that if we have something that could either be in a register or in 2591 /// memory that use of the register could cause selection of *other* 2592 /// operands to fail: they might only succeed if we pick memory. Because of 2593 /// this the heuristic we use is: 2594 /// 2595 /// 1) If there is an 'other' constraint, and if the operand is valid for 2596 /// that constraint, use it. This makes us take advantage of 'i' 2597 /// constraints when available. 2598 /// 2) Otherwise, pick the most general constraint present. This prefers 2599 /// 'm' over 'r', for example. 2600 /// 2601 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, 2602 const TargetLowering &TLI, 2603 SDValue Op, SelectionDAG *DAG) { 2604 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); 2605 unsigned BestIdx = 0; 2606 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; 2607 int BestGenerality = -1; 2608 2609 // Loop over the options, keeping track of the most general one. 2610 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { 2611 TargetLowering::ConstraintType CType = 2612 TLI.getConstraintType(OpInfo.Codes[i]); 2613 2614 // If this is an 'other' constraint, see if the operand is valid for it. 2615 // For example, on X86 we might have an 'rI' constraint. If the operand 2616 // is an integer in the range [0..31] we want to use I (saving a load 2617 // of a register), otherwise we must use 'r'. 2618 if (CType == TargetLowering::C_Other && Op.getNode()) { 2619 assert(OpInfo.Codes[i].size() == 1 && 2620 "Unhandled multi-letter 'other' constraint"); 2621 std::vector<SDValue> ResultOps; 2622 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], 2623 ResultOps, *DAG); 2624 if (!ResultOps.empty()) { 2625 BestType = CType; 2626 BestIdx = i; 2627 break; 2628 } 2629 } 2630 2631 // Things with matching constraints can only be registers, per gcc 2632 // documentation. This mainly affects "g" constraints. 2633 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) 2634 continue; 2635 2636 // This constraint letter is more general than the previous one, use it. 2637 int Generality = getConstraintGenerality(CType); 2638 if (Generality > BestGenerality) { 2639 BestType = CType; 2640 BestIdx = i; 2641 BestGenerality = Generality; 2642 } 2643 } 2644 2645 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; 2646 OpInfo.ConstraintType = BestType; 2647 } 2648 2649 /// ComputeConstraintToUse - Determines the constraint code and constraint 2650 /// type to use for the specific AsmOperandInfo, setting 2651 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. 2652 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, 2653 SDValue Op, 2654 SelectionDAG *DAG) const { 2655 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); 2656 2657 // Single-letter constraints ('r') are very common. 2658 if (OpInfo.Codes.size() == 1) { 2659 OpInfo.ConstraintCode = OpInfo.Codes[0]; 2660 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2661 } else { 2662 ChooseConstraint(OpInfo, *this, Op, DAG); 2663 } 2664 2665 // 'X' matches anything. 2666 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) { 2667 // Labels and constants are handled elsewhere ('X' is the only thing 2668 // that matches labels). For Functions, the type here is the type of 2669 // the result, which is not what we want to look at; leave them alone. 2670 Value *v = OpInfo.CallOperandVal; 2671 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) { 2672 OpInfo.CallOperandVal = v; 2673 return; 2674 } 2675 2676 // Otherwise, try to resolve it to something we know about by looking at 2677 // the actual operand type. 2678 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) { 2679 OpInfo.ConstraintCode = Repl; 2680 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); 2681 } 2682 } 2683 } 2684 2685 //===----------------------------------------------------------------------===// 2686 // Loop Strength Reduction hooks 2687 //===----------------------------------------------------------------------===// 2688 2689 /// isLegalAddressingMode - Return true if the addressing mode represented 2690 /// by AM is legal for this target, for a load/store of the specified type. 2691 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, 2692 const Type *Ty) const { 2693 // The default implementation of this implements a conservative RISCy, r+r and 2694 // r+i addr mode. 2695 2696 // Allows a sign-extended 16-bit immediate field. 2697 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2698 return false; 2699 2700 // No global is ever allowed as a base. 2701 if (AM.BaseGV) 2702 return false; 2703 2704 // Only support r+r, 2705 switch (AM.Scale) { 2706 case 0: // "r+i" or just "i", depending on HasBaseReg. 2707 break; 2708 case 1: 2709 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2710 return false; 2711 // Otherwise we have r+r or r+i. 2712 break; 2713 case 2: 2714 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2715 return false; 2716 // Allow 2*r as r+r. 2717 break; 2718 } 2719 2720 return true; 2721 } 2722 2723 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2724 /// return a DAG expression to select that will generate the same value by 2725 /// multiplying by a magic number. See: 2726 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2727 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, 2728 std::vector<SDNode*>* Created) const { 2729 EVT VT = N->getValueType(0); 2730 DebugLoc dl= N->getDebugLoc(); 2731 2732 // Check to see if we can do this. 2733 // FIXME: We should be more aggressive here. 2734 if (!isTypeLegal(VT)) 2735 return SDValue(); 2736 2737 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue(); 2738 APInt::ms magics = d.magic(); 2739 2740 // Multiply the numerator (operand 0) by the magic value 2741 // FIXME: We should support doing a MUL in a wider type 2742 SDValue Q; 2743 if (isOperationLegalOrCustom(ISD::MULHS, VT)) 2744 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), 2745 DAG.getConstant(magics.m, VT)); 2746 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) 2747 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), 2748 N->getOperand(0), 2749 DAG.getConstant(magics.m, VT)).getNode(), 1); 2750 else 2751 return SDValue(); // No mulhs or equvialent 2752 // If d > 0 and m < 0, add the numerator 2753 if (d.isStrictlyPositive() && magics.m.isNegative()) { 2754 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); 2755 if (Created) 2756 Created->push_back(Q.getNode()); 2757 } 2758 // If d < 0 and m > 0, subtract the numerator. 2759 if (d.isNegative() && magics.m.isStrictlyPositive()) { 2760 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2761 if (Created) 2762 Created->push_back(Q.getNode()); 2763 } 2764 // Shift right algebraic if shift value is nonzero 2765 if (magics.s > 0) { 2766 Q = DAG.getNode(ISD::SRA, dl, VT, Q, 2767 DAG.getConstant(magics.s, getShiftAmountTy())); 2768 if (Created) 2769 Created->push_back(Q.getNode()); 2770 } 2771 // Extract the sign bit and add it to the quotient 2772 SDValue T = 2773 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1, 2774 getShiftAmountTy())); 2775 if (Created) 2776 Created->push_back(T.getNode()); 2777 return DAG.getNode(ISD::ADD, dl, VT, Q, T); 2778 } 2779 2780 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2781 /// return a DAG expression to select that will generate the same value by 2782 /// multiplying by a magic number. See: 2783 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2784 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, 2785 std::vector<SDNode*>* Created) const { 2786 EVT VT = N->getValueType(0); 2787 DebugLoc dl = N->getDebugLoc(); 2788 2789 // Check to see if we can do this. 2790 // FIXME: We should be more aggressive here. 2791 if (!isTypeLegal(VT)) 2792 return SDValue(); 2793 2794 // FIXME: We should use a narrower constant when the upper 2795 // bits are known to be zero. 2796 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1)); 2797 APInt::mu magics = N1C->getAPIntValue().magicu(); 2798 2799 // Multiply the numerator (operand 0) by the magic value 2800 // FIXME: We should support doing a MUL in a wider type 2801 SDValue Q; 2802 if (isOperationLegalOrCustom(ISD::MULHU, VT)) 2803 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0), 2804 DAG.getConstant(magics.m, VT)); 2805 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) 2806 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), 2807 N->getOperand(0), 2808 DAG.getConstant(magics.m, VT)).getNode(), 1); 2809 else 2810 return SDValue(); // No mulhu or equvialent 2811 if (Created) 2812 Created->push_back(Q.getNode()); 2813 2814 if (magics.a == 0) { 2815 assert(magics.s < N1C->getAPIntValue().getBitWidth() && 2816 "We shouldn't generate an undefined shift!"); 2817 return DAG.getNode(ISD::SRL, dl, VT, Q, 2818 DAG.getConstant(magics.s, getShiftAmountTy())); 2819 } else { 2820 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 2821 if (Created) 2822 Created->push_back(NPQ.getNode()); 2823 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, 2824 DAG.getConstant(1, getShiftAmountTy())); 2825 if (Created) 2826 Created->push_back(NPQ.getNode()); 2827 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q); 2828 if (Created) 2829 Created->push_back(NPQ.getNode()); 2830 return DAG.getNode(ISD::SRL, dl, VT, NPQ, 2831 DAG.getConstant(magics.s-1, getShiftAmountTy())); 2832 } 2833 } 2834