1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements routines for translating functions from LLVM IR into
11 // Machine IR.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/FunctionLoweringInfo.h"
16 #include "llvm/ADT/PostOrderIterator.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/WinEHFuncInfo.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
42 #include <algorithm>
43 using namespace llvm;
44 
45 #define DEBUG_TYPE "function-lowering-info"
46 
47 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
48 /// PHI nodes or outside of the basic block that defines it, or used by a
49 /// switch or atomic instruction, which may expand to multiple basic blocks.
50 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
51   if (I->use_empty()) return false;
52   if (isa<PHINode>(I)) return true;
53   const BasicBlock *BB = I->getParent();
54   for (const User *U : I->users())
55     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
56       return true;
57 
58   return false;
59 }
60 
61 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
62   // For the users of the source value being used for compare instruction, if
63   // the number of signed predicate is greater than unsigned predicate, we
64   // prefer to use SIGN_EXTEND.
65   //
66   // With this optimization, we would be able to reduce some redundant sign or
67   // zero extension instruction, and eventually more machine CSE opportunities
68   // can be exposed.
69   ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
70   unsigned NumOfSigned = 0, NumOfUnsigned = 0;
71   for (const User *U : V->users()) {
72     if (const auto *CI = dyn_cast<CmpInst>(U)) {
73       NumOfSigned += CI->isSigned();
74       NumOfUnsigned += CI->isUnsigned();
75     }
76   }
77   if (NumOfSigned > NumOfUnsigned)
78     ExtendKind = ISD::SIGN_EXTEND;
79 
80   return ExtendKind;
81 }
82 
83 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
84                                SelectionDAG *DAG) {
85   Fn = &fn;
86   MF = &mf;
87   TLI = MF->getSubtarget().getTargetLowering();
88   RegInfo = &MF->getRegInfo();
89   MachineModuleInfo &MMI = MF->getMMI();
90 
91   // Check whether the function can return without sret-demotion.
92   SmallVector<ISD::OutputArg, 4> Outs;
93   GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
94   CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
95                                        Fn->isVarArg(), Outs, Fn->getContext());
96 
97   // Initialize the mapping of values to registers.  This is only set up for
98   // instruction values that are used outside of the block that defines
99   // them.
100   Function::const_iterator BB = Fn->begin(), EB = Fn->end();
101   for (; BB != EB; ++BB)
102     for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
103          I != E; ++I) {
104       if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
105         // Static allocas can be folded into the initial stack frame adjustment.
106         if (AI->isStaticAlloca()) {
107           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
108           Type *Ty = AI->getAllocatedType();
109           uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
110           unsigned Align =
111               std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
112                        AI->getAlignment());
113 
114           TySize *= CUI->getZExtValue();   // Get total allocated size.
115           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
116 
117           StaticAllocaMap[AI] =
118             MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
119 
120         } else {
121           unsigned Align = std::max(
122               (unsigned)TLI->getDataLayout()->getPrefTypeAlignment(
123                 AI->getAllocatedType()),
124               AI->getAlignment());
125           unsigned StackAlign =
126               MF->getSubtarget().getFrameLowering()->getStackAlignment();
127           if (Align <= StackAlign)
128             Align = 0;
129           // Inform the Frame Information that we have variable-sized objects.
130           MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
131         }
132       }
133 
134       // Look for inline asm that clobbers the SP register.
135       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
136         ImmutableCallSite CS(I);
137         if (isa<InlineAsm>(CS.getCalledValue())) {
138           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
139           const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
140           std::vector<TargetLowering::AsmOperandInfo> Ops =
141               TLI->ParseConstraints(TRI, CS);
142           for (size_t I = 0, E = Ops.size(); I != E; ++I) {
143             TargetLowering::AsmOperandInfo &Op = Ops[I];
144             if (Op.Type == InlineAsm::isClobber) {
145               // Clobbers don't have SDValue operands, hence SDValue().
146               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
147               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
148                   TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
149                                                     Op.ConstraintVT);
150               if (PhysReg.first == SP)
151                 MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
152             }
153           }
154         }
155       }
156 
157       // Look for calls to the @llvm.va_start intrinsic. We can omit some
158       // prologue boilerplate for variadic functions that don't examine their
159       // arguments.
160       if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
161         if (II->getIntrinsicID() == Intrinsic::vastart)
162           MF->getFrameInfo()->setHasVAStart(true);
163       }
164 
165       // If we have a musttail call in a variadic funciton, we need to ensure we
166       // forward implicit register parameters.
167       if (const auto *CI = dyn_cast<CallInst>(I)) {
168         if (CI->isMustTailCall() && Fn->isVarArg())
169           MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
170       }
171 
172       // Mark values used outside their block as exported, by allocating
173       // a virtual register for them.
174       if (isUsedOutsideOfDefiningBlock(I))
175         if (!isa<AllocaInst>(I) ||
176             !StaticAllocaMap.count(cast<AllocaInst>(I)))
177           InitializeRegForValue(I);
178 
179       // Collect llvm.dbg.declare information. This is done now instead of
180       // during the initial isel pass through the IR so that it is done
181       // in a predictable order.
182       if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
183         assert(DI->getVariable() && "Missing variable");
184         assert(DI->getDebugLoc() && "Missing location");
185         if (MMI.hasDebugInfo()) {
186           // Don't handle byval struct arguments or VLAs, for example.
187           // Non-byval arguments are handled here (they refer to the stack
188           // temporary alloca at this point).
189           const Value *Address = DI->getAddress();
190           if (Address) {
191             if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
192               Address = BCI->getOperand(0);
193             if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
194               DenseMap<const AllocaInst *, int>::iterator SI =
195                 StaticAllocaMap.find(AI);
196               if (SI != StaticAllocaMap.end()) { // Check for VLAs.
197                 int FI = SI->second;
198                 MMI.setVariableDbgInfo(DI->getVariable(), DI->getExpression(),
199                                        FI, DI->getDebugLoc());
200               }
201             }
202           }
203         }
204       }
205 
206       // Decide the preferred extend type for a value.
207       PreferredExtendType[I] = getPreferredExtendForValue(I);
208     }
209 
210   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
211   // also creates the initial PHI MachineInstrs, though none of the input
212   // operands are populated.
213   for (BB = Fn->begin(); BB != EB; ++BB) {
214     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
215     MBBMap[BB] = MBB;
216     MF->push_back(MBB);
217 
218     // Transfer the address-taken flag. This is necessary because there could
219     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
220     // the first one should be marked.
221     if (BB->hasAddressTaken())
222       MBB->setHasAddressTaken();
223 
224     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
225     // appropriate.
226     for (BasicBlock::const_iterator I = BB->begin();
227          const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
228       if (PN->use_empty()) continue;
229 
230       // Skip empty types
231       if (PN->getType()->isEmptyTy())
232         continue;
233 
234       DebugLoc DL = PN->getDebugLoc();
235       unsigned PHIReg = ValueMap[PN];
236       assert(PHIReg && "PHI node does not have an assigned virtual register!");
237 
238       SmallVector<EVT, 4> ValueVTs;
239       ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
240       for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
241         EVT VT = ValueVTs[vti];
242         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
243         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
244         for (unsigned i = 0; i != NumRegisters; ++i)
245           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
246         PHIReg += NumRegisters;
247       }
248     }
249   }
250 
251   // Mark landing pad blocks.
252   SmallVector<const LandingPadInst *, 4> LPads;
253   for (BB = Fn->begin(); BB != EB; ++BB) {
254     if (const auto *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
255       MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
256     if (BB->isLandingPad())
257       LPads.push_back(BB->getLandingPadInst());
258   }
259 
260   // If this is an MSVC EH personality, we need to do a bit more work.
261   EHPersonality Personality = EHPersonality::Unknown;
262   if (!LPads.empty())
263     Personality = classifyEHPersonality(LPads.back()->getPersonalityFn());
264   if (!isMSVCEHPersonality(Personality))
265     return;
266 
267   if (Personality == EHPersonality::MSVC_Win64SEH) {
268     addSEHHandlersForLPads(LPads);
269   } else if (Personality == EHPersonality::MSVC_CXX) {
270     const Function *WinEHParentFn = MMI.getWinEHParent(&fn);
271     WinEHFuncInfo &EHInfo = MMI.getWinEHFuncInfo(WinEHParentFn);
272     calculateWinCXXEHStateNumbers(WinEHParentFn, EHInfo);
273 
274     // Copy the state numbers to LandingPadInfo for the current function, which
275     // could be a handler or the parent.
276     for (const LandingPadInst *LP : LPads) {
277       MachineBasicBlock *LPadMBB = MBBMap[LP->getParent()];
278       MMI.addWinEHState(LPadMBB, EHInfo.LandingPadStateMap[LP]);
279     }
280   }
281 }
282 
283 void FunctionLoweringInfo::addSEHHandlersForLPads(
284     ArrayRef<const LandingPadInst *> LPads) {
285   MachineModuleInfo &MMI = MF->getMMI();
286 
287   // Iterate over all landing pads with llvm.eh.actions calls.
288   for (const LandingPadInst *LP : LPads) {
289     const IntrinsicInst *ActionsCall =
290         dyn_cast<IntrinsicInst>(LP->getNextNode());
291     if (!ActionsCall ||
292         ActionsCall->getIntrinsicID() != Intrinsic::eh_actions)
293       continue;
294 
295     // Parse the llvm.eh.actions call we found.
296     MachineBasicBlock *LPadMBB = MBBMap[LP->getParent()];
297     SmallVector<std::unique_ptr<ActionHandler>, 4> Actions;
298     parseEHActions(ActionsCall, Actions);
299 
300     // Iterate EH actions from most to least precedence, which means
301     // iterating in reverse.
302     for (auto I = Actions.rbegin(), E = Actions.rend(); I != E; ++I) {
303       ActionHandler *Action = I->get();
304       if (auto *CH = dyn_cast<CatchHandler>(Action)) {
305         const auto *Filter =
306             dyn_cast<Function>(CH->getSelector()->stripPointerCasts());
307         assert((Filter || CH->getSelector()->isNullValue()) &&
308                "expected function or catch-all");
309         const auto *RecoverBA =
310             cast<BlockAddress>(CH->getHandlerBlockOrFunc());
311         MMI.addSEHCatchHandler(LPadMBB, Filter, RecoverBA);
312       } else {
313         assert(isa<CleanupHandler>(Action));
314         const auto *Fini = cast<Function>(Action->getHandlerBlockOrFunc());
315         MMI.addSEHCleanupHandler(LPadMBB, Fini);
316       }
317     }
318   }
319 }
320 
321 /// clear - Clear out all the function-specific state. This returns this
322 /// FunctionLoweringInfo to an empty state, ready to be used for a
323 /// different function.
324 void FunctionLoweringInfo::clear() {
325   assert(CatchInfoFound.size() == CatchInfoLost.size() &&
326          "Not all catch info was assigned to a landing pad!");
327 
328   MBBMap.clear();
329   ValueMap.clear();
330   StaticAllocaMap.clear();
331 #ifndef NDEBUG
332   CatchInfoLost.clear();
333   CatchInfoFound.clear();
334 #endif
335   LiveOutRegInfo.clear();
336   VisitedBBs.clear();
337   ArgDbgValues.clear();
338   ByValArgFrameIndexMap.clear();
339   RegFixups.clear();
340   StatepointStackSlots.clear();
341   StatepointRelocatedValues.clear();
342   PreferredExtendType.clear();
343 }
344 
345 /// CreateReg - Allocate a single virtual register for the given type.
346 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
347   return RegInfo->createVirtualRegister(
348       MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
349 }
350 
351 /// CreateRegs - Allocate the appropriate number of virtual registers of
352 /// the correctly promoted or expanded types.  Assign these registers
353 /// consecutive vreg numbers and return the first assigned number.
354 ///
355 /// In the case that the given value has struct or array type, this function
356 /// will assign registers for each member or element.
357 ///
358 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
359   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
360 
361   SmallVector<EVT, 4> ValueVTs;
362   ComputeValueVTs(*TLI, Ty, ValueVTs);
363 
364   unsigned FirstReg = 0;
365   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
366     EVT ValueVT = ValueVTs[Value];
367     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
368 
369     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
370     for (unsigned i = 0; i != NumRegs; ++i) {
371       unsigned R = CreateReg(RegisterVT);
372       if (!FirstReg) FirstReg = R;
373     }
374   }
375   return FirstReg;
376 }
377 
378 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
379 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
380 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
381 /// the larger bit width by zero extension. The bit width must be no smaller
382 /// than the LiveOutInfo's existing bit width.
383 const FunctionLoweringInfo::LiveOutInfo *
384 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
385   if (!LiveOutRegInfo.inBounds(Reg))
386     return nullptr;
387 
388   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
389   if (!LOI->IsValid)
390     return nullptr;
391 
392   if (BitWidth > LOI->KnownZero.getBitWidth()) {
393     LOI->NumSignBits = 1;
394     LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
395     LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
396   }
397 
398   return LOI;
399 }
400 
401 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
402 /// register based on the LiveOutInfo of its operands.
403 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
404   Type *Ty = PN->getType();
405   if (!Ty->isIntegerTy() || Ty->isVectorTy())
406     return;
407 
408   SmallVector<EVT, 1> ValueVTs;
409   ComputeValueVTs(*TLI, Ty, ValueVTs);
410   assert(ValueVTs.size() == 1 &&
411          "PHIs with non-vector integer types should have a single VT.");
412   EVT IntVT = ValueVTs[0];
413 
414   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
415     return;
416   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
417   unsigned BitWidth = IntVT.getSizeInBits();
418 
419   unsigned DestReg = ValueMap[PN];
420   if (!TargetRegisterInfo::isVirtualRegister(DestReg))
421     return;
422   LiveOutRegInfo.grow(DestReg);
423   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
424 
425   Value *V = PN->getIncomingValue(0);
426   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
427     DestLOI.NumSignBits = 1;
428     APInt Zero(BitWidth, 0);
429     DestLOI.KnownZero = Zero;
430     DestLOI.KnownOne = Zero;
431     return;
432   }
433 
434   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
435     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
436     DestLOI.NumSignBits = Val.getNumSignBits();
437     DestLOI.KnownZero = ~Val;
438     DestLOI.KnownOne = Val;
439   } else {
440     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
441                                 "CopyToReg node was created.");
442     unsigned SrcReg = ValueMap[V];
443     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
444       DestLOI.IsValid = false;
445       return;
446     }
447     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
448     if (!SrcLOI) {
449       DestLOI.IsValid = false;
450       return;
451     }
452     DestLOI = *SrcLOI;
453   }
454 
455   assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
456          DestLOI.KnownOne.getBitWidth() == BitWidth &&
457          "Masks should have the same bit width as the type.");
458 
459   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
460     Value *V = PN->getIncomingValue(i);
461     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
462       DestLOI.NumSignBits = 1;
463       APInt Zero(BitWidth, 0);
464       DestLOI.KnownZero = Zero;
465       DestLOI.KnownOne = Zero;
466       return;
467     }
468 
469     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
470       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
471       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
472       DestLOI.KnownZero &= ~Val;
473       DestLOI.KnownOne &= Val;
474       continue;
475     }
476 
477     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
478                                 "its CopyToReg node was created.");
479     unsigned SrcReg = ValueMap[V];
480     if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
481       DestLOI.IsValid = false;
482       return;
483     }
484     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
485     if (!SrcLOI) {
486       DestLOI.IsValid = false;
487       return;
488     }
489     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
490     DestLOI.KnownZero &= SrcLOI->KnownZero;
491     DestLOI.KnownOne &= SrcLOI->KnownOne;
492   }
493 }
494 
495 /// setArgumentFrameIndex - Record frame index for the byval
496 /// argument. This overrides previous frame index entry for this argument,
497 /// if any.
498 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
499                                                  int FI) {
500   ByValArgFrameIndexMap[A] = FI;
501 }
502 
503 /// getArgumentFrameIndex - Get frame index for the byval argument.
504 /// If the argument does not have any assigned frame index then 0 is
505 /// returned.
506 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
507   DenseMap<const Argument *, int>::iterator I =
508     ByValArgFrameIndexMap.find(A);
509   if (I != ByValArgFrameIndexMap.end())
510     return I->second;
511   DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
512   return 0;
513 }
514 
515 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
516 /// being passed to this variadic function, and set the MachineModuleInfo's
517 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
518 /// reference to _fltused on Windows, which will link in MSVCRT's
519 /// floating-point support.
520 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
521                                       MachineModuleInfo *MMI)
522 {
523   FunctionType *FT = cast<FunctionType>(
524     I.getCalledValue()->getType()->getContainedType(0));
525   if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
526     for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
527       Type* T = I.getArgOperand(i)->getType();
528       for (auto i : post_order(T)) {
529         if (i->isFloatingPointTy()) {
530           MMI->setUsesVAFloatArgument(true);
531           return;
532         }
533       }
534     }
535   }
536 }
537 
538 /// AddLandingPadInfo - Extract the exception handling information from the
539 /// landingpad instruction and add them to the specified machine module info.
540 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
541                              MachineBasicBlock *MBB) {
542   MMI.addPersonality(MBB,
543                      cast<Function>(I.getPersonalityFn()->stripPointerCasts()));
544 
545   if (I.isCleanup())
546     MMI.addCleanup(MBB);
547 
548   // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
549   //        but we need to do it this way because of how the DWARF EH emitter
550   //        processes the clauses.
551   for (unsigned i = I.getNumClauses(); i != 0; --i) {
552     Value *Val = I.getClause(i - 1);
553     if (I.isCatch(i - 1)) {
554       MMI.addCatchTypeInfo(MBB,
555                            dyn_cast<GlobalValue>(Val->stripPointerCasts()));
556     } else {
557       // Add filters in a list.
558       Constant *CVal = cast<Constant>(Val);
559       SmallVector<const GlobalValue*, 4> FilterList;
560       for (User::op_iterator
561              II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
562         FilterList.push_back(cast<GlobalValue>((*II)->stripPointerCasts()));
563 
564       MMI.addFilterTypeInfo(MBB, FilterList);
565     }
566   }
567 }
568