1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the class that prints out the LLVM IR and machine
11 // functions using the MIR serialization format.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/MIRPrinter.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/None.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/StringRef.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
26 #include "llvm/CodeGen/MIRYamlMapping.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstr.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineMemOperand.h"
34 #include "llvm/CodeGen/MachineOperand.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/TargetInstrInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
39 #include "llvm/CodeGen/TargetSubtargetInfo.h"
40 #include "llvm/IR/BasicBlock.h"
41 #include "llvm/IR/Constants.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalValue.h"
46 #include "llvm/IR/IRPrintingPasses.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/ModuleSlotTracker.h"
52 #include "llvm/IR/Value.h"
53 #include "llvm/MC/LaneBitmask.h"
54 #include "llvm/MC/MCDwarf.h"
55 #include "llvm/MC/MCSymbol.h"
56 #include "llvm/Support/AtomicOrdering.h"
57 #include "llvm/Support/BranchProbability.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CommandLine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Format.h"
62 #include "llvm/Support/LowLevelTypeImpl.h"
63 #include "llvm/Support/YAMLTraits.h"
64 #include "llvm/Support/raw_ostream.h"
65 #include "llvm/Target/TargetIntrinsicInfo.h"
66 #include "llvm/Target/TargetMachine.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cinttypes>
70 #include <cstdint>
71 #include <iterator>
72 #include <string>
73 #include <utility>
74 #include <vector>
75 
76 using namespace llvm;
77 
78 static cl::opt<bool> SimplifyMIR(
79     "simplify-mir", cl::Hidden,
80     cl::desc("Leave out unnecessary information when printing MIR"));
81 
82 namespace {
83 
84 /// This structure describes how to print out stack object references.
85 struct FrameIndexOperand {
86   std::string Name;
87   unsigned ID;
88   bool IsFixed;
89 
90   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
91       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
92 
93   /// Return an ordinary stack object reference.
94   static FrameIndexOperand create(StringRef Name, unsigned ID) {
95     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
96   }
97 
98   /// Return a fixed stack object reference.
99   static FrameIndexOperand createFixed(unsigned ID) {
100     return FrameIndexOperand("", ID, /*IsFixed=*/true);
101   }
102 };
103 
104 } // end anonymous namespace
105 
106 namespace llvm {
107 
108 /// This class prints out the machine functions using the MIR serialization
109 /// format.
110 class MIRPrinter {
111   raw_ostream &OS;
112   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
113   /// Maps from stack object indices to operand indices which will be used when
114   /// printing frame index machine operands.
115   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
116 
117 public:
118   MIRPrinter(raw_ostream &OS) : OS(OS) {}
119 
120   void print(const MachineFunction &MF);
121 
122   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
123                const TargetRegisterInfo *TRI);
124   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
125                const MachineFrameInfo &MFI);
126   void convert(yaml::MachineFunction &MF,
127                const MachineConstantPool &ConstantPool);
128   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
129                const MachineJumpTableInfo &JTI);
130   void convertStackObjects(yaml::MachineFunction &YMF,
131                            const MachineFunction &MF, ModuleSlotTracker &MST);
132 
133 private:
134   void initRegisterMaskIds(const MachineFunction &MF);
135 };
136 
137 /// This class prints out the machine instructions using the MIR serialization
138 /// format.
139 class MIPrinter {
140   raw_ostream &OS;
141   ModuleSlotTracker &MST;
142   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
143   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
144   /// Synchronization scope names registered with LLVMContext.
145   SmallVector<StringRef, 8> SSNs;
146 
147   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
148   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
149 
150 public:
151   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
152             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
153             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
154       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
155         StackObjectOperandMapping(StackObjectOperandMapping) {}
156 
157   void print(const MachineBasicBlock &MBB);
158 
159   void print(const MachineInstr &MI);
160   void printIRBlockReference(const BasicBlock &BB);
161   void printIRValueReference(const Value &V);
162   void printStackObjectReference(int FrameIndex);
163   void printOffset(int64_t Offset);
164   void print(const MachineInstr &MI, unsigned OpIdx,
165              const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
166              LLT TypeToPrint, bool PrintDef = true);
167   void print(const LLVMContext &Context, const TargetInstrInfo &TII,
168              const MachineMemOperand &Op);
169   void printSyncScope(const LLVMContext &Context, SyncScope::ID SSID);
170 
171   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
172 };
173 
174 } // end namespace llvm
175 
176 namespace llvm {
177 namespace yaml {
178 
179 /// This struct serializes the LLVM IR module.
180 template <> struct BlockScalarTraits<Module> {
181   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
182     Mod.print(OS, nullptr);
183   }
184 
185   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
186     llvm_unreachable("LLVM Module is supposed to be parsed separately");
187     return "";
188   }
189 };
190 
191 } // end namespace yaml
192 } // end namespace llvm
193 
194 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
195                         const TargetRegisterInfo *TRI) {
196   raw_string_ostream OS(Dest.Value);
197   OS << printReg(Reg, TRI);
198 }
199 
200 void MIRPrinter::print(const MachineFunction &MF) {
201   initRegisterMaskIds(MF);
202 
203   yaml::MachineFunction YamlMF;
204   YamlMF.Name = MF.getName();
205   YamlMF.Alignment = MF.getAlignment();
206   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
207 
208   YamlMF.Legalized = MF.getProperties().hasProperty(
209       MachineFunctionProperties::Property::Legalized);
210   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
211       MachineFunctionProperties::Property::RegBankSelected);
212   YamlMF.Selected = MF.getProperties().hasProperty(
213       MachineFunctionProperties::Property::Selected);
214 
215   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
216   ModuleSlotTracker MST(MF.getFunction().getParent());
217   MST.incorporateFunction(MF.getFunction());
218   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
219   convertStackObjects(YamlMF, MF, MST);
220   if (const auto *ConstantPool = MF.getConstantPool())
221     convert(YamlMF, *ConstantPool);
222   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
223     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
224   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
225   bool IsNewlineNeeded = false;
226   for (const auto &MBB : MF) {
227     if (IsNewlineNeeded)
228       StrOS << "\n";
229     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
230         .print(MBB);
231     IsNewlineNeeded = true;
232   }
233   StrOS.flush();
234   yaml::Output Out(OS);
235   if (!SimplifyMIR)
236       Out.setWriteDefaultValues(true);
237   Out << YamlMF;
238 }
239 
240 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
241                                const TargetRegisterInfo *TRI) {
242   assert(RegMask && "Can't print an empty register mask");
243   OS << StringRef("CustomRegMask(");
244 
245   bool IsRegInRegMaskFound = false;
246   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
247     // Check whether the register is asserted in regmask.
248     if (RegMask[I / 32] & (1u << (I % 32))) {
249       if (IsRegInRegMaskFound)
250         OS << ',';
251       OS << printReg(I, TRI);
252       IsRegInRegMaskFound = true;
253     }
254   }
255 
256   OS << ')';
257 }
258 
259 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
260                                 const MachineRegisterInfo &RegInfo,
261                                 const TargetRegisterInfo *TRI) {
262   raw_string_ostream OS(Dest.Value);
263   OS << printRegClassOrBank(Reg, RegInfo, TRI);
264 }
265 
266 
267 void MIRPrinter::convert(yaml::MachineFunction &MF,
268                          const MachineRegisterInfo &RegInfo,
269                          const TargetRegisterInfo *TRI) {
270   MF.TracksRegLiveness = RegInfo.tracksLiveness();
271 
272   // Print the virtual register definitions.
273   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
274     unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
275     yaml::VirtualRegisterDefinition VReg;
276     VReg.ID = I;
277     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
278     unsigned PreferredReg = RegInfo.getSimpleHint(Reg);
279     if (PreferredReg)
280       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
281     MF.VirtualRegisters.push_back(VReg);
282   }
283 
284   // Print the live ins.
285   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
286     yaml::MachineFunctionLiveIn LiveIn;
287     printRegMIR(LI.first, LiveIn.Register, TRI);
288     if (LI.second)
289       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
290     MF.LiveIns.push_back(LiveIn);
291   }
292 
293   // Prints the callee saved registers.
294   if (RegInfo.isUpdatedCSRsInitialized()) {
295     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
296     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
297     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
298       yaml::FlowStringValue Reg;
299       printRegMIR(*I, Reg, TRI);
300       CalleeSavedRegisters.push_back(Reg);
301     }
302     MF.CalleeSavedRegisters = CalleeSavedRegisters;
303   }
304 }
305 
306 void MIRPrinter::convert(ModuleSlotTracker &MST,
307                          yaml::MachineFrameInfo &YamlMFI,
308                          const MachineFrameInfo &MFI) {
309   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
310   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
311   YamlMFI.HasStackMap = MFI.hasStackMap();
312   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
313   YamlMFI.StackSize = MFI.getStackSize();
314   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
315   YamlMFI.MaxAlignment = MFI.getMaxAlignment();
316   YamlMFI.AdjustsStack = MFI.adjustsStack();
317   YamlMFI.HasCalls = MFI.hasCalls();
318   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
319     ? MFI.getMaxCallFrameSize() : ~0u;
320   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
321   YamlMFI.HasVAStart = MFI.hasVAStart();
322   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
323   if (MFI.getSavePoint()) {
324     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
325     StrOS << printMBBReference(*MFI.getSavePoint());
326   }
327   if (MFI.getRestorePoint()) {
328     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
329     StrOS << printMBBReference(*MFI.getRestorePoint());
330   }
331 }
332 
333 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
334                                      const MachineFunction &MF,
335                                      ModuleSlotTracker &MST) {
336   const MachineFrameInfo &MFI = MF.getFrameInfo();
337   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
338   // Process fixed stack objects.
339   unsigned ID = 0;
340   for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
341     if (MFI.isDeadObjectIndex(I))
342       continue;
343 
344     yaml::FixedMachineStackObject YamlObject;
345     YamlObject.ID = ID;
346     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
347                           ? yaml::FixedMachineStackObject::SpillSlot
348                           : yaml::FixedMachineStackObject::DefaultType;
349     YamlObject.Offset = MFI.getObjectOffset(I);
350     YamlObject.Size = MFI.getObjectSize(I);
351     YamlObject.Alignment = MFI.getObjectAlignment(I);
352     YamlObject.StackID = MFI.getStackID(I);
353     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
354     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
355     YMF.FixedStackObjects.push_back(YamlObject);
356     StackObjectOperandMapping.insert(
357         std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
358   }
359 
360   // Process ordinary stack objects.
361   ID = 0;
362   for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
363     if (MFI.isDeadObjectIndex(I))
364       continue;
365 
366     yaml::MachineStackObject YamlObject;
367     YamlObject.ID = ID;
368     if (const auto *Alloca = MFI.getObjectAllocation(I))
369       YamlObject.Name.Value =
370           Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
371     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
372                           ? yaml::MachineStackObject::SpillSlot
373                           : MFI.isVariableSizedObjectIndex(I)
374                                 ? yaml::MachineStackObject::VariableSized
375                                 : yaml::MachineStackObject::DefaultType;
376     YamlObject.Offset = MFI.getObjectOffset(I);
377     YamlObject.Size = MFI.getObjectSize(I);
378     YamlObject.Alignment = MFI.getObjectAlignment(I);
379     YamlObject.StackID = MFI.getStackID(I);
380 
381     YMF.StackObjects.push_back(YamlObject);
382     StackObjectOperandMapping.insert(std::make_pair(
383         I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
384   }
385 
386   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
387     yaml::StringValue Reg;
388     printRegMIR(CSInfo.getReg(), Reg, TRI);
389     auto StackObjectInfo = StackObjectOperandMapping.find(CSInfo.getFrameIdx());
390     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
391            "Invalid stack object index");
392     const FrameIndexOperand &StackObject = StackObjectInfo->second;
393     if (StackObject.IsFixed) {
394       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRegister = Reg;
395       YMF.FixedStackObjects[StackObject.ID].CalleeSavedRestored =
396         CSInfo.isRestored();
397     } else {
398       YMF.StackObjects[StackObject.ID].CalleeSavedRegister = Reg;
399       YMF.StackObjects[StackObject.ID].CalleeSavedRestored =
400         CSInfo.isRestored();
401     }
402   }
403   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
404     auto LocalObject = MFI.getLocalFrameObjectMap(I);
405     auto StackObjectInfo = StackObjectOperandMapping.find(LocalObject.first);
406     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
407            "Invalid stack object index");
408     const FrameIndexOperand &StackObject = StackObjectInfo->second;
409     assert(!StackObject.IsFixed && "Expected a locally mapped stack object");
410     YMF.StackObjects[StackObject.ID].LocalOffset = LocalObject.second;
411   }
412 
413   // Print the stack object references in the frame information class after
414   // converting the stack objects.
415   if (MFI.hasStackProtectorIndex()) {
416     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
417     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
418         .printStackObjectReference(MFI.getStackProtectorIndex());
419   }
420 
421   // Print the debug variable information.
422   for (const MachineFunction::VariableDbgInfo &DebugVar :
423        MF.getVariableDbgInfo()) {
424     auto StackObjectInfo = StackObjectOperandMapping.find(DebugVar.Slot);
425     assert(StackObjectInfo != StackObjectOperandMapping.end() &&
426            "Invalid stack object index");
427     const FrameIndexOperand &StackObject = StackObjectInfo->second;
428     assert(!StackObject.IsFixed && "Expected a non-fixed stack object");
429     auto &Object = YMF.StackObjects[StackObject.ID];
430     {
431       raw_string_ostream StrOS(Object.DebugVar.Value);
432       DebugVar.Var->printAsOperand(StrOS, MST);
433     }
434     {
435       raw_string_ostream StrOS(Object.DebugExpr.Value);
436       DebugVar.Expr->printAsOperand(StrOS, MST);
437     }
438     {
439       raw_string_ostream StrOS(Object.DebugLoc.Value);
440       DebugVar.Loc->printAsOperand(StrOS, MST);
441     }
442   }
443 }
444 
445 void MIRPrinter::convert(yaml::MachineFunction &MF,
446                          const MachineConstantPool &ConstantPool) {
447   unsigned ID = 0;
448   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
449     std::string Str;
450     raw_string_ostream StrOS(Str);
451     if (Constant.isMachineConstantPoolEntry()) {
452       Constant.Val.MachineCPVal->print(StrOS);
453     } else {
454       Constant.Val.ConstVal->printAsOperand(StrOS);
455     }
456 
457     yaml::MachineConstantPoolValue YamlConstant;
458     YamlConstant.ID = ID++;
459     YamlConstant.Value = StrOS.str();
460     YamlConstant.Alignment = Constant.getAlignment();
461     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
462 
463     MF.Constants.push_back(YamlConstant);
464   }
465 }
466 
467 void MIRPrinter::convert(ModuleSlotTracker &MST,
468                          yaml::MachineJumpTable &YamlJTI,
469                          const MachineJumpTableInfo &JTI) {
470   YamlJTI.Kind = JTI.getEntryKind();
471   unsigned ID = 0;
472   for (const auto &Table : JTI.getJumpTables()) {
473     std::string Str;
474     yaml::MachineJumpTable::Entry Entry;
475     Entry.ID = ID++;
476     for (const auto *MBB : Table.MBBs) {
477       raw_string_ostream StrOS(Str);
478       StrOS << printMBBReference(*MBB);
479       Entry.Blocks.push_back(StrOS.str());
480       Str.clear();
481     }
482     YamlJTI.Entries.push_back(Entry);
483   }
484 }
485 
486 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
487   const auto *TRI = MF.getSubtarget().getRegisterInfo();
488   unsigned I = 0;
489   for (const uint32_t *Mask : TRI->getRegMasks())
490     RegisterMaskIds.insert(std::make_pair(Mask, I++));
491 }
492 
493 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
494                            SmallVectorImpl<MachineBasicBlock*> &Result,
495                            bool &IsFallthrough) {
496   SmallPtrSet<MachineBasicBlock*,8> Seen;
497 
498   for (const MachineInstr &MI : MBB) {
499     if (MI.isPHI())
500       continue;
501     for (const MachineOperand &MO : MI.operands()) {
502       if (!MO.isMBB())
503         continue;
504       MachineBasicBlock *Succ = MO.getMBB();
505       auto RP = Seen.insert(Succ);
506       if (RP.second)
507         Result.push_back(Succ);
508     }
509   }
510   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
511   IsFallthrough = I == MBB.end() || !I->isBarrier();
512 }
513 
514 bool
515 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
516   if (MBB.succ_size() <= 1)
517     return true;
518   if (!MBB.hasSuccessorProbabilities())
519     return true;
520 
521   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
522                                               MBB.Probs.end());
523   BranchProbability::normalizeProbabilities(Normalized.begin(),
524                                             Normalized.end());
525   SmallVector<BranchProbability,8> Equal(Normalized.size());
526   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
527 
528   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
529 }
530 
531 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
532   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
533   bool GuessedFallthrough;
534   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
535   if (GuessedFallthrough) {
536     const MachineFunction &MF = *MBB.getParent();
537     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
538     if (NextI != MF.end()) {
539       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
540       if (!is_contained(GuessedSuccs, Next))
541         GuessedSuccs.push_back(Next);
542     }
543   }
544   if (GuessedSuccs.size() != MBB.succ_size())
545     return false;
546   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
547 }
548 
549 void MIPrinter::print(const MachineBasicBlock &MBB) {
550   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
551   OS << "bb." << MBB.getNumber();
552   bool HasAttributes = false;
553   if (const auto *BB = MBB.getBasicBlock()) {
554     if (BB->hasName()) {
555       OS << "." << BB->getName();
556     } else {
557       HasAttributes = true;
558       OS << " (";
559       int Slot = MST.getLocalSlot(BB);
560       if (Slot == -1)
561         OS << "<ir-block badref>";
562       else
563         OS << (Twine("%ir-block.") + Twine(Slot)).str();
564     }
565   }
566   if (MBB.hasAddressTaken()) {
567     OS << (HasAttributes ? ", " : " (");
568     OS << "address-taken";
569     HasAttributes = true;
570   }
571   if (MBB.isEHPad()) {
572     OS << (HasAttributes ? ", " : " (");
573     OS << "landing-pad";
574     HasAttributes = true;
575   }
576   if (MBB.getAlignment()) {
577     OS << (HasAttributes ? ", " : " (");
578     OS << "align " << MBB.getAlignment();
579     HasAttributes = true;
580   }
581   if (HasAttributes)
582     OS << ")";
583   OS << ":\n";
584 
585   bool HasLineAttributes = false;
586   // Print the successors
587   bool canPredictProbs = canPredictBranchProbabilities(MBB);
588   // Even if the list of successors is empty, if we cannot guess it,
589   // we need to print it to tell the parser that the list is empty.
590   // This is needed, because MI model unreachable as empty blocks
591   // with an empty successor list. If the parser would see that
592   // without the successor list, it would guess the code would
593   // fallthrough.
594   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
595       !canPredictSuccessors(MBB)) {
596     OS.indent(2) << "successors: ";
597     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
598       if (I != MBB.succ_begin())
599         OS << ", ";
600       OS << printMBBReference(**I);
601       if (!SimplifyMIR || !canPredictProbs)
602         OS << '('
603            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
604            << ')';
605     }
606     OS << "\n";
607     HasLineAttributes = true;
608   }
609 
610   // Print the live in registers.
611   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
612   if (MRI.tracksLiveness() && !MBB.livein_empty()) {
613     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
614     OS.indent(2) << "liveins: ";
615     bool First = true;
616     for (const auto &LI : MBB.liveins()) {
617       if (!First)
618         OS << ", ";
619       First = false;
620       OS << printReg(LI.PhysReg, &TRI);
621       if (!LI.LaneMask.all())
622         OS << ":0x" << PrintLaneMask(LI.LaneMask);
623     }
624     OS << "\n";
625     HasLineAttributes = true;
626   }
627 
628   if (HasLineAttributes)
629     OS << "\n";
630   bool IsInBundle = false;
631   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
632     const MachineInstr &MI = *I;
633     if (IsInBundle && !MI.isInsideBundle()) {
634       OS.indent(2) << "}\n";
635       IsInBundle = false;
636     }
637     OS.indent(IsInBundle ? 4 : 2);
638     print(MI);
639     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
640       OS << " {";
641       IsInBundle = true;
642     }
643     OS << "\n";
644   }
645   if (IsInBundle)
646     OS.indent(2) << "}\n";
647 }
648 
649 void MIPrinter::print(const MachineInstr &MI) {
650   const auto *MF = MI.getMF();
651   const auto &MRI = MF->getRegInfo();
652   const auto &SubTarget = MF->getSubtarget();
653   const auto *TRI = SubTarget.getRegisterInfo();
654   assert(TRI && "Expected target register info");
655   const auto *TII = SubTarget.getInstrInfo();
656   assert(TII && "Expected target instruction info");
657   if (MI.isCFIInstruction())
658     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
659 
660   SmallBitVector PrintedTypes(8);
661   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
662   unsigned I = 0, E = MI.getNumOperands();
663   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
664          !MI.getOperand(I).isImplicit();
665        ++I) {
666     if (I)
667       OS << ", ";
668     print(MI, I, TRI, ShouldPrintRegisterTies,
669           MI.getTypeToPrint(I, PrintedTypes, MRI),
670           /*PrintDef=*/false);
671   }
672 
673   if (I)
674     OS << " = ";
675   if (MI.getFlag(MachineInstr::FrameSetup))
676     OS << "frame-setup ";
677   OS << TII->getName(MI.getOpcode());
678   if (I < E)
679     OS << ' ';
680 
681   bool NeedComma = false;
682   for (; I < E; ++I) {
683     if (NeedComma)
684       OS << ", ";
685     print(MI, I, TRI, ShouldPrintRegisterTies,
686           MI.getTypeToPrint(I, PrintedTypes, MRI));
687     NeedComma = true;
688   }
689 
690   if (MI.getDebugLoc()) {
691     if (NeedComma)
692       OS << ',';
693     OS << " debug-location ";
694     MI.getDebugLoc()->printAsOperand(OS, MST);
695   }
696 
697   if (!MI.memoperands_empty()) {
698     OS << " :: ";
699     const LLVMContext &Context = MF->getFunction().getContext();
700     bool NeedComma = false;
701     for (const auto *Op : MI.memoperands()) {
702       if (NeedComma)
703         OS << ", ";
704       print(Context, *TII, *Op);
705       NeedComma = true;
706     }
707   }
708 }
709 
710 static void printIRSlotNumber(raw_ostream &OS, int Slot) {
711   if (Slot == -1)
712     OS << "<badref>";
713   else
714     OS << Slot;
715 }
716 
717 void MIPrinter::printIRBlockReference(const BasicBlock &BB) {
718   OS << "%ir-block.";
719   if (BB.hasName()) {
720     printLLVMNameWithoutPrefix(OS, BB.getName());
721     return;
722   }
723   const Function *F = BB.getParent();
724   int Slot;
725   if (F == MST.getCurrentFunction()) {
726     Slot = MST.getLocalSlot(&BB);
727   } else {
728     ModuleSlotTracker CustomMST(F->getParent(),
729                                 /*ShouldInitializeAllMetadata=*/false);
730     CustomMST.incorporateFunction(*F);
731     Slot = CustomMST.getLocalSlot(&BB);
732   }
733   printIRSlotNumber(OS, Slot);
734 }
735 
736 void MIPrinter::printIRValueReference(const Value &V) {
737   if (isa<GlobalValue>(V)) {
738     V.printAsOperand(OS, /*PrintType=*/false, MST);
739     return;
740   }
741   if (isa<Constant>(V)) {
742     // Machine memory operands can load/store to/from constant value pointers.
743     OS << '`';
744     V.printAsOperand(OS, /*PrintType=*/true, MST);
745     OS << '`';
746     return;
747   }
748   OS << "%ir.";
749   if (V.hasName()) {
750     printLLVMNameWithoutPrefix(OS, V.getName());
751     return;
752   }
753   printIRSlotNumber(OS, MST.getLocalSlot(&V));
754 }
755 
756 void MIPrinter::printStackObjectReference(int FrameIndex) {
757   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
758   assert(ObjectInfo != StackObjectOperandMapping.end() &&
759          "Invalid frame index");
760   const FrameIndexOperand &Operand = ObjectInfo->second;
761   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
762                                             Operand.Name);
763 }
764 
765 void MIPrinter::printOffset(int64_t Offset) {
766   if (Offset == 0)
767     return;
768   if (Offset < 0) {
769     OS << " - " << -Offset;
770     return;
771   }
772   OS << " + " << Offset;
773 }
774 
775 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
776                       const TargetRegisterInfo *TRI,
777                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
778                       bool PrintDef) {
779   const MachineOperand &Op = MI.getOperand(OpIdx);
780   switch (Op.getType()) {
781   case MachineOperand::MO_Immediate:
782     if (MI.isOperandSubregIdx(OpIdx)) {
783       MachineOperand::printTargetFlags(OS, Op);
784       MachineOperand::printSubregIdx(OS, Op.getImm(), TRI);
785       break;
786     }
787     LLVM_FALLTHROUGH;
788   case MachineOperand::MO_Register:
789   case MachineOperand::MO_CImmediate:
790   case MachineOperand::MO_MachineBasicBlock:
791   case MachineOperand::MO_ConstantPoolIndex:
792   case MachineOperand::MO_TargetIndex:
793   case MachineOperand::MO_JumpTableIndex:
794   case MachineOperand::MO_ExternalSymbol:
795   case MachineOperand::MO_GlobalAddress:
796   case MachineOperand::MO_RegisterLiveOut:
797   case MachineOperand::MO_Metadata:
798   case MachineOperand::MO_MCSymbol: {
799     unsigned TiedOperandIdx = 0;
800     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
801       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
802     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
803     Op.print(OS, MST, TypeToPrint, PrintDef, ShouldPrintRegisterTies,
804              TiedOperandIdx, TRI, TII);
805     break;
806   }
807   case MachineOperand::MO_FPImmediate:
808     Op.getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
809     break;
810   case MachineOperand::MO_FrameIndex:
811     printStackObjectReference(Op.getIndex());
812     break;
813   case MachineOperand::MO_BlockAddress:
814     OS << "blockaddress(";
815     Op.getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
816                                                         MST);
817     OS << ", ";
818     printIRBlockReference(*Op.getBlockAddress()->getBasicBlock());
819     OS << ')';
820     printOffset(Op.getOffset());
821     break;
822   case MachineOperand::MO_RegisterMask: {
823     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
824     if (RegMaskInfo != RegisterMaskIds.end())
825       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
826     else
827       printCustomRegMask(Op.getRegMask(), OS, TRI);
828     break;
829   }
830   case MachineOperand::MO_CFIIndex: {
831     const MachineFunction &MF = *Op.getParent()->getMF();
832     print(MF.getFrameInstructions()[Op.getCFIIndex()], TRI);
833     break;
834   }
835   case MachineOperand::MO_IntrinsicID: {
836     Intrinsic::ID ID = Op.getIntrinsicID();
837     if (ID < Intrinsic::num_intrinsics)
838       OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
839     else {
840       const MachineFunction &MF = *Op.getParent()->getMF();
841       const TargetIntrinsicInfo *TII = MF.getTarget().getIntrinsicInfo();
842       OS << "intrinsic(@" << TII->getName(ID) << ')';
843     }
844     break;
845   }
846   case MachineOperand::MO_Predicate: {
847     auto Pred = static_cast<CmpInst::Predicate>(Op.getPredicate());
848     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
849        << CmpInst::getPredicateName(Pred) << ')';
850     break;
851   }
852   }
853 }
854 
855 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
856                                         unsigned TMMOFlag) {
857   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
858   for (const auto &I : Flags) {
859     if (I.first == TMMOFlag) {
860       return I.second;
861     }
862   }
863   return nullptr;
864 }
865 
866 void MIPrinter::print(const LLVMContext &Context, const TargetInstrInfo &TII,
867                       const MachineMemOperand &Op) {
868   OS << '(';
869   if (Op.isVolatile())
870     OS << "volatile ";
871   if (Op.isNonTemporal())
872     OS << "non-temporal ";
873   if (Op.isDereferenceable())
874     OS << "dereferenceable ";
875   if (Op.isInvariant())
876     OS << "invariant ";
877   if (Op.getFlags() & MachineMemOperand::MOTargetFlag1)
878     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag1)
879        << "\" ";
880   if (Op.getFlags() & MachineMemOperand::MOTargetFlag2)
881     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag2)
882        << "\" ";
883   if (Op.getFlags() & MachineMemOperand::MOTargetFlag3)
884     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag3)
885        << "\" ";
886 
887   assert((Op.isLoad() || Op.isStore()) && "machine memory operand must be a load or store (or both)");
888   if (Op.isLoad())
889     OS << "load ";
890   if (Op.isStore())
891     OS << "store ";
892 
893   printSyncScope(Context, Op.getSyncScopeID());
894 
895   if (Op.getOrdering() != AtomicOrdering::NotAtomic)
896     OS << toIRString(Op.getOrdering()) << ' ';
897   if (Op.getFailureOrdering() != AtomicOrdering::NotAtomic)
898     OS << toIRString(Op.getFailureOrdering()) << ' ';
899 
900   OS << Op.getSize();
901   if (const Value *Val = Op.getValue()) {
902     OS << ((Op.isLoad() && Op.isStore()) ? " on "
903                                          : Op.isLoad() ? " from " : " into ");
904     printIRValueReference(*Val);
905   } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
906     OS << ((Op.isLoad() && Op.isStore()) ? " on "
907                                          : Op.isLoad() ? " from " : " into ");
908     assert(PVal && "Expected a pseudo source value");
909     switch (PVal->kind()) {
910     case PseudoSourceValue::Stack:
911       OS << "stack";
912       break;
913     case PseudoSourceValue::GOT:
914       OS << "got";
915       break;
916     case PseudoSourceValue::JumpTable:
917       OS << "jump-table";
918       break;
919     case PseudoSourceValue::ConstantPool:
920       OS << "constant-pool";
921       break;
922     case PseudoSourceValue::FixedStack:
923       printStackObjectReference(
924           cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex());
925       break;
926     case PseudoSourceValue::GlobalValueCallEntry:
927       OS << "call-entry ";
928       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
929           OS, /*PrintType=*/false, MST);
930       break;
931     case PseudoSourceValue::ExternalSymbolCallEntry:
932       OS << "call-entry $";
933       printLLVMNameWithoutPrefix(
934           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
935       break;
936     case PseudoSourceValue::TargetCustom:
937       llvm_unreachable("TargetCustom pseudo source values are not supported");
938       break;
939     }
940   }
941   printOffset(Op.getOffset());
942   if (Op.getBaseAlignment() != Op.getSize())
943     OS << ", align " << Op.getBaseAlignment();
944   auto AAInfo = Op.getAAInfo();
945   if (AAInfo.TBAA) {
946     OS << ", !tbaa ";
947     AAInfo.TBAA->printAsOperand(OS, MST);
948   }
949   if (AAInfo.Scope) {
950     OS << ", !alias.scope ";
951     AAInfo.Scope->printAsOperand(OS, MST);
952   }
953   if (AAInfo.NoAlias) {
954     OS << ", !noalias ";
955     AAInfo.NoAlias->printAsOperand(OS, MST);
956   }
957   if (Op.getRanges()) {
958     OS << ", !range ";
959     Op.getRanges()->printAsOperand(OS, MST);
960   }
961   OS << ')';
962 }
963 
964 void MIPrinter::printSyncScope(const LLVMContext &Context, SyncScope::ID SSID) {
965   switch (SSID) {
966   case SyncScope::System: {
967     break;
968   }
969   default: {
970     if (SSNs.empty())
971       Context.getSyncScopeNames(SSNs);
972 
973     OS << "syncscope(\"";
974     PrintEscapedString(SSNs[SSID], OS);
975     OS << "\") ";
976     break;
977   }
978   }
979 }
980 
981 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
982                              const TargetRegisterInfo *TRI) {
983   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
984   if (Reg == -1) {
985     OS << "<badreg>";
986     return;
987   }
988   OS << printReg(Reg, TRI);
989 }
990 
991 void MIPrinter::print(const MCCFIInstruction &CFI,
992                       const TargetRegisterInfo *TRI) {
993   switch (CFI.getOperation()) {
994   case MCCFIInstruction::OpSameValue:
995     OS << "same_value ";
996     if (MCSymbol *Label = CFI.getLabel())
997       MachineOperand::printSymbol(OS, *Label);
998     printCFIRegister(CFI.getRegister(), OS, TRI);
999     break;
1000   case MCCFIInstruction::OpRememberState:
1001     OS << "remember_state ";
1002     if (MCSymbol *Label = CFI.getLabel())
1003       MachineOperand::printSymbol(OS, *Label);
1004     break;
1005   case MCCFIInstruction::OpRestoreState:
1006     OS << "restore_state ";
1007     if (MCSymbol *Label = CFI.getLabel())
1008       MachineOperand::printSymbol(OS, *Label);
1009     break;
1010   case MCCFIInstruction::OpOffset:
1011     OS << "offset ";
1012     if (MCSymbol *Label = CFI.getLabel())
1013       MachineOperand::printSymbol(OS, *Label);
1014     printCFIRegister(CFI.getRegister(), OS, TRI);
1015     OS << ", " << CFI.getOffset();
1016     break;
1017   case MCCFIInstruction::OpDefCfaRegister:
1018     OS << "def_cfa_register ";
1019     if (MCSymbol *Label = CFI.getLabel())
1020       MachineOperand::printSymbol(OS, *Label);
1021     printCFIRegister(CFI.getRegister(), OS, TRI);
1022     break;
1023   case MCCFIInstruction::OpDefCfaOffset:
1024     OS << "def_cfa_offset ";
1025     if (MCSymbol *Label = CFI.getLabel())
1026       MachineOperand::printSymbol(OS, *Label);
1027     OS << CFI.getOffset();
1028     break;
1029   case MCCFIInstruction::OpDefCfa:
1030     OS << "def_cfa ";
1031     if (MCSymbol *Label = CFI.getLabel())
1032       MachineOperand::printSymbol(OS, *Label);
1033     printCFIRegister(CFI.getRegister(), OS, TRI);
1034     OS << ", " << CFI.getOffset();
1035     break;
1036   case MCCFIInstruction::OpRelOffset:
1037     OS << "rel_offset ";
1038     if (MCSymbol *Label = CFI.getLabel())
1039       MachineOperand::printSymbol(OS, *Label);
1040     printCFIRegister(CFI.getRegister(), OS, TRI);
1041     OS << ", " << CFI.getOffset();
1042     break;
1043   case MCCFIInstruction::OpAdjustCfaOffset:
1044     OS << "adjust_cfa_offset ";
1045     if (MCSymbol *Label = CFI.getLabel())
1046       MachineOperand::printSymbol(OS, *Label);
1047     OS << CFI.getOffset();
1048     break;
1049   case MCCFIInstruction::OpRestore:
1050     OS << "restore ";
1051     if (MCSymbol *Label = CFI.getLabel())
1052       MachineOperand::printSymbol(OS, *Label);
1053     printCFIRegister(CFI.getRegister(), OS, TRI);
1054     break;
1055   case MCCFIInstruction::OpEscape: {
1056     OS << "escape ";
1057     if (MCSymbol *Label = CFI.getLabel())
1058       MachineOperand::printSymbol(OS, *Label);
1059     if (!CFI.getValues().empty()) {
1060       size_t e = CFI.getValues().size() - 1;
1061       for (size_t i = 0; i < e; ++i)
1062         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
1063       OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
1064     }
1065     break;
1066   }
1067   case MCCFIInstruction::OpUndefined:
1068     OS << "undefined ";
1069     if (MCSymbol *Label = CFI.getLabel())
1070       MachineOperand::printSymbol(OS, *Label);
1071     printCFIRegister(CFI.getRegister(), OS, TRI);
1072     break;
1073   case MCCFIInstruction::OpRegister:
1074     OS << "register ";
1075     if (MCSymbol *Label = CFI.getLabel())
1076       MachineOperand::printSymbol(OS, *Label);
1077     printCFIRegister(CFI.getRegister(), OS, TRI);
1078     OS << ", ";
1079     printCFIRegister(CFI.getRegister2(), OS, TRI);
1080     break;
1081   case MCCFIInstruction::OpWindowSave:
1082     OS << "window_save ";
1083     if (MCSymbol *Label = CFI.getLabel())
1084       MachineOperand::printSymbol(OS, *Label);
1085     break;
1086   default:
1087     // TODO: Print the other CFI Operations.
1088     OS << "<unserializable cfi operation>";
1089     break;
1090   }
1091 }
1092 
1093 void llvm::printMIR(raw_ostream &OS, const Module &M) {
1094   yaml::Output Out(OS);
1095   Out << const_cast<Module &>(M);
1096 }
1097 
1098 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
1099   MIRPrinter Printer(OS);
1100   Printer.print(MF);
1101 }
1102