1 //===- MIParser.h - Machine Instructions Parser -----------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the function that parses the machine instructions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
15 #define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
16 
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/StringMap.h"
19 #include "llvm/Support/Allocator.h"
20 
21 namespace llvm {
22 
23 class MachineBasicBlock;
24 class MachineFunction;
25 class MDNode;
26 class RegisterBank;
27 struct SlotMapping;
28 class SMDiagnostic;
29 class SourceMgr;
30 class StringRef;
31 class TargetRegisterClass;
32 
33 struct VRegInfo {
34   enum uint8_t {
35     UNKNOWN, NORMAL, GENERIC, REGBANK
36   } Kind = UNKNOWN;
37   bool Explicit = false; ///< VReg was explicitly specified in the .mir file.
38   union {
39     const TargetRegisterClass *RC;
40     const RegisterBank *RegBank;
41   } D;
42   unsigned VReg;
43   unsigned PreferredReg = 0;
44 };
45 
46 using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
47 using Name2RegBankMap = StringMap<const RegisterBank *>;
48 
49 struct PerFunctionMIParsingState {
50   BumpPtrAllocator Allocator;
51   MachineFunction &MF;
52   SourceMgr *SM;
53   const SlotMapping &IRSlots;
54   const Name2RegClassMap &Names2RegClasses;
55   const Name2RegBankMap &Names2RegBanks;
56 
57   DenseMap<unsigned, MachineBasicBlock *> MBBSlots;
58   DenseMap<unsigned, VRegInfo*> VRegInfos;
59   DenseMap<unsigned, int> FixedStackObjectSlots;
60   DenseMap<unsigned, int> StackObjectSlots;
61   DenseMap<unsigned, unsigned> ConstantPoolSlots;
62   DenseMap<unsigned, unsigned> JumpTableSlots;
63 
64   PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM,
65                             const SlotMapping &IRSlots,
66                             const Name2RegClassMap &Names2RegClasses,
67                             const Name2RegBankMap &Names2RegBanks);
68 
69   VRegInfo &getVRegInfo(unsigned VReg);
70 };
71 
72 /// Parse the machine basic block definitions, and skip the machine
73 /// instructions.
74 ///
75 /// This function runs the first parsing pass on the machine function's body.
76 /// It parses only the machine basic block definitions and creates the machine
77 /// basic blocks in the given machine function.
78 ///
79 /// The machine instructions aren't parsed during the first pass because all
80 /// the machine basic blocks aren't defined yet - this makes it impossible to
81 /// resolve the machine basic block references.
82 ///
83 /// Return true if an error occurred.
84 bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS,
85                                        StringRef Src, SMDiagnostic &Error);
86 
87 /// Parse the machine instructions.
88 ///
89 /// This function runs the second parsing pass on the machine function's body.
90 /// It skips the machine basic block definitions and parses only the machine
91 /// instructions and basic block attributes like liveins and successors.
92 ///
93 /// The second parsing pass assumes that the first parsing pass already ran
94 /// on the given source string.
95 ///
96 /// Return true if an error occurred.
97 bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src,
98                               SMDiagnostic &Error);
99 
100 bool parseMBBReference(PerFunctionMIParsingState &PFS,
101                        MachineBasicBlock *&MBB, StringRef Src,
102                        SMDiagnostic &Error);
103 
104 bool parseRegisterReference(PerFunctionMIParsingState &PFS,
105                             unsigned &Reg, StringRef Src,
106                             SMDiagnostic &Error);
107 
108 bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, unsigned &Reg,
109                                  StringRef Src, SMDiagnostic &Error);
110 
111 bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS,
112                                    VRegInfo *&Info, StringRef Src,
113                                    SMDiagnostic &Error);
114 
115 bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI,
116                                StringRef Src, SMDiagnostic &Error);
117 
118 bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src,
119                  SMDiagnostic &Error);
120 
121 } // end namespace llvm
122 
123 #endif // LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
124