1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegisterBank class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
15 
16 #define DEBUG_TYPE "registerbank"
17 
18 using namespace llvm;
19 
20 const unsigned RegisterBank::InvalidID = UINT_MAX;
21 
22 RegisterBank::RegisterBank(unsigned ID, const char *Name, unsigned Size,
23                            const uint32_t *CoveredClasses)
24     : ID(ID), Name(Name), Size(Size) {
25   ContainedRegClasses.resize(200);
26   ContainedRegClasses.setBitsInMask(CoveredClasses);
27 }
28 
29 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
30   assert(isValid() && "Invalid register bank");
31   for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
32     const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
33 
34     if (!covers(RC))
35       continue;
36     // Verify that the register bank covers all the sub classes of the
37     // classes it covers.
38 
39     // Use a different (slow in that case) method than
40     // RegisterBankInfo to find the subclasses of RC, to make sure
41     // both agree on the covers.
42     for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
43       const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
44 
45       if (!RC.hasSubClassEq(&SubRC))
46         continue;
47 
48       // Verify that the Size of the register bank is big enough to cover
49       // all the register classes it covers.
50       assert((getSize() >= SubRC.getSize() * 8) &&
51              "Size is not big enough for all the subclasses!");
52       assert(covers(SubRC) && "Not all subclasses are covered");
53     }
54   }
55   return true;
56 }
57 
58 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
59   assert(isValid() && "RB hasn't been initialized yet");
60   return ContainedRegClasses.test(RC.getID());
61 }
62 
63 bool RegisterBank::isValid() const {
64   return ID != InvalidID && Name != nullptr && Size != 0 &&
65          // A register bank that does not cover anything is useless.
66          !ContainedRegClasses.empty();
67 }
68 
69 bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
70   // There must be only one instance of a given register bank alive
71   // for the whole compilation.
72   // The RegisterBankInfo is supposed to enforce that.
73   assert((OtherRB.getID() != getID() || &OtherRB == this) &&
74          "ID does not uniquely identify a RegisterBank");
75   return &OtherRB == this;
76 }
77 
78 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
79   print(dbgs(), /* IsForDebug */ true, TRI);
80 }
81 
82 void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
83                          const TargetRegisterInfo *TRI) const {
84   OS << getName();
85   if (!IsForDebug)
86     return;
87   OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
88      << "isValid:" << isValid() << '\n'
89      << "Number of Covered register classes: " << ContainedRegClasses.count()
90      << '\n';
91   // Print all the subclasses if we can.
92   // This register classes may not be properly initialized yet.
93   if (!TRI || ContainedRegClasses.empty())
94     return;
95   assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
96          "TRI does not match the initialization process?");
97   bool IsFirst = true;
98   OS << "Covered register classes:\n";
99   for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
100     const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
101 
102     if (!covers(RC))
103       continue;
104 
105     if (!IsFirst)
106       OS << ", ";
107     OS << TRI->getRegClassName(&RC);
108     IsFirst = false;
109   }
110 }
111