1 //===- llvm/CodeGen/GlobalISel/RegisterBank.cpp - Register Bank --*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the RegisterBank class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
14 #include "llvm/CodeGen/TargetRegisterInfo.h"
15 
16 #define DEBUG_TYPE "registerbank"
17 
18 using namespace llvm;
19 
20 const unsigned RegisterBank::InvalidID = UINT_MAX;
21 
22 RegisterBank::RegisterBank(
23     unsigned ID, const char *Name, unsigned Size,
24     const uint32_t *CoveredClasses, unsigned NumRegClasses)
25     : ID(ID), Name(Name), Size(Size) {
26   ContainedRegClasses.resize(NumRegClasses);
27   ContainedRegClasses.setBitsInMask(CoveredClasses);
28 }
29 
30 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
31   assert(isValid() && "Invalid register bank");
32   for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
33     const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
34 
35     if (!covers(RC))
36       continue;
37     // Verify that the register bank covers all the sub classes of the
38     // classes it covers.
39 
40     // Use a different (slow in that case) method than
41     // RegisterBankInfo to find the subclasses of RC, to make sure
42     // both agree on the covers.
43     for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
44       const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
45 
46       if (!RC.hasSubClassEq(&SubRC))
47         continue;
48 
49       // Verify that the Size of the register bank is big enough to cover
50       // all the register classes it covers.
51       assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
52              "Size is not big enough for all the subclasses!");
53       assert(covers(SubRC) && "Not all subclasses are covered");
54     }
55   }
56   return true;
57 }
58 
59 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
60   assert(isValid() && "RB hasn't been initialized yet");
61   return ContainedRegClasses.test(RC.getID());
62 }
63 
64 bool RegisterBank::isValid() const {
65   return ID != InvalidID && Name != nullptr && Size != 0 &&
66          // A register bank that does not cover anything is useless.
67          !ContainedRegClasses.empty();
68 }
69 
70 bool RegisterBank::operator==(const RegisterBank &OtherRB) const {
71   // There must be only one instance of a given register bank alive
72   // for the whole compilation.
73   // The RegisterBankInfo is supposed to enforce that.
74   assert((OtherRB.getID() != getID() || &OtherRB == this) &&
75          "ID does not uniquely identify a RegisterBank");
76   return &OtherRB == this;
77 }
78 
79 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
80 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
81   print(dbgs(), /* IsForDebug */ true, TRI);
82 }
83 #endif
84 
85 void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
86                          const TargetRegisterInfo *TRI) const {
87   OS << getName();
88   if (!IsForDebug)
89     return;
90   OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n"
91      << "isValid:" << isValid() << '\n'
92      << "Number of Covered register classes: " << ContainedRegClasses.count()
93      << '\n';
94   // Print all the subclasses if we can.
95   // This register classes may not be properly initialized yet.
96   if (!TRI || ContainedRegClasses.empty())
97     return;
98   assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &&
99          "TRI does not match the initialization process?");
100   bool IsFirst = true;
101   OS << "Covered register classes:\n";
102   for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
103     const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
104 
105     if (!covers(RC))
106       continue;
107 
108     if (!IsFirst)
109       OS << ", ";
110     OS << TRI->getRegClassName(&RC);
111     IsFirst = false;
112   }
113 }
114