1 //=- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-=====//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // This class implements a deterministic finite automaton (DFA) based
10 // packetizing mechanism for VLIW architectures. It provides APIs to
11 // determine whether there exists a legal mapping of instructions to
12 // functional unit assignments in a packet. The DFA is auto-generated from
13 // the target's Schedule.td file.
14 //
15 // A DFA consists of 3 major elements: states, inputs, and transitions. For
16 // the packetizing mechanism, the input is the set of instruction classes for
17 // a target. The state models all possible combinations of functional unit
18 // consumption for a given set of instructions in a packet. A transition
19 // models the addition of an instruction to a packet. In the DFA constructed
20 // by this class, if an instruction can be added to a packet, then a valid
21 // transition exists from the corresponding state. Invalid transitions
22 // indicate that the instruction cannot be added to the current packet.
23 //
24 //===----------------------------------------------------------------------===//
25 
26 #ifndef LLVM_CODEGEN_DFAPACKETIZER_H
27 #define LLVM_CODEGEN_DFAPACKETIZER_H
28 
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/ADT/DenseMap.h"
31 
32 namespace llvm {
33 
34 class MCInstrDesc;
35 class MachineInstr;
36 class MachineLoopInfo;
37 class MachineDominatorTree;
38 class InstrItineraryData;
39 class ScheduleDAGInstrs;
40 class SUnit;
41 
42 class DFAPacketizer {
43 private:
44   typedef std::pair<unsigned, unsigned> UnsignPair;
45   const InstrItineraryData *InstrItins;
46   int CurrentState;
47   const int (*DFAStateInputTable)[2];
48   const unsigned *DFAStateEntryTable;
49 
50   // CachedTable is a map from <FromState, Input> to ToState.
51   DenseMap<UnsignPair, unsigned> CachedTable;
52 
53   // ReadTable - Read the DFA transition table and update CachedTable.
54   void ReadTable(unsigned int state);
55 
56 public:
57   DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
58                 const unsigned *SET);
59 
60   // Reset the current state to make all resources available.
61   void clearResources() {
62     CurrentState = 0;
63   }
64 
65   // canReserveResources - Check if the resources occupied by a MCInstrDesc
66   // are available in the current state.
67   bool canReserveResources(const llvm::MCInstrDesc *MID);
68 
69   // reserveResources - Reserve the resources occupied by a MCInstrDesc and
70   // change the current state to reflect that change.
71   void reserveResources(const llvm::MCInstrDesc *MID);
72 
73   // canReserveResources - Check if the resources occupied by a machine
74   // instruction are available in the current state.
75   bool canReserveResources(llvm::MachineInstr *MI);
76 
77   // reserveResources - Reserve the resources occupied by a machine
78   // instruction and change the current state to reflect that change.
79   void reserveResources(llvm::MachineInstr *MI);
80 };
81 
82 // VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The
83 // packetizer works on machine basic blocks. For each instruction I in BB, the
84 // packetizer consults the DFA to see if machine resources are available to
85 // execute I. If so, the packetizer checks if I depends on any instruction J in
86 // the current packet. If no dependency is found, I is added to current packet
87 // and machine resource is marked as taken. If any dependency is found, a target
88 // API call is made to prune the dependence.
89 class VLIWPacketizerList {
90   const TargetMachine &TM;
91   const MachineFunction &MF;
92   const TargetInstrInfo *TII;
93 
94   // Encapsulate data types not exposed to the target interface.
95   ScheduleDAGInstrs *SchedulerImpl;
96 
97 protected:
98   // Vector of instructions assigned to the current packet.
99   std::vector<MachineInstr*> CurrentPacketMIs;
100   // DFA resource tracker.
101   DFAPacketizer *ResourceTracker;
102   // Scheduling units.
103   std::vector<SUnit> SUnits;
104 
105 public:
106   VLIWPacketizerList(
107     MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
108     bool IsPostRA);
109 
110   virtual ~VLIWPacketizerList();
111 
112   // PacketizeMIs - Implement this API in the backend to bundle instructions.
113   void PacketizeMIs(MachineBasicBlock *MBB,
114                     MachineBasicBlock::iterator BeginItr,
115                     MachineBasicBlock::iterator EndItr);
116 
117   // getResourceTracker - return ResourceTracker
118   DFAPacketizer *getResourceTracker() {return ResourceTracker;}
119 
120   // addToPacket - Add MI to the current packet.
121   void addToPacket(MachineInstr *MI);
122 
123   // endPacket - End the current packet.
124   void endPacket(MachineBasicBlock *MBB, MachineInstr *I);
125 
126   // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
127   bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB);
128 
129   // isSoloInstruction - return true if instruction I must end previous
130   // packet.
131   bool isSoloInstruction(MachineInstr *I);
132 
133   // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
134   // together.
135   virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
136     return false;
137   }
138 
139   // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
140   // and SUJ.
141   virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
142     return false;
143   }
144 };
145 }
146 
147 #endif
148