1*a9643ea8Slogwang# 2*a9643ea8Slogwang# This file adds to the values in AR933X_BASE.hints 3*a9643ea8Slogwang# 4*a9643ea8Slogwang# $FreeBSD$ 5*a9643ea8Slogwang 6*a9643ea8Slogwang# mdiobus on arge1 7*a9643ea8Slogwanghint.argemdio.0.at="nexus0" 8*a9643ea8Slogwanghint.argemdio.0.maddr=0x1a000000 9*a9643ea8Slogwanghint.argemdio.0.msize=0x1000 10*a9643ea8Slogwanghint.argemdio.0.order=0 11*a9643ea8Slogwang 12*a9643ea8Slogwang# There's no need to set the ar933x GMAC configuration bits. 13*a9643ea8Slogwang# This just creates a switch instance and correctly uses it. 14*a9643ea8Slogwang 15*a9643ea8Slogwang# Embedded Atheros Switch 16*a9643ea8Slogwanghint.arswitch.0.at="mdio0" 17*a9643ea8Slogwang 18*a9643ea8Slogwang# XXX this should really say it's an AR933x switch, as there 19*a9643ea8Slogwang# are some vlan specific differences here! 20*a9643ea8Slogwanghint.arswitch.0.is_7240=1 21*a9643ea8Slogwanghint.arswitch.0.numphys=4 22*a9643ea8Slogwanghint.arswitch.0.phy4cpu=1 # phy 4 is a "CPU" separate PHY 23*a9643ea8Slogwanghint.arswitch.0.is_rgmii=0 24*a9643ea8Slogwanghint.arswitch.0.is_gmii=1 # arge1 <-> switch PHY is GMII 25*a9643ea8Slogwang 26*a9643ea8Slogwang# arge0 - MII, autoneg, phy(4) 27*a9643ea8Slogwanghint.arge.0.phymask=0x10 # PHY4 28*a9643ea8Slogwanghint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus 29*a9643ea8Slogwang 30*a9643ea8Slogwang# arge1 - GMII, 1000/full 31*a9643ea8Slogwanghint.arge.1.phymask=0x0 # No directly mapped PHYs 32*a9643ea8Slogwanghint.arge.1.media=1000 33*a9643ea8Slogwanghint.arge.1.fduplex=1 34*a9643ea8Slogwang 35*a9643ea8Slogwang# Where the ART is - last 64k in the flash 36*a9643ea8Slogwang# 0x9fff1000 ? 37*a9643ea8Slogwanghint.ath.0.eepromaddr=0x1fff0000 38*a9643ea8Slogwanghint.ath.0.eepromsize=16384 39*a9643ea8Slogwang 40*a9643ea8Slogwang# The board 16MiB flash layout in uboot env: 41*a9643ea8Slogwang# 42*a9643ea8Slogwang# 256k (uboot), 64k (uboot-env), 14336k (rootfs), 1600k (kernel), 64k (NVRAM), 64k (ART) 43*a9643ea8Slogwang 44*a9643ea8Slogwang# However, it boots from 0x9f050000, which is the front of the flsah! 45*a9643ea8Slogwang# Thus the kernel/rootfs are switched around. 46*a9643ea8Slogwang 47*a9643ea8Slogwang# 256KB 48*a9643ea8Slogwanghint.map.0.at="flash/spi0" 49*a9643ea8Slogwanghint.map.0.start=0x00000000 50*a9643ea8Slogwanghint.map.0.end=0x000040000 51*a9643ea8Slogwanghint.map.0.name="uboot" 52*a9643ea8Slogwanghint.map.0.readonly=1 53*a9643ea8Slogwang 54*a9643ea8Slogwang# 64KB 55*a9643ea8Slogwanghint.map.1.at="flash/spi0" 56*a9643ea8Slogwanghint.map.1.start=0x00040000 57*a9643ea8Slogwanghint.map.1.end=0x00050000 58*a9643ea8Slogwanghint.map.1.name="uboot-env" 59*a9643ea8Slogwanghint.map.1.readonly=0 60*a9643ea8Slogwang 61*a9643ea8Slogwang# 1600KB 62*a9643ea8Slogwanghint.map.2.at="flash/spi0" 63*a9643ea8Slogwanghint.map.2.start=0x00050000 64*a9643ea8Slogwanghint.map.2.end=0x001e0000 65*a9643ea8Slogwanghint.map.2.name="kernel" 66*a9643ea8Slogwanghint.map.2.readonly=0 67*a9643ea8Slogwang 68*a9643ea8Slogwang# 14336KB 69*a9643ea8Slogwanghint.map.3.at="flash/spi0" 70*a9643ea8Slogwanghint.map.3.start=0x001e0000 71*a9643ea8Slogwanghint.map.3.end=0x00fe0000 72*a9643ea8Slogwanghint.map.3.name="rootfs" 73*a9643ea8Slogwanghint.map.3.readonly=0 74*a9643ea8Slogwang 75*a9643ea8Slogwang# NVRAM 76*a9643ea8Slogwanghint.map.4.at="flash/spi0" 77*a9643ea8Slogwanghint.map.4.start=0x00fe0000 78*a9643ea8Slogwanghint.map.4.end=0x00ff0000 79*a9643ea8Slogwanghint.map.4.name="cfg" 80*a9643ea8Slogwanghint.map.4.readonly=0 81*a9643ea8Slogwang 82*a9643ea8Slogwang# This is radio calibration section. It is (or should be!) unique 83*a9643ea8Slogwang# for each board, to take into account thermal and electrical differences 84*a9643ea8Slogwang# as well as the regulatory compliance data. 85*a9643ea8Slogwang# 86*a9643ea8Slogwanghint.map.5.at="flash/spi0" 87*a9643ea8Slogwanghint.map.5.start=0x00ff0000 88*a9643ea8Slogwanghint.map.5.end=0x01000000 89*a9643ea8Slogwanghint.map.5.name="art" 90*a9643ea8Slogwanghint.map.5.readonly=1 91*a9643ea8Slogwang 92*a9643ea8Slogwang# GPIO specific configuration block 93*a9643ea8Slogwang 94*a9643ea8Slogwang# Don't flip on anything that isn't already enabled. 95*a9643ea8Slogwang# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're 96*a9643ea8Slogwang# not used here. 97*a9643ea8Slogwanghint.gpio.0.function_set=0x00000000 98*a9643ea8Slogwanghint.gpio.0.function_clear=0x00000000 99*a9643ea8Slogwang 100*a9643ea8Slogwang# These are the GPIO LEDs and buttons which can be software controlled. 101*a9643ea8Slogwang#hint.gpio.0.pinmask=0x001c02ae 102*a9643ea8Slogwang#hint.gpio.0.pinmask=0x00001803 103*a9643ea8Slogwang 104*a9643ea8Slogwang# XXX TODO: the button and LEDs! 105*a9643ea8Slogwang 106