1a9643ea8Slogwang /*- 2a9643ea8Slogwang * Copyright 2014 Svatopluk Kraus <[email protected]> 3a9643ea8Slogwang * Copyright 2014 Michal Meloun <[email protected]> 4a9643ea8Slogwang * All rights reserved. 5a9643ea8Slogwang * 6a9643ea8Slogwang * Redistribution and use in source and binary forms, with or without 7a9643ea8Slogwang * modification, are permitted provided that the following conditions 8a9643ea8Slogwang * are met: 9a9643ea8Slogwang * 1. Redistributions of source code must retain the above copyright 10a9643ea8Slogwang * notice, this list of conditions and the following disclaimer. 11a9643ea8Slogwang * 2. Redistributions in binary form must reproduce the above copyright 12a9643ea8Slogwang * notice, this list of conditions and the following disclaimer in the 13a9643ea8Slogwang * documentation and/or other materials provided with the distribution. 14a9643ea8Slogwang * 15a9643ea8Slogwang * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16a9643ea8Slogwang * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17a9643ea8Slogwang * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18a9643ea8Slogwang * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19a9643ea8Slogwang * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20a9643ea8Slogwang * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21a9643ea8Slogwang * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22a9643ea8Slogwang * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23a9643ea8Slogwang * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24a9643ea8Slogwang * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25a9643ea8Slogwang * SUCH DAMAGE. 26a9643ea8Slogwang * 27a9643ea8Slogwang * $FreeBSD$ 28a9643ea8Slogwang */ 29a9643ea8Slogwang 30a9643ea8Slogwang /* 31a9643ea8Slogwang * Macros to make working with the System Control Registers simpler. 32a9643ea8Slogwang * 33a9643ea8Slogwang * Note that when register r0 is hard-coded in these definitions it means the 34a9643ea8Slogwang * cp15 operation neither reads nor writes the register, and r0 is used only 35a9643ea8Slogwang * because some syntatically-valid register name has to appear at that point to 36a9643ea8Slogwang * keep the asm parser happy. 37a9643ea8Slogwang */ 38a9643ea8Slogwang 39a9643ea8Slogwang #ifndef MACHINE_SYSREG_H 40a9643ea8Slogwang #define MACHINE_SYSREG_H 41a9643ea8Slogwang 42a9643ea8Slogwang /* 43a9643ea8Slogwang * CP14 registers 44a9643ea8Slogwang */ 45a9643ea8Slogwang #define CP14_DBGDIDR(rr) p14, 0, rr, c0, c0, 0 /* Debug ID Register */ 46a9643ea8Slogwang #define CP14_DBGDSCRext_V6(rr) p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */ 47a9643ea8Slogwang #define CP14_DBGDSCRext_V7(rr) p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */ 48a9643ea8Slogwang #define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */ 49a9643ea8Slogwang #define CP14_DBGOSLAR(rr) p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */ 50a9643ea8Slogwang #define CP14_DBGOSLSR(rr) p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */ 51a9643ea8Slogwang #define CP14_DBGOSDLR(rr) p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */ 52a9643ea8Slogwang #define CP14_DBGPRSR(rr) p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */ 53a9643ea8Slogwang 54a9643ea8Slogwang #define CP14_DBGDSCRint(rr) CP14_DBGDSCRext_V6(rr) /* Debug Status and Ctrl internal view */ 55a9643ea8Slogwang 56a9643ea8Slogwang /* 57a9643ea8Slogwang * CP15 C0 registers 58a9643ea8Slogwang */ 59a9643ea8Slogwang #define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ 60a9643ea8Slogwang #define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ 61a9643ea8Slogwang #define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ 62a9643ea8Slogwang #define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ 63a9643ea8Slogwang #define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ 64a9643ea8Slogwang #define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ 65a9643ea8Slogwang 66a9643ea8Slogwang #define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */ 67a9643ea8Slogwang #define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */ 68a9643ea8Slogwang #define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */ 69a9643ea8Slogwang #define CP15_ID_AFR0(rr) p15, 0, rr, c0, c1, 3 /* Auxiliary Feature Register 0 */ 70a9643ea8Slogwang #define CP15_ID_MMFR0(rr) p15, 0, rr, c0, c1, 4 /* Memory Model Feature Register 0 */ 71a9643ea8Slogwang #define CP15_ID_MMFR1(rr) p15, 0, rr, c0, c1, 5 /* Memory Model Feature Register 1 */ 72a9643ea8Slogwang #define CP15_ID_MMFR2(rr) p15, 0, rr, c0, c1, 6 /* Memory Model Feature Register 2 */ 73a9643ea8Slogwang #define CP15_ID_MMFR3(rr) p15, 0, rr, c0, c1, 7 /* Memory Model Feature Register 3 */ 74a9643ea8Slogwang 75a9643ea8Slogwang #define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ 76a9643ea8Slogwang #define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ 77a9643ea8Slogwang #define CP15_ID_ISAR2(rr) p15, 0, rr, c0, c2, 2 /* Instruction Set Attribute Register 2 */ 78a9643ea8Slogwang #define CP15_ID_ISAR3(rr) p15, 0, rr, c0, c2, 3 /* Instruction Set Attribute Register 3 */ 79a9643ea8Slogwang #define CP15_ID_ISAR4(rr) p15, 0, rr, c0, c2, 4 /* Instruction Set Attribute Register 4 */ 80a9643ea8Slogwang #define CP15_ID_ISAR5(rr) p15, 0, rr, c0, c2, 5 /* Instruction Set Attribute Register 5 */ 81a9643ea8Slogwang 82a9643ea8Slogwang #define CP15_CCSIDR(rr) p15, 1, rr, c0, c0, 0 /* Cache Size ID Registers */ 83a9643ea8Slogwang #define CP15_CLIDR(rr) p15, 1, rr, c0, c0, 1 /* Cache Level ID Register */ 84a9643ea8Slogwang #define CP15_AIDR(rr) p15, 1, rr, c0, c0, 7 /* Auxiliary ID Register */ 85a9643ea8Slogwang 86a9643ea8Slogwang #define CP15_CSSELR(rr) p15, 2, rr, c0, c0, 0 /* Cache Size Selection Register */ 87a9643ea8Slogwang 88*22ce4affSfengbojiang #define CP15_VPIDR(rr) p15, 4, rr, c0, c0, 0 /* Virtualization Processor ID Register */ 89*22ce4affSfengbojiang #define CP15_VMPIDR(rr) p15, 4, rr, c0, c0, 5 /* Virtualization Multiprocessor ID Register */ 90*22ce4affSfengbojiang 91a9643ea8Slogwang /* 92a9643ea8Slogwang * CP15 C1 registers 93a9643ea8Slogwang */ 94a9643ea8Slogwang #define CP15_SCTLR(rr) p15, 0, rr, c1, c0, 0 /* System Control Register */ 95a9643ea8Slogwang #define CP15_ACTLR(rr) p15, 0, rr, c1, c0, 1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */ 96a9643ea8Slogwang #define CP15_CPACR(rr) p15, 0, rr, c1, c0, 2 /* Coprocessor Access Control Register */ 97a9643ea8Slogwang 98a9643ea8Slogwang #define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */ 99a9643ea8Slogwang #define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */ 100a9643ea8Slogwang #define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */ 101a9643ea8Slogwang 102*22ce4affSfengbojiang #define CP15_HSCTLR(rr) p15, 4, rr, c1, c0, 0 /* Hyp System Control Register */ 103*22ce4affSfengbojiang 104*22ce4affSfengbojiang #define CP15_HCR(rr) p15, 4, rr, c1, c1, 0 /* Hyp Configuration Register */ 105*22ce4affSfengbojiang #define CP15_HDCR(rr) p15, 4, rr, c1, c1, 1 /* Hyp Debug Configuration Register */ 106*22ce4affSfengbojiang #define CP15_HCPTR(rr) p15, 4, rr, c1, c1, 2 /* Hyp Coprocessor Trap Register */ 107*22ce4affSfengbojiang #define CP15_HSTR(rr) p15, 4, rr, c1, c1, 3 /* Hyp System Trap Register */ 108*22ce4affSfengbojiang 109a9643ea8Slogwang /* 110a9643ea8Slogwang * CP15 C2 registers 111a9643ea8Slogwang */ 112a9643ea8Slogwang #define CP15_TTBR0(rr) p15, 0, rr, c2, c0, 0 /* Translation Table Base Register 0 */ 113a9643ea8Slogwang #define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ 114a9643ea8Slogwang #define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ 115a9643ea8Slogwang 116*22ce4affSfengbojiang #define CP15_HTCR(rr) p15, 4, rr, c2, c0, 2 /* Hyp Translation Control Register */ 117*22ce4affSfengbojiang #define CP15_VTCR(rr) p15, 4, rr, c2, c1, 2 /* Virtualization Translation Control Register */ 118*22ce4affSfengbojiang 119a9643ea8Slogwang /* 120a9643ea8Slogwang * CP15 C3 registers 121a9643ea8Slogwang */ 122a9643ea8Slogwang #define CP15_DACR(rr) p15, 0, rr, c3, c0, 0 /* Domain Access Control Register */ 123a9643ea8Slogwang 124a9643ea8Slogwang /* 125a9643ea8Slogwang * CP15 C5 registers 126a9643ea8Slogwang */ 127a9643ea8Slogwang #define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ 128*22ce4affSfengbojiang #define CP15_HSR(rr) p15, 4, rr, c5, c2, 0 /* Hyp Syndrome Register */ 129a9643ea8Slogwang 130a9643ea8Slogwang /* From ARMv6: */ 131a9643ea8Slogwang #define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */ 132a9643ea8Slogwang #if __ARM_ARCH >= 7 133a9643ea8Slogwang /* From ARMv7: */ 134a9643ea8Slogwang #define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */ 135a9643ea8Slogwang #define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */ 136a9643ea8Slogwang #endif 137a9643ea8Slogwang 138a9643ea8Slogwang /* 139a9643ea8Slogwang * CP15 C6 registers 140a9643ea8Slogwang */ 141a9643ea8Slogwang #define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ 142*22ce4affSfengbojiang #define CP15_HDFAR(rr) p15, 4, rr, c6, c0, 0 /* Hyp Data Fault Address Register */ 143*22ce4affSfengbojiang #define CP15_HIFAR(rr) p15, 4, rr, c6, c0, 2 /* Hyp Instruction Fault Address Register */ 144*22ce4affSfengbojiang #define CP15_HPFAR(rr) p15, 4, rr, c6, c0, 4 /* Hyp IPA Fault Address Register */ 145a9643ea8Slogwang 146a9643ea8Slogwang /* From ARMv6k: */ 147a9643ea8Slogwang #define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ 148a9643ea8Slogwang 149a9643ea8Slogwang /* 150a9643ea8Slogwang * CP15 C7 registers 151a9643ea8Slogwang */ 152a9643ea8Slogwang #if __ARM_ARCH >= 7 && defined(SMP) 153a9643ea8Slogwang /* From ARMv7: */ 154a9643ea8Slogwang #define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ 155a9643ea8Slogwang #define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ 156a9643ea8Slogwang #endif 157a9643ea8Slogwang 158a9643ea8Slogwang #define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */ 159a9643ea8Slogwang 160a9643ea8Slogwang #define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ 161a9643ea8Slogwang #define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */ 162a9643ea8Slogwang #if __ARM_ARCH == 6 163a9643ea8Slogwang /* Deprecated in ARMv7 */ 164a9643ea8Slogwang #define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */ 165a9643ea8Slogwang #endif 166a9643ea8Slogwang #define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */ 167a9643ea8Slogwang #define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */ 168a9643ea8Slogwang 169a9643ea8Slogwang #if __ARM_ARCH == 6 170a9643ea8Slogwang /* Only ARMv6: */ 171a9643ea8Slogwang #define CP15_DCIALL p15, 0, r0, c7, c6, 0 /* Data cache invalidate all */ 172a9643ea8Slogwang #endif 173a9643ea8Slogwang #define CP15_DCIMVAC(rr) p15, 0, rr, c7, c6, 1 /* Data cache invalidate by MVA PoC */ 174a9643ea8Slogwang #define CP15_DCISW(rr) p15, 0, rr, c7, c6, 2 /* Data cache invalidate by set/way */ 175a9643ea8Slogwang 176a9643ea8Slogwang #define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */ 177a9643ea8Slogwang #define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */ 178a9643ea8Slogwang #define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */ 179a9643ea8Slogwang #define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */ 180a9643ea8Slogwang 181a9643ea8Slogwang #if __ARM_ARCH >= 7 182a9643ea8Slogwang /* From ARMv7: */ 183a9643ea8Slogwang #define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ 184a9643ea8Slogwang #define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ 185a9643ea8Slogwang #define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */ 186a9643ea8Slogwang #define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */ 187a9643ea8Slogwang #endif 188a9643ea8Slogwang 189a9643ea8Slogwang #if __ARM_ARCH == 6 190a9643ea8Slogwang /* Only ARMv6: */ 191a9643ea8Slogwang #define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */ 192a9643ea8Slogwang #endif 193a9643ea8Slogwang #define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ 194a9643ea8Slogwang #define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ 195a9643ea8Slogwang #if __ARM_ARCH == 6 196a9643ea8Slogwang /* Only ARMv6: */ 197a9643ea8Slogwang #define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */ 198a9643ea8Slogwang #define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */ 199a9643ea8Slogwang #define CP15_CP15WFI p15, 0, r0, c7, c0, 4 /* WFI */ 200a9643ea8Slogwang #endif 201a9643ea8Slogwang 202a9643ea8Slogwang #if __ARM_ARCH >= 7 203a9643ea8Slogwang /* From ARMv7: */ 204a9643ea8Slogwang #define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ 205a9643ea8Slogwang #endif 206a9643ea8Slogwang 207a9643ea8Slogwang #if __ARM_ARCH == 6 208a9643ea8Slogwang /* Only ARMv6: */ 209a9643ea8Slogwang #define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */ 210a9643ea8Slogwang #endif 211a9643ea8Slogwang #define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ 212a9643ea8Slogwang #define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ 213a9643ea8Slogwang 214a9643ea8Slogwang /* 215a9643ea8Slogwang * CP15 C8 registers 216a9643ea8Slogwang */ 217a9643ea8Slogwang #if __ARM_ARCH >= 7 && defined(SMP) 218a9643ea8Slogwang /* From ARMv7: */ 219a9643ea8Slogwang #define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ 220a9643ea8Slogwang #define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ 221a9643ea8Slogwang #define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ 222a9643ea8Slogwang #define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ 223a9643ea8Slogwang #endif 224a9643ea8Slogwang 225a9643ea8Slogwang #define CP15_TLBIALL p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */ 226a9643ea8Slogwang #define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ 227a9643ea8Slogwang #define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ 228a9643ea8Slogwang 229*22ce4affSfengbojiang #define CP15_TLBIALLH(rr) p15, 4, rr, c8, c7, 0 /* Invalidate Entire Hyp Unified TLB */ 230*22ce4affSfengbojiang 231a9643ea8Slogwang /* From ARMv6: */ 232a9643ea8Slogwang #define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ 233a9643ea8Slogwang 234a9643ea8Slogwang /* 235a9643ea8Slogwang * CP15 C9 registers 236a9643ea8Slogwang */ 237a9643ea8Slogwang #if __ARM_ARCH == 6 && defined(CPU_ARM1176) 238a9643ea8Slogwang #define CP15_PMUSERENR(rr) p15, 0, rr, c15, c9, 0 /* Access Validation Control Register */ 239a9643ea8Slogwang #define CP15_PMCR(rr) p15, 0, rr, c15, c12, 0 /* Performance Monitor Control Register */ 240a9643ea8Slogwang #define CP15_PMCCNTR(rr) p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */ 241*22ce4affSfengbojiang #else 242a9643ea8Slogwang #define CP15_L2CTLR(rr) p15, 1, rr, c9, c0, 2 /* L2 Control Register */ 243a9643ea8Slogwang #define CP15_PMCR(rr) p15, 0, rr, c9, c12, 0 /* Performance Monitor Control Register */ 244a9643ea8Slogwang #define CP15_PMCNTENSET(rr) p15, 0, rr, c9, c12, 1 /* PM Count Enable Set Register */ 245a9643ea8Slogwang #define CP15_PMCNTENCLR(rr) p15, 0, rr, c9, c12, 2 /* PM Count Enable Clear Register */ 246a9643ea8Slogwang #define CP15_PMOVSR(rr) p15, 0, rr, c9, c12, 3 /* PM Overflow Flag Status Register */ 247a9643ea8Slogwang #define CP15_PMSWINC(rr) p15, 0, rr, c9, c12, 4 /* PM Software Increment Register */ 248a9643ea8Slogwang #define CP15_PMSELR(rr) p15, 0, rr, c9, c12, 5 /* PM Event Counter Selection Register */ 249a9643ea8Slogwang #define CP15_PMCCNTR(rr) p15, 0, rr, c9, c13, 0 /* PM Cycle Count Register */ 250a9643ea8Slogwang #define CP15_PMXEVTYPER(rr) p15, 0, rr, c9, c13, 1 /* PM Event Type Select Register */ 251a9643ea8Slogwang #define CP15_PMXEVCNTRR(rr) p15, 0, rr, c9, c13, 2 /* PM Event Count Register */ 252a9643ea8Slogwang #define CP15_PMUSERENR(rr) p15, 0, rr, c9, c14, 0 /* PM User Enable Register */ 253a9643ea8Slogwang #define CP15_PMINTENSET(rr) p15, 0, rr, c9, c14, 1 /* PM Interrupt Enable Set Register */ 254a9643ea8Slogwang #define CP15_PMINTENCLR(rr) p15, 0, rr, c9, c14, 2 /* PM Interrupt Enable Clear Register */ 255a9643ea8Slogwang #endif 256a9643ea8Slogwang 257a9643ea8Slogwang /* 258a9643ea8Slogwang * CP15 C10 registers 259a9643ea8Slogwang */ 260a9643ea8Slogwang /* Without LPAE this is PRRR, with LPAE it's MAIR0 */ 261a9643ea8Slogwang #define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ 262a9643ea8Slogwang #define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ 263a9643ea8Slogwang /* Without LPAE this is NMRR, with LPAE it's MAIR1 */ 264a9643ea8Slogwang #define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ 265a9643ea8Slogwang #define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ 266a9643ea8Slogwang 267a9643ea8Slogwang #define CP15_AMAIR0(rr) p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */ 268a9643ea8Slogwang #define CP15_AMAIR1(rr) p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */ 269a9643ea8Slogwang 270*22ce4affSfengbojiang #define CP15_HMAIR0(rr) p15, 4, rr, c10, c2, 0 /* Hyp Memory Attribute Indirection Register 0 */ 271*22ce4affSfengbojiang #define CP15_HMAIR1(rr) p15, 4, rr, c10, c2, 1 /* Hyp Memory Attribute Indirection Register 1 */ 272*22ce4affSfengbojiang 273a9643ea8Slogwang /* 274a9643ea8Slogwang * CP15 C12 registers 275a9643ea8Slogwang */ 276a9643ea8Slogwang #define CP15_VBAR(rr) p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */ 277a9643ea8Slogwang #define CP15_MVBAR(rr) p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */ 278a9643ea8Slogwang 279a9643ea8Slogwang #define CP15_ISR(rr) p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */ 280*22ce4affSfengbojiang #define CP15_HVBAR(rr) p15, 4, rr, c12, c0, 0 /* Hyp Vector Base Address Register*/ 281a9643ea8Slogwang 282a9643ea8Slogwang /* 283a9643ea8Slogwang * CP15 C13 registers 284a9643ea8Slogwang */ 285a9643ea8Slogwang #define CP15_FCSEIDR(rr) p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */ 286a9643ea8Slogwang #define CP15_CONTEXTIDR(rr) p15, 0, rr, c13, c0, 1 /* Context ID Register */ 287a9643ea8Slogwang #define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ 288a9643ea8Slogwang #define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ 289a9643ea8Slogwang #define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ 290*22ce4affSfengbojiang #define CP15_HTPIDR(rr) p15, 4, rr, c13, c0, 2 /* Hyp Software Thread ID Register */ 291a9643ea8Slogwang 292a9643ea8Slogwang /* 293a9643ea8Slogwang * CP15 C14 registers 294a9643ea8Slogwang * These are the Generic Timer registers and may be unallocated on some SoCs. 295a9643ea8Slogwang * Only use these when you know the Generic Timer is available. 296a9643ea8Slogwang */ 297a9643ea8Slogwang #define CP15_CNTFRQ(rr) p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */ 298a9643ea8Slogwang #define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */ 299a9643ea8Slogwang #define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */ 300a9643ea8Slogwang #define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */ 301a9643ea8Slogwang #define CP15_CNTV_TVAL(rr) p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */ 302a9643ea8Slogwang #define CP15_CNTV_CTL(rr) p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */ 303a9643ea8Slogwang #define CP15_CNTHCTL(rr) p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */ 304a9643ea8Slogwang #define CP15_CNTHP_TVAL(rr) p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */ 305a9643ea8Slogwang #define CP15_CNTHP_CTL(rr) p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */ 306a9643ea8Slogwang /* 64-bit registers for use with mcrr/mrrc */ 307a9643ea8Slogwang #define CP15_CNTPCT(rq, rr) p15, 0, rq, rr, c14 /* Physical Count Register */ 308a9643ea8Slogwang #define CP15_CNTVCT(rq, rr) p15, 1, rq, rr, c14 /* Virtual Count Register */ 309a9643ea8Slogwang #define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */ 310a9643ea8Slogwang #define CP15_CNTV_CVAL(rq, rr) p15, 3, rq, rr, c14 /* Virtual Timer Compare Value Register */ 311a9643ea8Slogwang #define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */ 312a9643ea8Slogwang #define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */ 313a9643ea8Slogwang 314*22ce4affSfengbojiang #define CP15_VTTBR(rq, rr) p15, 6, rq, rr, c2 /* Virtualization Translation Table Base Register */ 315*22ce4affSfengbojiang #define CP15_HTTBR(rq, rr) p15, 4, rq, rr, c2 /* Hyp Translation Table Base Register */ 316*22ce4affSfengbojiang #define CP15_TTBR0_2(rq, rr) p15, 0, rq, rr, c2 /* Translation Table Base Register 0 */ 317*22ce4affSfengbojiang #define CP15_TTBR1_2(rq, rr) p15, 1, rq, rr, c2 /* Translation Table Base Register 1 */ 318*22ce4affSfengbojiang #define CP15_PAR_2(rq, rr) p15, 0, rq, rr, c7 /* Physical Address Register */ 319*22ce4affSfengbojiang 320a9643ea8Slogwang /* 321a9643ea8Slogwang * CP15 C15 registers 322a9643ea8Slogwang */ 323a9643ea8Slogwang #define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */ 324a9643ea8Slogwang 325a9643ea8Slogwang #endif /* !MACHINE_SYSREG_H */ 326