xref: /f-stack/freebsd/amd64/include/pcpu.h (revision 22ce4aff)
1a9643ea8Slogwang /*-
2*22ce4affSfengbojiang  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3*22ce4affSfengbojiang  *
4a9643ea8Slogwang  * Copyright (c) Peter Wemm <[email protected]>
5a9643ea8Slogwang  * All rights reserved.
6a9643ea8Slogwang  *
7a9643ea8Slogwang  * Redistribution and use in source and binary forms, with or without
8a9643ea8Slogwang  * modification, are permitted provided that the following conditions
9a9643ea8Slogwang  * are met:
10a9643ea8Slogwang  * 1. Redistributions of source code must retain the above copyright
11a9643ea8Slogwang  *    notice, this list of conditions and the following disclaimer.
12a9643ea8Slogwang  * 2. Redistributions in binary form must reproduce the above copyright
13a9643ea8Slogwang  *    notice, this list of conditions and the following disclaimer in the
14a9643ea8Slogwang  *    documentation and/or other materials provided with the distribution.
15a9643ea8Slogwang  *
16a9643ea8Slogwang  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17a9643ea8Slogwang  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18a9643ea8Slogwang  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19a9643ea8Slogwang  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20a9643ea8Slogwang  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21a9643ea8Slogwang  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22a9643ea8Slogwang  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23a9643ea8Slogwang  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24a9643ea8Slogwang  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25a9643ea8Slogwang  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26a9643ea8Slogwang  * SUCH DAMAGE.
27a9643ea8Slogwang  *
28a9643ea8Slogwang  * $FreeBSD$
29a9643ea8Slogwang  */
30a9643ea8Slogwang 
31a9643ea8Slogwang #ifndef _MACHINE_PCPU_H_
32a9643ea8Slogwang #define	_MACHINE_PCPU_H_
33a9643ea8Slogwang 
34a9643ea8Slogwang #ifndef _SYS_CDEFS_H_
35a9643ea8Slogwang #error "sys/cdefs.h is a prerequisite for this file"
36a9643ea8Slogwang #endif
37a9643ea8Slogwang 
38*22ce4affSfengbojiang #include <machine/segments.h>
39*22ce4affSfengbojiang #include <machine/tss.h>
40*22ce4affSfengbojiang 
41*22ce4affSfengbojiang #define	PC_PTI_STACK_SZ	16
42*22ce4affSfengbojiang 
43*22ce4affSfengbojiang struct monitorbuf {
44*22ce4affSfengbojiang 	int idle_state;		/* Used by cpu_idle_mwait. */
45*22ce4affSfengbojiang 	int stop_state;		/* Used by cpustop_handler. */
46*22ce4affSfengbojiang 	char padding[128 - (2 * sizeof(int))];
47*22ce4affSfengbojiang };
48*22ce4affSfengbojiang _Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line");
49*22ce4affSfengbojiang 
50a9643ea8Slogwang /*
51a9643ea8Slogwang  * The SMP parts are setup in pmap.c and locore.s for the BSP, and
52a9643ea8Slogwang  * mp_machdep.c sets up the data for the AP's to "see" when they awake.
53a9643ea8Slogwang  * The reason for doing it via a struct is so that an array of pointers
54a9643ea8Slogwang  * to each CPU's data can be set up for things like "check curproc on all
55a9643ea8Slogwang  * other processors"
56a9643ea8Slogwang  */
57a9643ea8Slogwang #define	PCPU_MD_FIELDS							\
58*22ce4affSfengbojiang 	struct monitorbuf pc_monitorbuf __aligned(128);	/* cache line */\
59a9643ea8Slogwang 	struct	pcpu *pc_prvspace;	/* Self-reference */		\
60a9643ea8Slogwang 	struct	pmap *pc_curpmap;					\
61a9643ea8Slogwang 	struct	amd64tss *pc_tssp;	/* TSS segment active on CPU */	\
62*22ce4affSfengbojiang 	void	*pc_pad0;						\
63*22ce4affSfengbojiang 	uint64_t pc_kcr3;						\
64*22ce4affSfengbojiang 	uint64_t pc_ucr3;						\
65*22ce4affSfengbojiang 	uint64_t pc_saved_ucr3;						\
66a9643ea8Slogwang 	register_t pc_rsp0;						\
67a9643ea8Slogwang 	register_t pc_scratch_rsp;	/* User %rsp in syscall */	\
68*22ce4affSfengbojiang 	register_t pc_scratch_rax;					\
69a9643ea8Slogwang 	u_int	pc_apic_id;						\
70a9643ea8Slogwang 	u_int   pc_acpi_id;		/* ACPI CPU id */		\
71a9643ea8Slogwang 	/* Pointer to the CPU %fs descriptor */				\
72a9643ea8Slogwang 	struct user_segment_descriptor	*pc_fs32p;			\
73a9643ea8Slogwang 	/* Pointer to the CPU %gs descriptor */				\
74a9643ea8Slogwang 	struct user_segment_descriptor	*pc_gs32p;			\
75a9643ea8Slogwang 	/* Pointer to the CPU LDT descriptor */				\
76a9643ea8Slogwang 	struct system_segment_descriptor *pc_ldt;			\
77a9643ea8Slogwang 	/* Pointer to the CPU TSS descriptor */				\
78a9643ea8Slogwang 	struct system_segment_descriptor *pc_tss;			\
79a9643ea8Slogwang 	uint64_t	pc_pm_save_cnt;					\
80a9643ea8Slogwang 	u_int	pc_cmci_mask;		/* MCx banks for CMCI */	\
81a9643ea8Slogwang 	uint64_t pc_dbreg[16];		/* ddb debugging regs */	\
82*22ce4affSfengbojiang 	uint64_t pc_pti_stack[PC_PTI_STACK_SZ];				\
83*22ce4affSfengbojiang 	register_t pc_pti_rsp0;						\
84a9643ea8Slogwang 	int pc_dbreg_cmd;		/* ddb debugging reg cmd */	\
85a9643ea8Slogwang 	u_int	pc_vcpu_id;		/* Xen vCPU ID */		\
86a9643ea8Slogwang 	uint32_t pc_pcid_next;						\
87a9643ea8Slogwang 	uint32_t pc_pcid_gen;						\
88*22ce4affSfengbojiang 	uint32_t pc_unused;						\
89*22ce4affSfengbojiang 	uint32_t pc_ibpb_set;						\
90*22ce4affSfengbojiang 	void	*pc_mds_buf;						\
91*22ce4affSfengbojiang 	void	*pc_mds_buf64;						\
92*22ce4affSfengbojiang 	uint32_t pc_pad[2];						\
93*22ce4affSfengbojiang 	uint8_t	pc_mds_tmp[64];						\
94*22ce4affSfengbojiang 	u_int 	pc_ipi_bitmap;						\
95*22ce4affSfengbojiang 	struct amd64tss pc_common_tss;					\
96*22ce4affSfengbojiang 	struct user_segment_descriptor pc_gdt[NGDT];			\
97*22ce4affSfengbojiang 	void	*pc_smp_tlb_pmap;					\
98*22ce4affSfengbojiang 	uint64_t pc_smp_tlb_addr1;					\
99*22ce4affSfengbojiang 	uint64_t pc_smp_tlb_addr2;					\
100*22ce4affSfengbojiang 	uint32_t pc_smp_tlb_gen;					\
101*22ce4affSfengbojiang 	u_int	pc_smp_tlb_op;						\
102*22ce4affSfengbojiang 	uint64_t pc_ucr3_load_mask;					\
103*22ce4affSfengbojiang 	char	__pad[2916]		/* pad to UMA_PCPU_ALLOC_SIZE */
104a9643ea8Slogwang 
105a9643ea8Slogwang #define	PC_DBREG_CMD_NONE	0
106a9643ea8Slogwang #define	PC_DBREG_CMD_LOAD	1
107a9643ea8Slogwang 
108a9643ea8Slogwang #ifdef _KERNEL
109a9643ea8Slogwang 
110*22ce4affSfengbojiang #define MONITOR_STOPSTATE_RUNNING	0
111*22ce4affSfengbojiang #define MONITOR_STOPSTATE_STOPPED	1
112a9643ea8Slogwang 
113*22ce4affSfengbojiang #if defined(__GNUCLIKE_ASM) && defined(__GNUCLIKE___TYPEOF)
114a9643ea8Slogwang 
115a9643ea8Slogwang /*
116a9643ea8Slogwang  * Evaluates to the byte offset of the per-cpu variable name.
117a9643ea8Slogwang  */
118a9643ea8Slogwang #define	__pcpu_offset(name)						\
119a9643ea8Slogwang 	__offsetof(struct pcpu, name)
120a9643ea8Slogwang 
121a9643ea8Slogwang /*
122a9643ea8Slogwang  * Evaluates to the type of the per-cpu variable name.
123a9643ea8Slogwang  */
124a9643ea8Slogwang #define	__pcpu_type(name)						\
125a9643ea8Slogwang 	__typeof(((struct pcpu *)0)->name)
126a9643ea8Slogwang 
127a9643ea8Slogwang /*
128a9643ea8Slogwang  * Evaluates to the address of the per-cpu variable name.
129a9643ea8Slogwang  */
130a9643ea8Slogwang #define	__PCPU_PTR(name) __extension__ ({				\
131a9643ea8Slogwang 	__pcpu_type(name) *__p;						\
132a9643ea8Slogwang 									\
133a9643ea8Slogwang 	__asm __volatile("movq %%gs:%1,%0; addq %2,%0"			\
134a9643ea8Slogwang 	    : "=r" (__p)						\
135a9643ea8Slogwang 	    : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))),	\
136a9643ea8Slogwang 	      "i" (__pcpu_offset(name)));				\
137a9643ea8Slogwang 									\
138a9643ea8Slogwang 	__p;								\
139a9643ea8Slogwang })
140a9643ea8Slogwang 
141a9643ea8Slogwang /*
142a9643ea8Slogwang  * Evaluates to the value of the per-cpu variable name.
143a9643ea8Slogwang  */
144a9643ea8Slogwang #define	__PCPU_GET(name) __extension__ ({				\
145a9643ea8Slogwang 	__pcpu_type(name) __res;					\
146a9643ea8Slogwang 	struct __s {							\
147a9643ea8Slogwang 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
148a9643ea8Slogwang 	} __s;								\
149a9643ea8Slogwang 									\
150a9643ea8Slogwang 	if (sizeof(__res) == 1 || sizeof(__res) == 2 ||			\
151a9643ea8Slogwang 	    sizeof(__res) == 4 || sizeof(__res) == 8) {			\
152a9643ea8Slogwang 		__asm __volatile("mov %%gs:%1,%0"			\
153a9643ea8Slogwang 		    : "=r" (__s)					\
154a9643ea8Slogwang 		    : "m" (*(struct __s *)(__pcpu_offset(name))));	\
155a9643ea8Slogwang 		*(struct __s *)(void *)&__res = __s;			\
156a9643ea8Slogwang 	} else {							\
157a9643ea8Slogwang 		__res = *__PCPU_PTR(name);				\
158a9643ea8Slogwang 	}								\
159a9643ea8Slogwang 	__res;								\
160a9643ea8Slogwang })
161a9643ea8Slogwang 
162a9643ea8Slogwang /*
163a9643ea8Slogwang  * Adds the value to the per-cpu counter name.  The implementation
164a9643ea8Slogwang  * must be atomic with respect to interrupts.
165a9643ea8Slogwang  */
166a9643ea8Slogwang #define	__PCPU_ADD(name, val) do {					\
167a9643ea8Slogwang 	__pcpu_type(name) __val;					\
168a9643ea8Slogwang 	struct __s {							\
169a9643ea8Slogwang 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
170a9643ea8Slogwang 	} __s;								\
171a9643ea8Slogwang 									\
172a9643ea8Slogwang 	__val = (val);							\
173a9643ea8Slogwang 	if (sizeof(__val) == 1 || sizeof(__val) == 2 ||			\
174a9643ea8Slogwang 	    sizeof(__val) == 4 || sizeof(__val) == 8) {			\
175a9643ea8Slogwang 		__s = *(struct __s *)(void *)&__val;			\
176a9643ea8Slogwang 		__asm __volatile("add %1,%%gs:%0"			\
177a9643ea8Slogwang 		    : "=m" (*(struct __s *)(__pcpu_offset(name)))	\
178a9643ea8Slogwang 		    : "r" (__s));					\
179a9643ea8Slogwang 	} else								\
180a9643ea8Slogwang 		*__PCPU_PTR(name) += __val;				\
181a9643ea8Slogwang } while (0)
182a9643ea8Slogwang 
183a9643ea8Slogwang /*
184a9643ea8Slogwang  * Increments the value of the per-cpu counter name.  The implementation
185a9643ea8Slogwang  * must be atomic with respect to interrupts.
186a9643ea8Slogwang  */
187a9643ea8Slogwang #define	__PCPU_INC(name) do {						\
188a9643ea8Slogwang 	CTASSERT(sizeof(__pcpu_type(name)) == 1 ||			\
189a9643ea8Slogwang 	    sizeof(__pcpu_type(name)) == 2 ||				\
190a9643ea8Slogwang 	    sizeof(__pcpu_type(name)) == 4 ||				\
191a9643ea8Slogwang 	    sizeof(__pcpu_type(name)) == 8);				\
192a9643ea8Slogwang 	if (sizeof(__pcpu_type(name)) == 1) {				\
193a9643ea8Slogwang 		__asm __volatile("incb %%gs:%0"				\
194a9643ea8Slogwang 		    : "=m" (*(__pcpu_type(name) *)(__pcpu_offset(name)))\
195a9643ea8Slogwang 		    : "m" (*(__pcpu_type(name) *)(__pcpu_offset(name))));\
196a9643ea8Slogwang 	} else if (sizeof(__pcpu_type(name)) == 2) {			\
197a9643ea8Slogwang 		__asm __volatile("incw %%gs:%0"				\
198a9643ea8Slogwang 		    : "=m" (*(__pcpu_type(name) *)(__pcpu_offset(name)))\
199a9643ea8Slogwang 		    : "m" (*(__pcpu_type(name) *)(__pcpu_offset(name))));\
200a9643ea8Slogwang 	} else if (sizeof(__pcpu_type(name)) == 4) {			\
201a9643ea8Slogwang 		__asm __volatile("incl %%gs:%0"				\
202a9643ea8Slogwang 		    : "=m" (*(__pcpu_type(name) *)(__pcpu_offset(name)))\
203a9643ea8Slogwang 		    : "m" (*(__pcpu_type(name) *)(__pcpu_offset(name))));\
204a9643ea8Slogwang 	} else if (sizeof(__pcpu_type(name)) == 8) {			\
205a9643ea8Slogwang 		__asm __volatile("incq %%gs:%0"				\
206a9643ea8Slogwang 		    : "=m" (*(__pcpu_type(name) *)(__pcpu_offset(name)))\
207a9643ea8Slogwang 		    : "m" (*(__pcpu_type(name) *)(__pcpu_offset(name))));\
208a9643ea8Slogwang 	}								\
209a9643ea8Slogwang } while (0)
210a9643ea8Slogwang 
211a9643ea8Slogwang /*
212a9643ea8Slogwang  * Sets the value of the per-cpu variable name to value val.
213a9643ea8Slogwang  */
214a9643ea8Slogwang #define	__PCPU_SET(name, val) {						\
215a9643ea8Slogwang 	__pcpu_type(name) __val;					\
216a9643ea8Slogwang 	struct __s {							\
217a9643ea8Slogwang 		u_char	__b[MIN(sizeof(__pcpu_type(name)), 8)];		\
218a9643ea8Slogwang 	} __s;								\
219a9643ea8Slogwang 									\
220a9643ea8Slogwang 	__val = (val);							\
221a9643ea8Slogwang 	if (sizeof(__val) == 1 || sizeof(__val) == 2 ||			\
222a9643ea8Slogwang 	    sizeof(__val) == 4 || sizeof(__val) == 8) {			\
223a9643ea8Slogwang 		__s = *(struct __s *)(void *)&__val;			\
224a9643ea8Slogwang 		__asm __volatile("mov %1,%%gs:%0"			\
225a9643ea8Slogwang 		    : "=m" (*(struct __s *)(__pcpu_offset(name)))	\
226a9643ea8Slogwang 		    : "r" (__s));					\
227a9643ea8Slogwang 	} else {							\
228a9643ea8Slogwang 		*__PCPU_PTR(name) = __val;				\
229a9643ea8Slogwang 	}								\
230a9643ea8Slogwang }
231a9643ea8Slogwang 
232*22ce4affSfengbojiang #define	get_pcpu() __extension__ ({					\
233*22ce4affSfengbojiang 	struct pcpu *__pc;						\
234*22ce4affSfengbojiang 									\
235*22ce4affSfengbojiang 	__asm __volatile("movq %%gs:%1,%0"				\
236*22ce4affSfengbojiang 	    : "=r" (__pc)						\
237*22ce4affSfengbojiang 	    : "m" (*(struct pcpu *)(__pcpu_offset(pc_prvspace))));	\
238*22ce4affSfengbojiang 	__pc;								\
239*22ce4affSfengbojiang })
240*22ce4affSfengbojiang 
241a9643ea8Slogwang #define	PCPU_GET(member)	__PCPU_GET(pc_ ## member)
242a9643ea8Slogwang #define	PCPU_ADD(member, val)	__PCPU_ADD(pc_ ## member, val)
243a9643ea8Slogwang #define	PCPU_INC(member)	__PCPU_INC(pc_ ## member)
244a9643ea8Slogwang #define	PCPU_PTR(member)	__PCPU_PTR(pc_ ## member)
245a9643ea8Slogwang #define	PCPU_SET(member, val)	__PCPU_SET(pc_ ## member, val)
246a9643ea8Slogwang 
247a9643ea8Slogwang #define	IS_BSP()	(PCPU_GET(cpuid) == 0)
248a9643ea8Slogwang 
249*22ce4affSfengbojiang #ifndef FSTACK
250*22ce4affSfengbojiang #define zpcpu_offset_cpu(cpu)	((uintptr_t)&__pcpu[0] + UMA_PCPU_ALLOC_SIZE * cpu)
251*22ce4affSfengbojiang #define zpcpu_base_to_offset(base) (void *)((uintptr_t)(base) - (uintptr_t)&__pcpu[0])
252*22ce4affSfengbojiang #define zpcpu_offset_to_base(base) (void *)((uintptr_t)(base) + (uintptr_t)&__pcpu[0])
253*22ce4affSfengbojiang #endif
254*22ce4affSfengbojiang 
255*22ce4affSfengbojiang #define zpcpu_sub_protected(base, n) do {				\
256*22ce4affSfengbojiang 	ZPCPU_ASSERT_PROTECTED();					\
257*22ce4affSfengbojiang 	zpcpu_sub(base, n);						\
258*22ce4affSfengbojiang } while (0)
259*22ce4affSfengbojiang 
260*22ce4affSfengbojiang #define zpcpu_set_protected(base, n) do {				\
261*22ce4affSfengbojiang 	__typeof(*base) __n = (n);					\
262*22ce4affSfengbojiang 	ZPCPU_ASSERT_PROTECTED();					\
263*22ce4affSfengbojiang 	switch (sizeof(*base)) {					\
264*22ce4affSfengbojiang 	case 4:								\
265*22ce4affSfengbojiang 		__asm __volatile("movl\t%1,%%gs:(%0)"			\
266*22ce4affSfengbojiang 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
267*22ce4affSfengbojiang 		break;							\
268*22ce4affSfengbojiang 	case 8:								\
269*22ce4affSfengbojiang 		__asm __volatile("movq\t%1,%%gs:(%0)"			\
270*22ce4affSfengbojiang 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
271*22ce4affSfengbojiang 		break;							\
272*22ce4affSfengbojiang 	default:							\
273*22ce4affSfengbojiang 		*zpcpu_get(base) = __n;					\
274*22ce4affSfengbojiang 	}								\
275*22ce4affSfengbojiang } while (0);
276*22ce4affSfengbojiang 
277*22ce4affSfengbojiang #define zpcpu_add(base, n) do {						\
278*22ce4affSfengbojiang 	__typeof(*base) __n = (n);					\
279*22ce4affSfengbojiang 	CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8);		\
280*22ce4affSfengbojiang 	switch (sizeof(*base)) {					\
281*22ce4affSfengbojiang 	case 4:								\
282*22ce4affSfengbojiang 		__asm __volatile("addl\t%1,%%gs:(%0)"			\
283*22ce4affSfengbojiang 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
284*22ce4affSfengbojiang 		break;							\
285*22ce4affSfengbojiang 	case 8:								\
286*22ce4affSfengbojiang 		__asm __volatile("addq\t%1,%%gs:(%0)"			\
287*22ce4affSfengbojiang 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
288*22ce4affSfengbojiang 		break;							\
289*22ce4affSfengbojiang 	}								\
290*22ce4affSfengbojiang } while (0)
291*22ce4affSfengbojiang 
292*22ce4affSfengbojiang #define zpcpu_add_protected(base, n) do {				\
293*22ce4affSfengbojiang 	ZPCPU_ASSERT_PROTECTED();					\
294*22ce4affSfengbojiang 	zpcpu_add(base, n);						\
295*22ce4affSfengbojiang } while (0)
296*22ce4affSfengbojiang 
297*22ce4affSfengbojiang #define zpcpu_sub(base, n) do {						\
298*22ce4affSfengbojiang 	__typeof(*base) __n = (n);					\
299*22ce4affSfengbojiang 	CTASSERT(sizeof(*base) == 4 || sizeof(*base) == 8);		\
300*22ce4affSfengbojiang 	switch (sizeof(*base)) {					\
301*22ce4affSfengbojiang 	case 4:								\
302*22ce4affSfengbojiang 		__asm __volatile("subl\t%1,%%gs:(%0)"			\
303*22ce4affSfengbojiang 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
304*22ce4affSfengbojiang 		break;							\
305*22ce4affSfengbojiang 	case 8:								\
306*22ce4affSfengbojiang 		__asm __volatile("subq\t%1,%%gs:(%0)"			\
307*22ce4affSfengbojiang 		    : : "r" (base), "ri" (__n) : "memory", "cc");	\
308*22ce4affSfengbojiang 		break;							\
309*22ce4affSfengbojiang 	}								\
310*22ce4affSfengbojiang } while (0);
311*22ce4affSfengbojiang 
312*22ce4affSfengbojiang #else /* !__GNUCLIKE_ASM || !__GNUCLIKE___TYPEOF */
313a9643ea8Slogwang 
314a9643ea8Slogwang #error "this file needs to be ported to your compiler"
315a9643ea8Slogwang 
316*22ce4affSfengbojiang #endif /* __GNUCLIKE_ASM && __GNUCLIKE___TYPEOF */
317a9643ea8Slogwang 
318a9643ea8Slogwang #endif /* _KERNEL */
319a9643ea8Slogwang 
320a9643ea8Slogwang #endif /* !_MACHINE_PCPU_H_ */
321