1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/types.h> 6 #include <sys/queue.h> 7 #include <ctype.h> 8 #include <stdio.h> 9 #include <stdlib.h> 10 #include <string.h> 11 #include <stdarg.h> 12 #include <errno.h> 13 #include <stdbool.h> 14 #include <stdint.h> 15 #include <inttypes.h> 16 #include <netinet/in.h> 17 18 #include <rte_byteorder.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_interrupts.h> 22 #include <rte_memory.h> 23 #include <rte_memcpy.h> 24 #include <rte_memzone.h> 25 #include <rte_launch.h> 26 #include <rte_eal.h> 27 #include <rte_per_lcore.h> 28 #include <rte_lcore.h> 29 #include <rte_atomic.h> 30 #include <rte_branch_prediction.h> 31 #include <rte_common.h> 32 #include <rte_mempool.h> 33 #include <rte_malloc.h> 34 #include <rte_mbuf.h> 35 #include <rte_errno.h> 36 #include <rte_spinlock.h> 37 #include <rte_string_fns.h> 38 #include <rte_kvargs.h> 39 #include <rte_class.h> 40 #include <rte_ether.h> 41 42 #include "rte_ethdev.h" 43 #include "rte_ethdev_driver.h" 44 #include "ethdev_profile.h" 45 #include "ethdev_private.h" 46 47 int rte_eth_dev_logtype; 48 49 static const char *MZ_RTE_ETH_DEV_DATA = "rte_eth_dev_data"; 50 struct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS]; 51 52 /* spinlock for eth device callbacks */ 53 static rte_spinlock_t rte_eth_dev_cb_lock = RTE_SPINLOCK_INITIALIZER; 54 55 /* spinlock for add/remove rx callbacks */ 56 static rte_spinlock_t rte_eth_rx_cb_lock = RTE_SPINLOCK_INITIALIZER; 57 58 /* spinlock for add/remove tx callbacks */ 59 static rte_spinlock_t rte_eth_tx_cb_lock = RTE_SPINLOCK_INITIALIZER; 60 61 /* spinlock for shared data allocation */ 62 static rte_spinlock_t rte_eth_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 63 64 /* store statistics names and its offset in stats structure */ 65 struct rte_eth_xstats_name_off { 66 char name[RTE_ETH_XSTATS_NAME_SIZE]; 67 unsigned offset; 68 }; 69 70 /* Shared memory between primary and secondary processes. */ 71 static struct { 72 uint64_t next_owner_id; 73 rte_spinlock_t ownership_lock; 74 struct rte_eth_dev_data data[RTE_MAX_ETHPORTS]; 75 } *rte_eth_dev_shared_data; 76 77 static const struct rte_eth_xstats_name_off rte_stats_strings[] = { 78 {"rx_good_packets", offsetof(struct rte_eth_stats, ipackets)}, 79 {"tx_good_packets", offsetof(struct rte_eth_stats, opackets)}, 80 {"rx_good_bytes", offsetof(struct rte_eth_stats, ibytes)}, 81 {"tx_good_bytes", offsetof(struct rte_eth_stats, obytes)}, 82 {"rx_missed_errors", offsetof(struct rte_eth_stats, imissed)}, 83 {"rx_errors", offsetof(struct rte_eth_stats, ierrors)}, 84 {"tx_errors", offsetof(struct rte_eth_stats, oerrors)}, 85 {"rx_mbuf_allocation_errors", offsetof(struct rte_eth_stats, 86 rx_nombuf)}, 87 }; 88 89 #define RTE_NB_STATS (sizeof(rte_stats_strings) / sizeof(rte_stats_strings[0])) 90 91 static const struct rte_eth_xstats_name_off rte_rxq_stats_strings[] = { 92 {"packets", offsetof(struct rte_eth_stats, q_ipackets)}, 93 {"bytes", offsetof(struct rte_eth_stats, q_ibytes)}, 94 {"errors", offsetof(struct rte_eth_stats, q_errors)}, 95 }; 96 97 #define RTE_NB_RXQ_STATS (sizeof(rte_rxq_stats_strings) / \ 98 sizeof(rte_rxq_stats_strings[0])) 99 100 static const struct rte_eth_xstats_name_off rte_txq_stats_strings[] = { 101 {"packets", offsetof(struct rte_eth_stats, q_opackets)}, 102 {"bytes", offsetof(struct rte_eth_stats, q_obytes)}, 103 }; 104 #define RTE_NB_TXQ_STATS (sizeof(rte_txq_stats_strings) / \ 105 sizeof(rte_txq_stats_strings[0])) 106 107 #define RTE_RX_OFFLOAD_BIT2STR(_name) \ 108 { DEV_RX_OFFLOAD_##_name, #_name } 109 110 static const struct { 111 uint64_t offload; 112 const char *name; 113 } rte_rx_offload_names[] = { 114 RTE_RX_OFFLOAD_BIT2STR(VLAN_STRIP), 115 RTE_RX_OFFLOAD_BIT2STR(IPV4_CKSUM), 116 RTE_RX_OFFLOAD_BIT2STR(UDP_CKSUM), 117 RTE_RX_OFFLOAD_BIT2STR(TCP_CKSUM), 118 RTE_RX_OFFLOAD_BIT2STR(TCP_LRO), 119 RTE_RX_OFFLOAD_BIT2STR(QINQ_STRIP), 120 RTE_RX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM), 121 RTE_RX_OFFLOAD_BIT2STR(MACSEC_STRIP), 122 RTE_RX_OFFLOAD_BIT2STR(HEADER_SPLIT), 123 RTE_RX_OFFLOAD_BIT2STR(VLAN_FILTER), 124 RTE_RX_OFFLOAD_BIT2STR(VLAN_EXTEND), 125 RTE_RX_OFFLOAD_BIT2STR(JUMBO_FRAME), 126 RTE_RX_OFFLOAD_BIT2STR(SCATTER), 127 RTE_RX_OFFLOAD_BIT2STR(TIMESTAMP), 128 RTE_RX_OFFLOAD_BIT2STR(SECURITY), 129 RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC), 130 RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM), 131 RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), 132 RTE_RX_OFFLOAD_BIT2STR(RSS_HASH), 133 }; 134 135 #undef RTE_RX_OFFLOAD_BIT2STR 136 137 #define RTE_TX_OFFLOAD_BIT2STR(_name) \ 138 { DEV_TX_OFFLOAD_##_name, #_name } 139 140 static const struct { 141 uint64_t offload; 142 const char *name; 143 } rte_tx_offload_names[] = { 144 RTE_TX_OFFLOAD_BIT2STR(VLAN_INSERT), 145 RTE_TX_OFFLOAD_BIT2STR(IPV4_CKSUM), 146 RTE_TX_OFFLOAD_BIT2STR(UDP_CKSUM), 147 RTE_TX_OFFLOAD_BIT2STR(TCP_CKSUM), 148 RTE_TX_OFFLOAD_BIT2STR(SCTP_CKSUM), 149 RTE_TX_OFFLOAD_BIT2STR(TCP_TSO), 150 RTE_TX_OFFLOAD_BIT2STR(UDP_TSO), 151 RTE_TX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM), 152 RTE_TX_OFFLOAD_BIT2STR(QINQ_INSERT), 153 RTE_TX_OFFLOAD_BIT2STR(VXLAN_TNL_TSO), 154 RTE_TX_OFFLOAD_BIT2STR(GRE_TNL_TSO), 155 RTE_TX_OFFLOAD_BIT2STR(IPIP_TNL_TSO), 156 RTE_TX_OFFLOAD_BIT2STR(GENEVE_TNL_TSO), 157 RTE_TX_OFFLOAD_BIT2STR(MACSEC_INSERT), 158 RTE_TX_OFFLOAD_BIT2STR(MT_LOCKFREE), 159 RTE_TX_OFFLOAD_BIT2STR(MULTI_SEGS), 160 RTE_TX_OFFLOAD_BIT2STR(MBUF_FAST_FREE), 161 RTE_TX_OFFLOAD_BIT2STR(SECURITY), 162 RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO), 163 RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO), 164 RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), 165 }; 166 167 #undef RTE_TX_OFFLOAD_BIT2STR 168 169 /** 170 * The user application callback description. 171 * 172 * It contains callback address to be registered by user application, 173 * the pointer to the parameters for callback, and the event type. 174 */ 175 struct rte_eth_dev_callback { 176 TAILQ_ENTRY(rte_eth_dev_callback) next; /**< Callbacks list */ 177 rte_eth_dev_cb_fn cb_fn; /**< Callback address */ 178 void *cb_arg; /**< Parameter for callback */ 179 void *ret_param; /**< Return parameter */ 180 enum rte_eth_event_type event; /**< Interrupt event type */ 181 uint32_t active; /**< Callback is executing */ 182 }; 183 184 enum { 185 STAT_QMAP_TX = 0, 186 STAT_QMAP_RX 187 }; 188 189 int 190 rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs_str) 191 { 192 int ret; 193 struct rte_devargs devargs = {.args = NULL}; 194 const char *bus_param_key; 195 char *bus_str = NULL; 196 char *cls_str = NULL; 197 int str_size; 198 199 memset(iter, 0, sizeof(*iter)); 200 201 /* 202 * The devargs string may use various syntaxes: 203 * - 0000:08:00.0,representor=[1-3] 204 * - pci:0000:06:00.0,representor=[0,5] 205 * - class=eth,mac=00:11:22:33:44:55 206 * A new syntax is in development (not yet supported): 207 * - bus=X,paramX=x/class=Y,paramY=y/driver=Z,paramZ=z 208 */ 209 210 /* 211 * Handle pure class filter (i.e. without any bus-level argument), 212 * from future new syntax. 213 * rte_devargs_parse() is not yet supporting the new syntax, 214 * that's why this simple case is temporarily parsed here. 215 */ 216 #define iter_anybus_str "class=eth," 217 if (strncmp(devargs_str, iter_anybus_str, 218 strlen(iter_anybus_str)) == 0) { 219 iter->cls_str = devargs_str + strlen(iter_anybus_str); 220 goto end; 221 } 222 223 /* Split bus, device and parameters. */ 224 ret = rte_devargs_parse(&devargs, devargs_str); 225 if (ret != 0) 226 goto error; 227 228 /* 229 * Assume parameters of old syntax can match only at ethdev level. 230 * Extra parameters will be ignored, thanks to "+" prefix. 231 */ 232 str_size = strlen(devargs.args) + 2; 233 cls_str = malloc(str_size); 234 if (cls_str == NULL) { 235 ret = -ENOMEM; 236 goto error; 237 } 238 ret = snprintf(cls_str, str_size, "+%s", devargs.args); 239 if (ret != str_size - 1) { 240 ret = -EINVAL; 241 goto error; 242 } 243 iter->cls_str = cls_str; 244 free(devargs.args); /* allocated by rte_devargs_parse() */ 245 devargs.args = NULL; 246 247 iter->bus = devargs.bus; 248 if (iter->bus->dev_iterate == NULL) { 249 ret = -ENOTSUP; 250 goto error; 251 } 252 253 /* Convert bus args to new syntax for use with new API dev_iterate. */ 254 if (strcmp(iter->bus->name, "vdev") == 0) { 255 bus_param_key = "name"; 256 } else if (strcmp(iter->bus->name, "pci") == 0) { 257 bus_param_key = "addr"; 258 } else { 259 ret = -ENOTSUP; 260 goto error; 261 } 262 str_size = strlen(bus_param_key) + strlen(devargs.name) + 2; 263 bus_str = malloc(str_size); 264 if (bus_str == NULL) { 265 ret = -ENOMEM; 266 goto error; 267 } 268 ret = snprintf(bus_str, str_size, "%s=%s", 269 bus_param_key, devargs.name); 270 if (ret != str_size - 1) { 271 ret = -EINVAL; 272 goto error; 273 } 274 iter->bus_str = bus_str; 275 276 end: 277 iter->cls = rte_class_find_by_name("eth"); 278 return 0; 279 280 error: 281 if (ret == -ENOTSUP) 282 RTE_LOG(ERR, EAL, "Bus %s does not support iterating.\n", 283 iter->bus->name); 284 free(devargs.args); 285 free(bus_str); 286 free(cls_str); 287 return ret; 288 } 289 290 uint16_t 291 rte_eth_iterator_next(struct rte_dev_iterator *iter) 292 { 293 if (iter->cls == NULL) /* invalid ethdev iterator */ 294 return RTE_MAX_ETHPORTS; 295 296 do { /* loop to try all matching rte_device */ 297 /* If not pure ethdev filter and */ 298 if (iter->bus != NULL && 299 /* not in middle of rte_eth_dev iteration, */ 300 iter->class_device == NULL) { 301 /* get next rte_device to try. */ 302 iter->device = iter->bus->dev_iterate( 303 iter->device, iter->bus_str, iter); 304 if (iter->device == NULL) 305 break; /* no more rte_device candidate */ 306 } 307 /* A device is matching bus part, need to check ethdev part. */ 308 iter->class_device = iter->cls->dev_iterate( 309 iter->class_device, iter->cls_str, iter); 310 if (iter->class_device != NULL) 311 return eth_dev_to_id(iter->class_device); /* match */ 312 } while (iter->bus != NULL); /* need to try next rte_device */ 313 314 /* No more ethdev port to iterate. */ 315 rte_eth_iterator_cleanup(iter); 316 return RTE_MAX_ETHPORTS; 317 } 318 319 void 320 rte_eth_iterator_cleanup(struct rte_dev_iterator *iter) 321 { 322 if (iter->bus_str == NULL) 323 return; /* nothing to free in pure class filter */ 324 free(RTE_CAST_FIELD(iter, bus_str, char *)); /* workaround const */ 325 free(RTE_CAST_FIELD(iter, cls_str, char *)); /* workaround const */ 326 memset(iter, 0, sizeof(*iter)); 327 } 328 329 uint16_t 330 rte_eth_find_next(uint16_t port_id) 331 { 332 while (port_id < RTE_MAX_ETHPORTS && 333 rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED) 334 port_id++; 335 336 if (port_id >= RTE_MAX_ETHPORTS) 337 return RTE_MAX_ETHPORTS; 338 339 return port_id; 340 } 341 342 /* 343 * Macro to iterate over all valid ports for internal usage. 344 * Note: RTE_ETH_FOREACH_DEV is different because filtering owned ports. 345 */ 346 #define RTE_ETH_FOREACH_VALID_DEV(port_id) \ 347 for (port_id = rte_eth_find_next(0); \ 348 port_id < RTE_MAX_ETHPORTS; \ 349 port_id = rte_eth_find_next(port_id + 1)) 350 351 uint16_t 352 rte_eth_find_next_of(uint16_t port_id, const struct rte_device *parent) 353 { 354 port_id = rte_eth_find_next(port_id); 355 while (port_id < RTE_MAX_ETHPORTS && 356 rte_eth_devices[port_id].device != parent) 357 port_id = rte_eth_find_next(port_id + 1); 358 359 return port_id; 360 } 361 362 uint16_t 363 rte_eth_find_next_sibling(uint16_t port_id, uint16_t ref_port_id) 364 { 365 RTE_ETH_VALID_PORTID_OR_ERR_RET(ref_port_id, RTE_MAX_ETHPORTS); 366 return rte_eth_find_next_of(port_id, 367 rte_eth_devices[ref_port_id].device); 368 } 369 370 static void 371 rte_eth_dev_shared_data_prepare(void) 372 { 373 const unsigned flags = 0; 374 const struct rte_memzone *mz; 375 376 rte_spinlock_lock(&rte_eth_shared_data_lock); 377 378 if (rte_eth_dev_shared_data == NULL) { 379 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 380 /* Allocate port data and ownership shared memory. */ 381 mz = rte_memzone_reserve(MZ_RTE_ETH_DEV_DATA, 382 sizeof(*rte_eth_dev_shared_data), 383 rte_socket_id(), flags); 384 } else 385 mz = rte_memzone_lookup(MZ_RTE_ETH_DEV_DATA); 386 if (mz == NULL) 387 rte_panic("Cannot allocate ethdev shared data\n"); 388 389 rte_eth_dev_shared_data = mz->addr; 390 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 391 rte_eth_dev_shared_data->next_owner_id = 392 RTE_ETH_DEV_NO_OWNER + 1; 393 rte_spinlock_init(&rte_eth_dev_shared_data->ownership_lock); 394 memset(rte_eth_dev_shared_data->data, 0, 395 sizeof(rte_eth_dev_shared_data->data)); 396 } 397 } 398 399 rte_spinlock_unlock(&rte_eth_shared_data_lock); 400 } 401 402 static bool 403 is_allocated(const struct rte_eth_dev *ethdev) 404 { 405 return ethdev->data->name[0] != '\0'; 406 } 407 408 static struct rte_eth_dev * 409 _rte_eth_dev_allocated(const char *name) 410 { 411 unsigned i; 412 413 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 414 if (rte_eth_devices[i].data != NULL && 415 strcmp(rte_eth_devices[i].data->name, name) == 0) 416 return &rte_eth_devices[i]; 417 } 418 return NULL; 419 } 420 421 struct rte_eth_dev * 422 rte_eth_dev_allocated(const char *name) 423 { 424 struct rte_eth_dev *ethdev; 425 426 rte_eth_dev_shared_data_prepare(); 427 428 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 429 430 ethdev = _rte_eth_dev_allocated(name); 431 432 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 433 434 return ethdev; 435 } 436 437 static uint16_t 438 rte_eth_dev_find_free_port(void) 439 { 440 unsigned i; 441 442 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 443 /* Using shared name field to find a free port. */ 444 if (rte_eth_dev_shared_data->data[i].name[0] == '\0') { 445 RTE_ASSERT(rte_eth_devices[i].state == 446 RTE_ETH_DEV_UNUSED); 447 return i; 448 } 449 } 450 return RTE_MAX_ETHPORTS; 451 } 452 453 static struct rte_eth_dev * 454 eth_dev_get(uint16_t port_id) 455 { 456 struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id]; 457 458 eth_dev->data = &rte_eth_dev_shared_data->data[port_id]; 459 460 return eth_dev; 461 } 462 463 struct rte_eth_dev * 464 rte_eth_dev_allocate(const char *name) 465 { 466 uint16_t port_id; 467 struct rte_eth_dev *eth_dev = NULL; 468 size_t name_len; 469 470 name_len = strnlen(name, RTE_ETH_NAME_MAX_LEN); 471 if (name_len == 0) { 472 RTE_ETHDEV_LOG(ERR, "Zero length Ethernet device name\n"); 473 return NULL; 474 } 475 476 if (name_len >= RTE_ETH_NAME_MAX_LEN) { 477 RTE_ETHDEV_LOG(ERR, "Ethernet device name is too long\n"); 478 return NULL; 479 } 480 481 rte_eth_dev_shared_data_prepare(); 482 483 /* Synchronize port creation between primary and secondary threads. */ 484 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 485 486 if (_rte_eth_dev_allocated(name) != NULL) { 487 RTE_ETHDEV_LOG(ERR, 488 "Ethernet device with name %s already allocated\n", 489 name); 490 goto unlock; 491 } 492 493 port_id = rte_eth_dev_find_free_port(); 494 if (port_id == RTE_MAX_ETHPORTS) { 495 RTE_ETHDEV_LOG(ERR, 496 "Reached maximum number of Ethernet ports\n"); 497 goto unlock; 498 } 499 500 eth_dev = eth_dev_get(port_id); 501 strlcpy(eth_dev->data->name, name, sizeof(eth_dev->data->name)); 502 eth_dev->data->port_id = port_id; 503 eth_dev->data->mtu = RTE_ETHER_MTU; 504 505 unlock: 506 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 507 508 return eth_dev; 509 } 510 511 /* 512 * Attach to a port already registered by the primary process, which 513 * makes sure that the same device would have the same port id both 514 * in the primary and secondary process. 515 */ 516 struct rte_eth_dev * 517 rte_eth_dev_attach_secondary(const char *name) 518 { 519 uint16_t i; 520 struct rte_eth_dev *eth_dev = NULL; 521 522 rte_eth_dev_shared_data_prepare(); 523 524 /* Synchronize port attachment to primary port creation and release. */ 525 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 526 527 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 528 if (strcmp(rte_eth_dev_shared_data->data[i].name, name) == 0) 529 break; 530 } 531 if (i == RTE_MAX_ETHPORTS) { 532 RTE_ETHDEV_LOG(ERR, 533 "Device %s is not driven by the primary process\n", 534 name); 535 } else { 536 eth_dev = eth_dev_get(i); 537 RTE_ASSERT(eth_dev->data->port_id == i); 538 } 539 540 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 541 return eth_dev; 542 } 543 544 int 545 rte_eth_dev_release_port(struct rte_eth_dev *eth_dev) 546 { 547 if (eth_dev == NULL) 548 return -EINVAL; 549 550 rte_eth_dev_shared_data_prepare(); 551 552 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 553 _rte_eth_dev_callback_process(eth_dev, 554 RTE_ETH_EVENT_DESTROY, NULL); 555 556 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 557 558 eth_dev->state = RTE_ETH_DEV_UNUSED; 559 560 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 561 rte_free(eth_dev->data->rx_queues); 562 rte_free(eth_dev->data->tx_queues); 563 rte_free(eth_dev->data->mac_addrs); 564 rte_free(eth_dev->data->hash_mac_addrs); 565 rte_free(eth_dev->data->dev_private); 566 memset(eth_dev->data, 0, sizeof(struct rte_eth_dev_data)); 567 } 568 569 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 570 571 return 0; 572 } 573 574 int 575 rte_eth_dev_is_valid_port(uint16_t port_id) 576 { 577 if (port_id >= RTE_MAX_ETHPORTS || 578 (rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED)) 579 return 0; 580 else 581 return 1; 582 } 583 584 static int 585 rte_eth_is_valid_owner_id(uint64_t owner_id) 586 { 587 if (owner_id == RTE_ETH_DEV_NO_OWNER || 588 rte_eth_dev_shared_data->next_owner_id <= owner_id) 589 return 0; 590 return 1; 591 } 592 593 uint64_t 594 rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id) 595 { 596 port_id = rte_eth_find_next(port_id); 597 while (port_id < RTE_MAX_ETHPORTS && 598 rte_eth_devices[port_id].data->owner.id != owner_id) 599 port_id = rte_eth_find_next(port_id + 1); 600 601 return port_id; 602 } 603 604 int 605 rte_eth_dev_owner_new(uint64_t *owner_id) 606 { 607 rte_eth_dev_shared_data_prepare(); 608 609 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 610 611 *owner_id = rte_eth_dev_shared_data->next_owner_id++; 612 613 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 614 return 0; 615 } 616 617 static int 618 _rte_eth_dev_owner_set(const uint16_t port_id, const uint64_t old_owner_id, 619 const struct rte_eth_dev_owner *new_owner) 620 { 621 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id]; 622 struct rte_eth_dev_owner *port_owner; 623 624 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) { 625 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n", 626 port_id); 627 return -ENODEV; 628 } 629 630 if (!rte_eth_is_valid_owner_id(new_owner->id) && 631 !rte_eth_is_valid_owner_id(old_owner_id)) { 632 RTE_ETHDEV_LOG(ERR, 633 "Invalid owner old_id=%016"PRIx64" new_id=%016"PRIx64"\n", 634 old_owner_id, new_owner->id); 635 return -EINVAL; 636 } 637 638 port_owner = &rte_eth_devices[port_id].data->owner; 639 if (port_owner->id != old_owner_id) { 640 RTE_ETHDEV_LOG(ERR, 641 "Cannot set owner to port %u already owned by %s_%016"PRIX64"\n", 642 port_id, port_owner->name, port_owner->id); 643 return -EPERM; 644 } 645 646 /* can not truncate (same structure) */ 647 strlcpy(port_owner->name, new_owner->name, RTE_ETH_MAX_OWNER_NAME_LEN); 648 649 port_owner->id = new_owner->id; 650 651 RTE_ETHDEV_LOG(DEBUG, "Port %u owner is %s_%016"PRIx64"\n", 652 port_id, new_owner->name, new_owner->id); 653 654 return 0; 655 } 656 657 int 658 rte_eth_dev_owner_set(const uint16_t port_id, 659 const struct rte_eth_dev_owner *owner) 660 { 661 int ret; 662 663 rte_eth_dev_shared_data_prepare(); 664 665 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 666 667 ret = _rte_eth_dev_owner_set(port_id, RTE_ETH_DEV_NO_OWNER, owner); 668 669 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 670 return ret; 671 } 672 673 int 674 rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id) 675 { 676 const struct rte_eth_dev_owner new_owner = (struct rte_eth_dev_owner) 677 {.id = RTE_ETH_DEV_NO_OWNER, .name = ""}; 678 int ret; 679 680 rte_eth_dev_shared_data_prepare(); 681 682 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 683 684 ret = _rte_eth_dev_owner_set(port_id, owner_id, &new_owner); 685 686 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 687 return ret; 688 } 689 690 int 691 rte_eth_dev_owner_delete(const uint64_t owner_id) 692 { 693 uint16_t port_id; 694 int ret = 0; 695 696 rte_eth_dev_shared_data_prepare(); 697 698 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 699 700 if (rte_eth_is_valid_owner_id(owner_id)) { 701 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) 702 if (rte_eth_devices[port_id].data->owner.id == owner_id) 703 memset(&rte_eth_devices[port_id].data->owner, 0, 704 sizeof(struct rte_eth_dev_owner)); 705 RTE_ETHDEV_LOG(NOTICE, 706 "All port owners owned by %016"PRIx64" identifier have removed\n", 707 owner_id); 708 } else { 709 RTE_ETHDEV_LOG(ERR, 710 "Invalid owner id=%016"PRIx64"\n", 711 owner_id); 712 ret = -EINVAL; 713 } 714 715 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 716 717 return ret; 718 } 719 720 int 721 rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner) 722 { 723 int ret = 0; 724 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id]; 725 726 rte_eth_dev_shared_data_prepare(); 727 728 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 729 730 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) { 731 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n", 732 port_id); 733 ret = -ENODEV; 734 } else { 735 rte_memcpy(owner, ðdev->data->owner, sizeof(*owner)); 736 } 737 738 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 739 return ret; 740 } 741 742 int 743 rte_eth_dev_socket_id(uint16_t port_id) 744 { 745 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1); 746 return rte_eth_devices[port_id].data->numa_node; 747 } 748 749 void * 750 rte_eth_dev_get_sec_ctx(uint16_t port_id) 751 { 752 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL); 753 return rte_eth_devices[port_id].security_ctx; 754 } 755 756 uint16_t 757 rte_eth_dev_count_avail(void) 758 { 759 uint16_t p; 760 uint16_t count; 761 762 count = 0; 763 764 RTE_ETH_FOREACH_DEV(p) 765 count++; 766 767 return count; 768 } 769 770 uint16_t 771 rte_eth_dev_count_total(void) 772 { 773 uint16_t port, count = 0; 774 775 RTE_ETH_FOREACH_VALID_DEV(port) 776 count++; 777 778 return count; 779 } 780 781 int 782 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name) 783 { 784 char *tmp; 785 786 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 787 788 if (name == NULL) { 789 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n"); 790 return -EINVAL; 791 } 792 793 /* shouldn't check 'rte_eth_devices[i].data', 794 * because it might be overwritten by VDEV PMD */ 795 tmp = rte_eth_dev_shared_data->data[port_id].name; 796 strcpy(name, tmp); 797 return 0; 798 } 799 800 int 801 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id) 802 { 803 uint32_t pid; 804 805 if (name == NULL) { 806 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n"); 807 return -EINVAL; 808 } 809 810 RTE_ETH_FOREACH_VALID_DEV(pid) 811 if (!strcmp(name, rte_eth_dev_shared_data->data[pid].name)) { 812 *port_id = pid; 813 return 0; 814 } 815 816 return -ENODEV; 817 } 818 819 static int 820 eth_err(uint16_t port_id, int ret) 821 { 822 if (ret == 0) 823 return 0; 824 if (rte_eth_dev_is_removed(port_id)) 825 return -EIO; 826 return ret; 827 } 828 829 static int 830 rte_eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues) 831 { 832 uint16_t old_nb_queues = dev->data->nb_rx_queues; 833 void **rxq; 834 unsigned i; 835 836 if (dev->data->rx_queues == NULL && nb_queues != 0) { /* first time configuration */ 837 dev->data->rx_queues = rte_zmalloc("ethdev->rx_queues", 838 sizeof(dev->data->rx_queues[0]) * nb_queues, 839 RTE_CACHE_LINE_SIZE); 840 if (dev->data->rx_queues == NULL) { 841 dev->data->nb_rx_queues = 0; 842 return -(ENOMEM); 843 } 844 } else if (dev->data->rx_queues != NULL && nb_queues != 0) { /* re-configure */ 845 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP); 846 847 rxq = dev->data->rx_queues; 848 849 for (i = nb_queues; i < old_nb_queues; i++) 850 (*dev->dev_ops->rx_queue_release)(rxq[i]); 851 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues, 852 RTE_CACHE_LINE_SIZE); 853 if (rxq == NULL) 854 return -(ENOMEM); 855 if (nb_queues > old_nb_queues) { 856 uint16_t new_qs = nb_queues - old_nb_queues; 857 858 memset(rxq + old_nb_queues, 0, 859 sizeof(rxq[0]) * new_qs); 860 } 861 862 dev->data->rx_queues = rxq; 863 864 } else if (dev->data->rx_queues != NULL && nb_queues == 0) { 865 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP); 866 867 rxq = dev->data->rx_queues; 868 869 for (i = nb_queues; i < old_nb_queues; i++) 870 (*dev->dev_ops->rx_queue_release)(rxq[i]); 871 872 rte_free(dev->data->rx_queues); 873 dev->data->rx_queues = NULL; 874 } 875 dev->data->nb_rx_queues = nb_queues; 876 return 0; 877 } 878 879 int 880 rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id) 881 { 882 struct rte_eth_dev *dev; 883 884 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 885 886 dev = &rte_eth_devices[port_id]; 887 if (!dev->data->dev_started) { 888 RTE_ETHDEV_LOG(ERR, 889 "Port %u must be started before start any queue\n", 890 port_id); 891 return -EINVAL; 892 } 893 894 if (rx_queue_id >= dev->data->nb_rx_queues) { 895 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 896 return -EINVAL; 897 } 898 899 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP); 900 901 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) { 902 RTE_ETHDEV_LOG(INFO, 903 "Can't start Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n", 904 rx_queue_id, port_id); 905 return -EINVAL; 906 } 907 908 if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) { 909 RTE_ETHDEV_LOG(INFO, 910 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n", 911 rx_queue_id, port_id); 912 return 0; 913 } 914 915 return eth_err(port_id, dev->dev_ops->rx_queue_start(dev, 916 rx_queue_id)); 917 918 } 919 920 int 921 rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id) 922 { 923 struct rte_eth_dev *dev; 924 925 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 926 927 dev = &rte_eth_devices[port_id]; 928 if (rx_queue_id >= dev->data->nb_rx_queues) { 929 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 930 return -EINVAL; 931 } 932 933 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP); 934 935 if (rte_eth_dev_is_rx_hairpin_queue(dev, rx_queue_id)) { 936 RTE_ETHDEV_LOG(INFO, 937 "Can't stop Rx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n", 938 rx_queue_id, port_id); 939 return -EINVAL; 940 } 941 942 if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) { 943 RTE_ETHDEV_LOG(INFO, 944 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n", 945 rx_queue_id, port_id); 946 return 0; 947 } 948 949 return eth_err(port_id, dev->dev_ops->rx_queue_stop(dev, rx_queue_id)); 950 951 } 952 953 int 954 rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id) 955 { 956 struct rte_eth_dev *dev; 957 958 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 959 960 dev = &rte_eth_devices[port_id]; 961 if (!dev->data->dev_started) { 962 RTE_ETHDEV_LOG(ERR, 963 "Port %u must be started before start any queue\n", 964 port_id); 965 return -EINVAL; 966 } 967 968 if (tx_queue_id >= dev->data->nb_tx_queues) { 969 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 970 return -EINVAL; 971 } 972 973 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP); 974 975 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) { 976 RTE_ETHDEV_LOG(INFO, 977 "Can't start Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n", 978 tx_queue_id, port_id); 979 return -EINVAL; 980 } 981 982 if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) { 983 RTE_ETHDEV_LOG(INFO, 984 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n", 985 tx_queue_id, port_id); 986 return 0; 987 } 988 989 return eth_err(port_id, dev->dev_ops->tx_queue_start(dev, tx_queue_id)); 990 } 991 992 int 993 rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id) 994 { 995 struct rte_eth_dev *dev; 996 997 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 998 999 dev = &rte_eth_devices[port_id]; 1000 if (tx_queue_id >= dev->data->nb_tx_queues) { 1001 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 1002 return -EINVAL; 1003 } 1004 1005 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP); 1006 1007 if (rte_eth_dev_is_tx_hairpin_queue(dev, tx_queue_id)) { 1008 RTE_ETHDEV_LOG(INFO, 1009 "Can't stop Tx hairpin queue %"PRIu16" of device with port_id=%"PRIu16"\n", 1010 tx_queue_id, port_id); 1011 return -EINVAL; 1012 } 1013 1014 if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) { 1015 RTE_ETHDEV_LOG(INFO, 1016 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n", 1017 tx_queue_id, port_id); 1018 return 0; 1019 } 1020 1021 return eth_err(port_id, dev->dev_ops->tx_queue_stop(dev, tx_queue_id)); 1022 1023 } 1024 1025 static int 1026 rte_eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues) 1027 { 1028 uint16_t old_nb_queues = dev->data->nb_tx_queues; 1029 void **txq; 1030 unsigned i; 1031 1032 if (dev->data->tx_queues == NULL && nb_queues != 0) { /* first time configuration */ 1033 dev->data->tx_queues = rte_zmalloc("ethdev->tx_queues", 1034 sizeof(dev->data->tx_queues[0]) * nb_queues, 1035 RTE_CACHE_LINE_SIZE); 1036 if (dev->data->tx_queues == NULL) { 1037 dev->data->nb_tx_queues = 0; 1038 return -(ENOMEM); 1039 } 1040 } else if (dev->data->tx_queues != NULL && nb_queues != 0) { /* re-configure */ 1041 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP); 1042 1043 txq = dev->data->tx_queues; 1044 1045 for (i = nb_queues; i < old_nb_queues; i++) 1046 (*dev->dev_ops->tx_queue_release)(txq[i]); 1047 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues, 1048 RTE_CACHE_LINE_SIZE); 1049 if (txq == NULL) 1050 return -ENOMEM; 1051 if (nb_queues > old_nb_queues) { 1052 uint16_t new_qs = nb_queues - old_nb_queues; 1053 1054 memset(txq + old_nb_queues, 0, 1055 sizeof(txq[0]) * new_qs); 1056 } 1057 1058 dev->data->tx_queues = txq; 1059 1060 } else if (dev->data->tx_queues != NULL && nb_queues == 0) { 1061 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP); 1062 1063 txq = dev->data->tx_queues; 1064 1065 for (i = nb_queues; i < old_nb_queues; i++) 1066 (*dev->dev_ops->tx_queue_release)(txq[i]); 1067 1068 rte_free(dev->data->tx_queues); 1069 dev->data->tx_queues = NULL; 1070 } 1071 dev->data->nb_tx_queues = nb_queues; 1072 return 0; 1073 } 1074 1075 uint32_t 1076 rte_eth_speed_bitflag(uint32_t speed, int duplex) 1077 { 1078 switch (speed) { 1079 case ETH_SPEED_NUM_10M: 1080 return duplex ? ETH_LINK_SPEED_10M : ETH_LINK_SPEED_10M_HD; 1081 case ETH_SPEED_NUM_100M: 1082 return duplex ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_100M_HD; 1083 case ETH_SPEED_NUM_1G: 1084 return ETH_LINK_SPEED_1G; 1085 case ETH_SPEED_NUM_2_5G: 1086 return ETH_LINK_SPEED_2_5G; 1087 case ETH_SPEED_NUM_5G: 1088 return ETH_LINK_SPEED_5G; 1089 case ETH_SPEED_NUM_10G: 1090 return ETH_LINK_SPEED_10G; 1091 case ETH_SPEED_NUM_20G: 1092 return ETH_LINK_SPEED_20G; 1093 case ETH_SPEED_NUM_25G: 1094 return ETH_LINK_SPEED_25G; 1095 case ETH_SPEED_NUM_40G: 1096 return ETH_LINK_SPEED_40G; 1097 case ETH_SPEED_NUM_50G: 1098 return ETH_LINK_SPEED_50G; 1099 case ETH_SPEED_NUM_56G: 1100 return ETH_LINK_SPEED_56G; 1101 case ETH_SPEED_NUM_100G: 1102 return ETH_LINK_SPEED_100G; 1103 default: 1104 return 0; 1105 } 1106 } 1107 1108 const char * 1109 rte_eth_dev_rx_offload_name(uint64_t offload) 1110 { 1111 const char *name = "UNKNOWN"; 1112 unsigned int i; 1113 1114 for (i = 0; i < RTE_DIM(rte_rx_offload_names); ++i) { 1115 if (offload == rte_rx_offload_names[i].offload) { 1116 name = rte_rx_offload_names[i].name; 1117 break; 1118 } 1119 } 1120 1121 return name; 1122 } 1123 1124 const char * 1125 rte_eth_dev_tx_offload_name(uint64_t offload) 1126 { 1127 const char *name = "UNKNOWN"; 1128 unsigned int i; 1129 1130 for (i = 0; i < RTE_DIM(rte_tx_offload_names); ++i) { 1131 if (offload == rte_tx_offload_names[i].offload) { 1132 name = rte_tx_offload_names[i].name; 1133 break; 1134 } 1135 } 1136 1137 return name; 1138 } 1139 1140 static inline int 1141 check_lro_pkt_size(uint16_t port_id, uint32_t config_size, 1142 uint32_t max_rx_pkt_len, uint32_t dev_info_size) 1143 { 1144 int ret = 0; 1145 1146 if (dev_info_size == 0) { 1147 if (config_size != max_rx_pkt_len) { 1148 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size" 1149 " %u != %u is not allowed\n", 1150 port_id, config_size, max_rx_pkt_len); 1151 ret = -EINVAL; 1152 } 1153 } else if (config_size > dev_info_size) { 1154 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u " 1155 "> max allowed value %u\n", port_id, config_size, 1156 dev_info_size); 1157 ret = -EINVAL; 1158 } else if (config_size < RTE_ETHER_MIN_LEN) { 1159 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%d max_lro_pkt_size %u " 1160 "< min allowed value %u\n", port_id, config_size, 1161 (unsigned int)RTE_ETHER_MIN_LEN); 1162 ret = -EINVAL; 1163 } 1164 return ret; 1165 } 1166 1167 /* 1168 * Validate offloads that are requested through rte_eth_dev_configure against 1169 * the offloads successfuly set by the ethernet device. 1170 * 1171 * @param port_id 1172 * The port identifier of the Ethernet device. 1173 * @param req_offloads 1174 * The offloads that have been requested through `rte_eth_dev_configure`. 1175 * @param set_offloads 1176 * The offloads successfuly set by the ethernet device. 1177 * @param offload_type 1178 * The offload type i.e. Rx/Tx string. 1179 * @param offload_name 1180 * The function that prints the offload name. 1181 * @return 1182 * - (0) if validation successful. 1183 * - (-EINVAL) if requested offload has been silently disabled. 1184 * 1185 */ 1186 static int 1187 validate_offloads(uint16_t port_id, uint64_t req_offloads, 1188 uint64_t set_offloads, const char *offload_type, 1189 const char *(*offload_name)(uint64_t)) 1190 { 1191 uint64_t offloads_diff = req_offloads ^ set_offloads; 1192 uint64_t offload; 1193 int ret = 0; 1194 1195 while (offloads_diff != 0) { 1196 /* Check if any offload is requested but not enabled. */ 1197 offload = 1ULL << __builtin_ctzll(offloads_diff); 1198 if (offload & req_offloads) { 1199 RTE_ETHDEV_LOG(ERR, 1200 "Port %u failed to enable %s offload %s\n", 1201 port_id, offload_type, offload_name(offload)); 1202 ret = -EINVAL; 1203 } 1204 1205 /* Chech if offload couldn't be disabled. */ 1206 if (offload & set_offloads) { 1207 RTE_ETHDEV_LOG(DEBUG, 1208 "Port %u %s offload %s is not requested but enabled\n", 1209 port_id, offload_type, offload_name(offload)); 1210 } 1211 1212 offloads_diff &= ~offload; 1213 } 1214 1215 return ret; 1216 } 1217 1218 int 1219 rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, 1220 const struct rte_eth_conf *dev_conf) 1221 { 1222 struct rte_eth_dev *dev; 1223 struct rte_eth_dev_info dev_info; 1224 struct rte_eth_conf orig_conf; 1225 int diag; 1226 int ret; 1227 1228 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1229 1230 dev = &rte_eth_devices[port_id]; 1231 1232 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_configure, -ENOTSUP); 1233 1234 if (dev->data->dev_started) { 1235 RTE_ETHDEV_LOG(ERR, 1236 "Port %u must be stopped to allow configuration\n", 1237 port_id); 1238 return -EBUSY; 1239 } 1240 1241 /* Store original config, as rollback required on failure */ 1242 memcpy(&orig_conf, &dev->data->dev_conf, sizeof(dev->data->dev_conf)); 1243 1244 /* 1245 * Copy the dev_conf parameter into the dev structure. 1246 * rte_eth_dev_info_get() requires dev_conf, copy it before dev_info get 1247 */ 1248 if (dev_conf != &dev->data->dev_conf) 1249 memcpy(&dev->data->dev_conf, dev_conf, 1250 sizeof(dev->data->dev_conf)); 1251 1252 ret = rte_eth_dev_info_get(port_id, &dev_info); 1253 if (ret != 0) 1254 goto rollback; 1255 1256 /* If number of queues specified by application for both Rx and Tx is 1257 * zero, use driver preferred values. This cannot be done individually 1258 * as it is valid for either Tx or Rx (but not both) to be zero. 1259 * If driver does not provide any preferred valued, fall back on 1260 * EAL defaults. 1261 */ 1262 if (nb_rx_q == 0 && nb_tx_q == 0) { 1263 nb_rx_q = dev_info.default_rxportconf.nb_queues; 1264 if (nb_rx_q == 0) 1265 nb_rx_q = RTE_ETH_DEV_FALLBACK_RX_NBQUEUES; 1266 nb_tx_q = dev_info.default_txportconf.nb_queues; 1267 if (nb_tx_q == 0) 1268 nb_tx_q = RTE_ETH_DEV_FALLBACK_TX_NBQUEUES; 1269 } 1270 1271 if (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) { 1272 RTE_ETHDEV_LOG(ERR, 1273 "Number of RX queues requested (%u) is greater than max supported(%d)\n", 1274 nb_rx_q, RTE_MAX_QUEUES_PER_PORT); 1275 ret = -EINVAL; 1276 goto rollback; 1277 } 1278 1279 if (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) { 1280 RTE_ETHDEV_LOG(ERR, 1281 "Number of TX queues requested (%u) is greater than max supported(%d)\n", 1282 nb_tx_q, RTE_MAX_QUEUES_PER_PORT); 1283 ret = -EINVAL; 1284 goto rollback; 1285 } 1286 1287 /* 1288 * Check that the numbers of RX and TX queues are not greater 1289 * than the maximum number of RX and TX queues supported by the 1290 * configured device. 1291 */ 1292 if (nb_rx_q > dev_info.max_rx_queues) { 1293 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_rx_queues=%u > %u\n", 1294 port_id, nb_rx_q, dev_info.max_rx_queues); 1295 ret = -EINVAL; 1296 goto rollback; 1297 } 1298 1299 if (nb_tx_q > dev_info.max_tx_queues) { 1300 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_tx_queues=%u > %u\n", 1301 port_id, nb_tx_q, dev_info.max_tx_queues); 1302 ret = -EINVAL; 1303 goto rollback; 1304 } 1305 1306 /* Check that the device supports requested interrupts */ 1307 if ((dev_conf->intr_conf.lsc == 1) && 1308 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC))) { 1309 RTE_ETHDEV_LOG(ERR, "Driver %s does not support lsc\n", 1310 dev->device->driver->name); 1311 ret = -EINVAL; 1312 goto rollback; 1313 } 1314 if ((dev_conf->intr_conf.rmv == 1) && 1315 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_RMV))) { 1316 RTE_ETHDEV_LOG(ERR, "Driver %s does not support rmv\n", 1317 dev->device->driver->name); 1318 ret = -EINVAL; 1319 goto rollback; 1320 } 1321 1322 /* 1323 * If jumbo frames are enabled, check that the maximum RX packet 1324 * length is supported by the configured device. 1325 */ 1326 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1327 if (dev_conf->rxmode.max_rx_pkt_len > dev_info.max_rx_pktlen) { 1328 RTE_ETHDEV_LOG(ERR, 1329 "Ethdev port_id=%u max_rx_pkt_len %u > max valid value %u\n", 1330 port_id, dev_conf->rxmode.max_rx_pkt_len, 1331 dev_info.max_rx_pktlen); 1332 ret = -EINVAL; 1333 goto rollback; 1334 } else if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN) { 1335 RTE_ETHDEV_LOG(ERR, 1336 "Ethdev port_id=%u max_rx_pkt_len %u < min valid value %u\n", 1337 port_id, dev_conf->rxmode.max_rx_pkt_len, 1338 (unsigned int)RTE_ETHER_MIN_LEN); 1339 ret = -EINVAL; 1340 goto rollback; 1341 } 1342 } else { 1343 if (dev_conf->rxmode.max_rx_pkt_len < RTE_ETHER_MIN_LEN || 1344 dev_conf->rxmode.max_rx_pkt_len > RTE_ETHER_MAX_LEN) 1345 /* Use default value */ 1346 dev->data->dev_conf.rxmode.max_rx_pkt_len = 1347 RTE_ETHER_MAX_LEN; 1348 } 1349 1350 /* 1351 * If LRO is enabled, check that the maximum aggregated packet 1352 * size is supported by the configured device. 1353 */ 1354 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) { 1355 if (dev_conf->rxmode.max_lro_pkt_size == 0) 1356 dev->data->dev_conf.rxmode.max_lro_pkt_size = 1357 dev->data->dev_conf.rxmode.max_rx_pkt_len; 1358 ret = check_lro_pkt_size(port_id, 1359 dev->data->dev_conf.rxmode.max_lro_pkt_size, 1360 dev->data->dev_conf.rxmode.max_rx_pkt_len, 1361 dev_info.max_lro_pkt_size); 1362 if (ret != 0) 1363 goto rollback; 1364 } 1365 1366 /* Any requested offloading must be within its device capabilities */ 1367 if ((dev_conf->rxmode.offloads & dev_info.rx_offload_capa) != 1368 dev_conf->rxmode.offloads) { 1369 RTE_ETHDEV_LOG(ERR, 1370 "Ethdev port_id=%u requested Rx offloads 0x%"PRIx64" doesn't match Rx offloads " 1371 "capabilities 0x%"PRIx64" in %s()\n", 1372 port_id, dev_conf->rxmode.offloads, 1373 dev_info.rx_offload_capa, 1374 __func__); 1375 ret = -EINVAL; 1376 goto rollback; 1377 } 1378 if ((dev_conf->txmode.offloads & dev_info.tx_offload_capa) != 1379 dev_conf->txmode.offloads) { 1380 RTE_ETHDEV_LOG(ERR, 1381 "Ethdev port_id=%u requested Tx offloads 0x%"PRIx64" doesn't match Tx offloads " 1382 "capabilities 0x%"PRIx64" in %s()\n", 1383 port_id, dev_conf->txmode.offloads, 1384 dev_info.tx_offload_capa, 1385 __func__); 1386 ret = -EINVAL; 1387 goto rollback; 1388 } 1389 1390 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf = 1391 rte_eth_rss_hf_refine(dev_conf->rx_adv_conf.rss_conf.rss_hf); 1392 1393 /* Check that device supports requested rss hash functions. */ 1394 if ((dev_info.flow_type_rss_offloads | 1395 dev_conf->rx_adv_conf.rss_conf.rss_hf) != 1396 dev_info.flow_type_rss_offloads) { 1397 RTE_ETHDEV_LOG(ERR, 1398 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n", 1399 port_id, dev_conf->rx_adv_conf.rss_conf.rss_hf, 1400 dev_info.flow_type_rss_offloads); 1401 ret = -EINVAL; 1402 goto rollback; 1403 } 1404 1405 /* Check if Rx RSS distribution is disabled but RSS hash is enabled. */ 1406 if (((dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) == 0) && 1407 (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_RSS_HASH)) { 1408 RTE_ETHDEV_LOG(ERR, 1409 "Ethdev port_id=%u config invalid Rx mq_mode without RSS but %s offload is requested\n", 1410 port_id, 1411 rte_eth_dev_rx_offload_name(DEV_RX_OFFLOAD_RSS_HASH)); 1412 ret = -EINVAL; 1413 goto rollback; 1414 } 1415 1416 /* 1417 * Setup new number of RX/TX queues and reconfigure device. 1418 */ 1419 diag = rte_eth_dev_rx_queue_config(dev, nb_rx_q); 1420 if (diag != 0) { 1421 RTE_ETHDEV_LOG(ERR, 1422 "Port%u rte_eth_dev_rx_queue_config = %d\n", 1423 port_id, diag); 1424 ret = diag; 1425 goto rollback; 1426 } 1427 1428 diag = rte_eth_dev_tx_queue_config(dev, nb_tx_q); 1429 if (diag != 0) { 1430 RTE_ETHDEV_LOG(ERR, 1431 "Port%u rte_eth_dev_tx_queue_config = %d\n", 1432 port_id, diag); 1433 rte_eth_dev_rx_queue_config(dev, 0); 1434 ret = diag; 1435 goto rollback; 1436 } 1437 1438 diag = (*dev->dev_ops->dev_configure)(dev); 1439 if (diag != 0) { 1440 RTE_ETHDEV_LOG(ERR, "Port%u dev_configure = %d\n", 1441 port_id, diag); 1442 ret = eth_err(port_id, diag); 1443 goto reset_queues; 1444 } 1445 1446 /* Initialize Rx profiling if enabled at compilation time. */ 1447 diag = __rte_eth_dev_profile_init(port_id, dev); 1448 if (diag != 0) { 1449 RTE_ETHDEV_LOG(ERR, "Port%u __rte_eth_dev_profile_init = %d\n", 1450 port_id, diag); 1451 ret = eth_err(port_id, diag); 1452 goto reset_queues; 1453 } 1454 1455 /* Validate Rx offloads. */ 1456 diag = validate_offloads(port_id, 1457 dev_conf->rxmode.offloads, 1458 dev->data->dev_conf.rxmode.offloads, "Rx", 1459 rte_eth_dev_rx_offload_name); 1460 if (diag != 0) { 1461 ret = diag; 1462 goto reset_queues; 1463 } 1464 1465 /* Validate Tx offloads. */ 1466 diag = validate_offloads(port_id, 1467 dev_conf->txmode.offloads, 1468 dev->data->dev_conf.txmode.offloads, "Tx", 1469 rte_eth_dev_tx_offload_name); 1470 if (diag != 0) { 1471 ret = diag; 1472 goto reset_queues; 1473 } 1474 1475 return 0; 1476 reset_queues: 1477 rte_eth_dev_rx_queue_config(dev, 0); 1478 rte_eth_dev_tx_queue_config(dev, 0); 1479 rollback: 1480 memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf)); 1481 1482 return ret; 1483 } 1484 1485 void 1486 _rte_eth_dev_reset(struct rte_eth_dev *dev) 1487 { 1488 if (dev->data->dev_started) { 1489 RTE_ETHDEV_LOG(ERR, "Port %u must be stopped to allow reset\n", 1490 dev->data->port_id); 1491 return; 1492 } 1493 1494 rte_eth_dev_rx_queue_config(dev, 0); 1495 rte_eth_dev_tx_queue_config(dev, 0); 1496 1497 memset(&dev->data->dev_conf, 0, sizeof(dev->data->dev_conf)); 1498 } 1499 1500 static void 1501 rte_eth_dev_mac_restore(struct rte_eth_dev *dev, 1502 struct rte_eth_dev_info *dev_info) 1503 { 1504 struct rte_ether_addr *addr; 1505 uint16_t i; 1506 uint32_t pool = 0; 1507 uint64_t pool_mask; 1508 1509 /* replay MAC address configuration including default MAC */ 1510 addr = &dev->data->mac_addrs[0]; 1511 if (*dev->dev_ops->mac_addr_set != NULL) 1512 (*dev->dev_ops->mac_addr_set)(dev, addr); 1513 else if (*dev->dev_ops->mac_addr_add != NULL) 1514 (*dev->dev_ops->mac_addr_add)(dev, addr, 0, pool); 1515 1516 if (*dev->dev_ops->mac_addr_add != NULL) { 1517 for (i = 1; i < dev_info->max_mac_addrs; i++) { 1518 addr = &dev->data->mac_addrs[i]; 1519 1520 /* skip zero address */ 1521 if (rte_is_zero_ether_addr(addr)) 1522 continue; 1523 1524 pool = 0; 1525 pool_mask = dev->data->mac_pool_sel[i]; 1526 1527 do { 1528 if (pool_mask & 1ULL) 1529 (*dev->dev_ops->mac_addr_add)(dev, 1530 addr, i, pool); 1531 pool_mask >>= 1; 1532 pool++; 1533 } while (pool_mask); 1534 } 1535 } 1536 } 1537 1538 static int 1539 rte_eth_dev_config_restore(struct rte_eth_dev *dev, 1540 struct rte_eth_dev_info *dev_info, uint16_t port_id) 1541 { 1542 int ret; 1543 1544 if (!(*dev_info->dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR)) 1545 rte_eth_dev_mac_restore(dev, dev_info); 1546 1547 /* replay promiscuous configuration */ 1548 /* 1549 * use callbacks directly since we don't need port_id check and 1550 * would like to bypass the same value set 1551 */ 1552 if (rte_eth_promiscuous_get(port_id) == 1 && 1553 *dev->dev_ops->promiscuous_enable != NULL) { 1554 ret = eth_err(port_id, 1555 (*dev->dev_ops->promiscuous_enable)(dev)); 1556 if (ret != 0 && ret != -ENOTSUP) { 1557 RTE_ETHDEV_LOG(ERR, 1558 "Failed to enable promiscuous mode for device (port %u): %s\n", 1559 port_id, rte_strerror(-ret)); 1560 return ret; 1561 } 1562 } else if (rte_eth_promiscuous_get(port_id) == 0 && 1563 *dev->dev_ops->promiscuous_disable != NULL) { 1564 ret = eth_err(port_id, 1565 (*dev->dev_ops->promiscuous_disable)(dev)); 1566 if (ret != 0 && ret != -ENOTSUP) { 1567 RTE_ETHDEV_LOG(ERR, 1568 "Failed to disable promiscuous mode for device (port %u): %s\n", 1569 port_id, rte_strerror(-ret)); 1570 return ret; 1571 } 1572 } 1573 1574 /* replay all multicast configuration */ 1575 /* 1576 * use callbacks directly since we don't need port_id check and 1577 * would like to bypass the same value set 1578 */ 1579 if (rte_eth_allmulticast_get(port_id) == 1 && 1580 *dev->dev_ops->allmulticast_enable != NULL) { 1581 ret = eth_err(port_id, 1582 (*dev->dev_ops->allmulticast_enable)(dev)); 1583 if (ret != 0 && ret != -ENOTSUP) { 1584 RTE_ETHDEV_LOG(ERR, 1585 "Failed to enable allmulticast mode for device (port %u): %s\n", 1586 port_id, rte_strerror(-ret)); 1587 return ret; 1588 } 1589 } else if (rte_eth_allmulticast_get(port_id) == 0 && 1590 *dev->dev_ops->allmulticast_disable != NULL) { 1591 ret = eth_err(port_id, 1592 (*dev->dev_ops->allmulticast_disable)(dev)); 1593 if (ret != 0 && ret != -ENOTSUP) { 1594 RTE_ETHDEV_LOG(ERR, 1595 "Failed to disable allmulticast mode for device (port %u): %s\n", 1596 port_id, rte_strerror(-ret)); 1597 return ret; 1598 } 1599 } 1600 1601 return 0; 1602 } 1603 1604 int 1605 rte_eth_dev_start(uint16_t port_id) 1606 { 1607 struct rte_eth_dev *dev; 1608 struct rte_eth_dev_info dev_info; 1609 int diag; 1610 int ret; 1611 1612 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1613 1614 dev = &rte_eth_devices[port_id]; 1615 1616 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP); 1617 1618 if (dev->data->dev_started != 0) { 1619 RTE_ETHDEV_LOG(INFO, 1620 "Device with port_id=%"PRIu16" already started\n", 1621 port_id); 1622 return 0; 1623 } 1624 1625 ret = rte_eth_dev_info_get(port_id, &dev_info); 1626 if (ret != 0) 1627 return ret; 1628 1629 /* Lets restore MAC now if device does not support live change */ 1630 if (*dev_info.dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR) 1631 rte_eth_dev_mac_restore(dev, &dev_info); 1632 1633 diag = (*dev->dev_ops->dev_start)(dev); 1634 if (diag == 0) 1635 dev->data->dev_started = 1; 1636 else 1637 return eth_err(port_id, diag); 1638 1639 ret = rte_eth_dev_config_restore(dev, &dev_info, port_id); 1640 if (ret != 0) { 1641 RTE_ETHDEV_LOG(ERR, 1642 "Error during restoring configuration for device (port %u): %s\n", 1643 port_id, rte_strerror(-ret)); 1644 rte_eth_dev_stop(port_id); 1645 return ret; 1646 } 1647 1648 if (dev->data->dev_conf.intr_conf.lsc == 0) { 1649 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP); 1650 (*dev->dev_ops->link_update)(dev, 0); 1651 } 1652 return 0; 1653 } 1654 1655 void 1656 rte_eth_dev_stop(uint16_t port_id) 1657 { 1658 struct rte_eth_dev *dev; 1659 1660 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1661 dev = &rte_eth_devices[port_id]; 1662 1663 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_stop); 1664 1665 if (dev->data->dev_started == 0) { 1666 RTE_ETHDEV_LOG(INFO, 1667 "Device with port_id=%"PRIu16" already stopped\n", 1668 port_id); 1669 return; 1670 } 1671 1672 dev->data->dev_started = 0; 1673 (*dev->dev_ops->dev_stop)(dev); 1674 } 1675 1676 int 1677 rte_eth_dev_set_link_up(uint16_t port_id) 1678 { 1679 struct rte_eth_dev *dev; 1680 1681 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1682 1683 dev = &rte_eth_devices[port_id]; 1684 1685 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_up, -ENOTSUP); 1686 return eth_err(port_id, (*dev->dev_ops->dev_set_link_up)(dev)); 1687 } 1688 1689 int 1690 rte_eth_dev_set_link_down(uint16_t port_id) 1691 { 1692 struct rte_eth_dev *dev; 1693 1694 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1695 1696 dev = &rte_eth_devices[port_id]; 1697 1698 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_down, -ENOTSUP); 1699 return eth_err(port_id, (*dev->dev_ops->dev_set_link_down)(dev)); 1700 } 1701 1702 void 1703 rte_eth_dev_close(uint16_t port_id) 1704 { 1705 struct rte_eth_dev *dev; 1706 1707 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1708 dev = &rte_eth_devices[port_id]; 1709 1710 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_close); 1711 dev->data->dev_started = 0; 1712 (*dev->dev_ops->dev_close)(dev); 1713 1714 /* check behaviour flag - temporary for PMD migration */ 1715 if ((dev->data->dev_flags & RTE_ETH_DEV_CLOSE_REMOVE) != 0) { 1716 /* new behaviour: send event + reset state + free all data */ 1717 rte_eth_dev_release_port(dev); 1718 return; 1719 } 1720 RTE_ETHDEV_LOG(DEBUG, "Port closing is using an old behaviour.\n" 1721 "The driver %s should migrate to the new behaviour.\n", 1722 dev->device->driver->name); 1723 /* old behaviour: only free queue arrays */ 1724 dev->data->nb_rx_queues = 0; 1725 rte_free(dev->data->rx_queues); 1726 dev->data->rx_queues = NULL; 1727 dev->data->nb_tx_queues = 0; 1728 rte_free(dev->data->tx_queues); 1729 dev->data->tx_queues = NULL; 1730 } 1731 1732 int 1733 rte_eth_dev_reset(uint16_t port_id) 1734 { 1735 struct rte_eth_dev *dev; 1736 int ret; 1737 1738 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1739 dev = &rte_eth_devices[port_id]; 1740 1741 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_reset, -ENOTSUP); 1742 1743 rte_eth_dev_stop(port_id); 1744 ret = dev->dev_ops->dev_reset(dev); 1745 1746 return eth_err(port_id, ret); 1747 } 1748 1749 int 1750 rte_eth_dev_is_removed(uint16_t port_id) 1751 { 1752 struct rte_eth_dev *dev; 1753 int ret; 1754 1755 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0); 1756 1757 dev = &rte_eth_devices[port_id]; 1758 1759 if (dev->state == RTE_ETH_DEV_REMOVED) 1760 return 1; 1761 1762 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->is_removed, 0); 1763 1764 ret = dev->dev_ops->is_removed(dev); 1765 if (ret != 0) 1766 /* Device is physically removed. */ 1767 dev->state = RTE_ETH_DEV_REMOVED; 1768 1769 return ret; 1770 } 1771 1772 int 1773 rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, 1774 uint16_t nb_rx_desc, unsigned int socket_id, 1775 const struct rte_eth_rxconf *rx_conf, 1776 struct rte_mempool *mp) 1777 { 1778 int ret; 1779 uint32_t mbp_buf_size; 1780 struct rte_eth_dev *dev; 1781 struct rte_eth_dev_info dev_info; 1782 struct rte_eth_rxconf local_conf; 1783 void **rxq; 1784 1785 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1786 1787 dev = &rte_eth_devices[port_id]; 1788 if (rx_queue_id >= dev->data->nb_rx_queues) { 1789 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 1790 return -EINVAL; 1791 } 1792 1793 if (mp == NULL) { 1794 RTE_ETHDEV_LOG(ERR, "Invalid null mempool pointer\n"); 1795 return -EINVAL; 1796 } 1797 1798 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_setup, -ENOTSUP); 1799 1800 /* 1801 * Check the size of the mbuf data buffer. 1802 * This value must be provided in the private data of the memory pool. 1803 * First check that the memory pool has a valid private data. 1804 */ 1805 ret = rte_eth_dev_info_get(port_id, &dev_info); 1806 if (ret != 0) 1807 return ret; 1808 1809 if (mp->private_data_size < sizeof(struct rte_pktmbuf_pool_private)) { 1810 RTE_ETHDEV_LOG(ERR, "%s private_data_size %d < %d\n", 1811 mp->name, (int)mp->private_data_size, 1812 (int)sizeof(struct rte_pktmbuf_pool_private)); 1813 return -ENOSPC; 1814 } 1815 mbp_buf_size = rte_pktmbuf_data_room_size(mp); 1816 1817 if ((mbp_buf_size - RTE_PKTMBUF_HEADROOM) < dev_info.min_rx_bufsize) { 1818 RTE_ETHDEV_LOG(ERR, 1819 "%s mbuf_data_room_size %d < %d (RTE_PKTMBUF_HEADROOM=%d + min_rx_bufsize(dev)=%d)\n", 1820 mp->name, (int)mbp_buf_size, 1821 (int)(RTE_PKTMBUF_HEADROOM + dev_info.min_rx_bufsize), 1822 (int)RTE_PKTMBUF_HEADROOM, 1823 (int)dev_info.min_rx_bufsize); 1824 return -EINVAL; 1825 } 1826 1827 /* Use default specified by driver, if nb_rx_desc is zero */ 1828 if (nb_rx_desc == 0) { 1829 nb_rx_desc = dev_info.default_rxportconf.ring_size; 1830 /* If driver default is also zero, fall back on EAL default */ 1831 if (nb_rx_desc == 0) 1832 nb_rx_desc = RTE_ETH_DEV_FALLBACK_RX_RINGSIZE; 1833 } 1834 1835 if (nb_rx_desc > dev_info.rx_desc_lim.nb_max || 1836 nb_rx_desc < dev_info.rx_desc_lim.nb_min || 1837 nb_rx_desc % dev_info.rx_desc_lim.nb_align != 0) { 1838 1839 RTE_ETHDEV_LOG(ERR, 1840 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n", 1841 nb_rx_desc, dev_info.rx_desc_lim.nb_max, 1842 dev_info.rx_desc_lim.nb_min, 1843 dev_info.rx_desc_lim.nb_align); 1844 return -EINVAL; 1845 } 1846 1847 if (dev->data->dev_started && 1848 !(dev_info.dev_capa & 1849 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP)) 1850 return -EBUSY; 1851 1852 if (dev->data->dev_started && 1853 (dev->data->rx_queue_state[rx_queue_id] != 1854 RTE_ETH_QUEUE_STATE_STOPPED)) 1855 return -EBUSY; 1856 1857 rxq = dev->data->rx_queues; 1858 if (rxq[rx_queue_id]) { 1859 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, 1860 -ENOTSUP); 1861 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]); 1862 rxq[rx_queue_id] = NULL; 1863 } 1864 1865 if (rx_conf == NULL) 1866 rx_conf = &dev_info.default_rxconf; 1867 1868 local_conf = *rx_conf; 1869 1870 /* 1871 * If an offloading has already been enabled in 1872 * rte_eth_dev_configure(), it has been enabled on all queues, 1873 * so there is no need to enable it in this queue again. 1874 * The local_conf.offloads input to underlying PMD only carries 1875 * those offloadings which are only enabled on this queue and 1876 * not enabled on all queues. 1877 */ 1878 local_conf.offloads &= ~dev->data->dev_conf.rxmode.offloads; 1879 1880 /* 1881 * New added offloadings for this queue are those not enabled in 1882 * rte_eth_dev_configure() and they must be per-queue type. 1883 * A pure per-port offloading can't be enabled on a queue while 1884 * disabled on another queue. A pure per-port offloading can't 1885 * be enabled for any queue as new added one if it hasn't been 1886 * enabled in rte_eth_dev_configure(). 1887 */ 1888 if ((local_conf.offloads & dev_info.rx_queue_offload_capa) != 1889 local_conf.offloads) { 1890 RTE_ETHDEV_LOG(ERR, 1891 "Ethdev port_id=%d rx_queue_id=%d, new added offloads 0x%"PRIx64" must be " 1892 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n", 1893 port_id, rx_queue_id, local_conf.offloads, 1894 dev_info.rx_queue_offload_capa, 1895 __func__); 1896 return -EINVAL; 1897 } 1898 1899 /* 1900 * If LRO is enabled, check that the maximum aggregated packet 1901 * size is supported by the configured device. 1902 */ 1903 if (local_conf.offloads & DEV_RX_OFFLOAD_TCP_LRO) { 1904 if (dev->data->dev_conf.rxmode.max_lro_pkt_size == 0) 1905 dev->data->dev_conf.rxmode.max_lro_pkt_size = 1906 dev->data->dev_conf.rxmode.max_rx_pkt_len; 1907 int ret = check_lro_pkt_size(port_id, 1908 dev->data->dev_conf.rxmode.max_lro_pkt_size, 1909 dev->data->dev_conf.rxmode.max_rx_pkt_len, 1910 dev_info.max_lro_pkt_size); 1911 if (ret != 0) 1912 return ret; 1913 } 1914 1915 ret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc, 1916 socket_id, &local_conf, mp); 1917 if (!ret) { 1918 if (!dev->data->min_rx_buf_size || 1919 dev->data->min_rx_buf_size > mbp_buf_size) 1920 dev->data->min_rx_buf_size = mbp_buf_size; 1921 } 1922 1923 return eth_err(port_id, ret); 1924 } 1925 1926 int 1927 rte_eth_rx_hairpin_queue_setup(uint16_t port_id, uint16_t rx_queue_id, 1928 uint16_t nb_rx_desc, 1929 const struct rte_eth_hairpin_conf *conf) 1930 { 1931 int ret; 1932 struct rte_eth_dev *dev; 1933 struct rte_eth_hairpin_cap cap; 1934 void **rxq; 1935 int i; 1936 int count; 1937 1938 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1939 1940 dev = &rte_eth_devices[port_id]; 1941 if (rx_queue_id >= dev->data->nb_rx_queues) { 1942 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 1943 return -EINVAL; 1944 } 1945 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap); 1946 if (ret != 0) 1947 return ret; 1948 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_hairpin_queue_setup, 1949 -ENOTSUP); 1950 /* if nb_rx_desc is zero use max number of desc from the driver. */ 1951 if (nb_rx_desc == 0) 1952 nb_rx_desc = cap.max_nb_desc; 1953 if (nb_rx_desc > cap.max_nb_desc) { 1954 RTE_ETHDEV_LOG(ERR, 1955 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu", 1956 nb_rx_desc, cap.max_nb_desc); 1957 return -EINVAL; 1958 } 1959 if (conf->peer_count > cap.max_rx_2_tx) { 1960 RTE_ETHDEV_LOG(ERR, 1961 "Invalid value for number of peers for Rx queue(=%hu), should be: <= %hu", 1962 conf->peer_count, cap.max_rx_2_tx); 1963 return -EINVAL; 1964 } 1965 if (conf->peer_count == 0) { 1966 RTE_ETHDEV_LOG(ERR, 1967 "Invalid value for number of peers for Rx queue(=%hu), should be: > 0", 1968 conf->peer_count); 1969 return -EINVAL; 1970 } 1971 for (i = 0, count = 0; i < dev->data->nb_rx_queues && 1972 cap.max_nb_queues != UINT16_MAX; i++) { 1973 if (i == rx_queue_id || rte_eth_dev_is_rx_hairpin_queue(dev, i)) 1974 count++; 1975 } 1976 if (count > cap.max_nb_queues) { 1977 RTE_ETHDEV_LOG(ERR, "To many Rx hairpin queues max is %d", 1978 cap.max_nb_queues); 1979 return -EINVAL; 1980 } 1981 if (dev->data->dev_started) 1982 return -EBUSY; 1983 rxq = dev->data->rx_queues; 1984 if (rxq[rx_queue_id] != NULL) { 1985 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, 1986 -ENOTSUP); 1987 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]); 1988 rxq[rx_queue_id] = NULL; 1989 } 1990 ret = (*dev->dev_ops->rx_hairpin_queue_setup)(dev, rx_queue_id, 1991 nb_rx_desc, conf); 1992 if (ret == 0) 1993 dev->data->rx_queue_state[rx_queue_id] = 1994 RTE_ETH_QUEUE_STATE_HAIRPIN; 1995 return eth_err(port_id, ret); 1996 } 1997 1998 int 1999 rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id, 2000 uint16_t nb_tx_desc, unsigned int socket_id, 2001 const struct rte_eth_txconf *tx_conf) 2002 { 2003 struct rte_eth_dev *dev; 2004 struct rte_eth_dev_info dev_info; 2005 struct rte_eth_txconf local_conf; 2006 void **txq; 2007 int ret; 2008 2009 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 2010 2011 dev = &rte_eth_devices[port_id]; 2012 if (tx_queue_id >= dev->data->nb_tx_queues) { 2013 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 2014 return -EINVAL; 2015 } 2016 2017 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_setup, -ENOTSUP); 2018 2019 ret = rte_eth_dev_info_get(port_id, &dev_info); 2020 if (ret != 0) 2021 return ret; 2022 2023 /* Use default specified by driver, if nb_tx_desc is zero */ 2024 if (nb_tx_desc == 0) { 2025 nb_tx_desc = dev_info.default_txportconf.ring_size; 2026 /* If driver default is zero, fall back on EAL default */ 2027 if (nb_tx_desc == 0) 2028 nb_tx_desc = RTE_ETH_DEV_FALLBACK_TX_RINGSIZE; 2029 } 2030 if (nb_tx_desc > dev_info.tx_desc_lim.nb_max || 2031 nb_tx_desc < dev_info.tx_desc_lim.nb_min || 2032 nb_tx_desc % dev_info.tx_desc_lim.nb_align != 0) { 2033 RTE_ETHDEV_LOG(ERR, 2034 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n", 2035 nb_tx_desc, dev_info.tx_desc_lim.nb_max, 2036 dev_info.tx_desc_lim.nb_min, 2037 dev_info.tx_desc_lim.nb_align); 2038 return -EINVAL; 2039 } 2040 2041 if (dev->data->dev_started && 2042 !(dev_info.dev_capa & 2043 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP)) 2044 return -EBUSY; 2045 2046 if (dev->data->dev_started && 2047 (dev->data->tx_queue_state[tx_queue_id] != 2048 RTE_ETH_QUEUE_STATE_STOPPED)) 2049 return -EBUSY; 2050 2051 txq = dev->data->tx_queues; 2052 if (txq[tx_queue_id]) { 2053 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, 2054 -ENOTSUP); 2055 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]); 2056 txq[tx_queue_id] = NULL; 2057 } 2058 2059 if (tx_conf == NULL) 2060 tx_conf = &dev_info.default_txconf; 2061 2062 local_conf = *tx_conf; 2063 2064 /* 2065 * If an offloading has already been enabled in 2066 * rte_eth_dev_configure(), it has been enabled on all queues, 2067 * so there is no need to enable it in this queue again. 2068 * The local_conf.offloads input to underlying PMD only carries 2069 * those offloadings which are only enabled on this queue and 2070 * not enabled on all queues. 2071 */ 2072 local_conf.offloads &= ~dev->data->dev_conf.txmode.offloads; 2073 2074 /* 2075 * New added offloadings for this queue are those not enabled in 2076 * rte_eth_dev_configure() and they must be per-queue type. 2077 * A pure per-port offloading can't be enabled on a queue while 2078 * disabled on another queue. A pure per-port offloading can't 2079 * be enabled for any queue as new added one if it hasn't been 2080 * enabled in rte_eth_dev_configure(). 2081 */ 2082 if ((local_conf.offloads & dev_info.tx_queue_offload_capa) != 2083 local_conf.offloads) { 2084 RTE_ETHDEV_LOG(ERR, 2085 "Ethdev port_id=%d tx_queue_id=%d, new added offloads 0x%"PRIx64" must be " 2086 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n", 2087 port_id, tx_queue_id, local_conf.offloads, 2088 dev_info.tx_queue_offload_capa, 2089 __func__); 2090 return -EINVAL; 2091 } 2092 2093 return eth_err(port_id, (*dev->dev_ops->tx_queue_setup)(dev, 2094 tx_queue_id, nb_tx_desc, socket_id, &local_conf)); 2095 } 2096 2097 int 2098 rte_eth_tx_hairpin_queue_setup(uint16_t port_id, uint16_t tx_queue_id, 2099 uint16_t nb_tx_desc, 2100 const struct rte_eth_hairpin_conf *conf) 2101 { 2102 struct rte_eth_dev *dev; 2103 struct rte_eth_hairpin_cap cap; 2104 void **txq; 2105 int i; 2106 int count; 2107 int ret; 2108 2109 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 2110 dev = &rte_eth_devices[port_id]; 2111 if (tx_queue_id >= dev->data->nb_tx_queues) { 2112 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 2113 return -EINVAL; 2114 } 2115 ret = rte_eth_dev_hairpin_capability_get(port_id, &cap); 2116 if (ret != 0) 2117 return ret; 2118 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_hairpin_queue_setup, 2119 -ENOTSUP); 2120 /* if nb_rx_desc is zero use max number of desc from the driver. */ 2121 if (nb_tx_desc == 0) 2122 nb_tx_desc = cap.max_nb_desc; 2123 if (nb_tx_desc > cap.max_nb_desc) { 2124 RTE_ETHDEV_LOG(ERR, 2125 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu", 2126 nb_tx_desc, cap.max_nb_desc); 2127 return -EINVAL; 2128 } 2129 if (conf->peer_count > cap.max_tx_2_rx) { 2130 RTE_ETHDEV_LOG(ERR, 2131 "Invalid value for number of peers for Tx queue(=%hu), should be: <= %hu", 2132 conf->peer_count, cap.max_tx_2_rx); 2133 return -EINVAL; 2134 } 2135 if (conf->peer_count == 0) { 2136 RTE_ETHDEV_LOG(ERR, 2137 "Invalid value for number of peers for Tx queue(=%hu), should be: > 0", 2138 conf->peer_count); 2139 return -EINVAL; 2140 } 2141 for (i = 0, count = 0; i < dev->data->nb_tx_queues && 2142 cap.max_nb_queues != UINT16_MAX; i++) { 2143 if (i == tx_queue_id || rte_eth_dev_is_tx_hairpin_queue(dev, i)) 2144 count++; 2145 } 2146 if (count > cap.max_nb_queues) { 2147 RTE_ETHDEV_LOG(ERR, "To many Tx hairpin queues max is %d", 2148 cap.max_nb_queues); 2149 return -EINVAL; 2150 } 2151 if (dev->data->dev_started) 2152 return -EBUSY; 2153 txq = dev->data->tx_queues; 2154 if (txq[tx_queue_id] != NULL) { 2155 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, 2156 -ENOTSUP); 2157 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]); 2158 txq[tx_queue_id] = NULL; 2159 } 2160 ret = (*dev->dev_ops->tx_hairpin_queue_setup) 2161 (dev, tx_queue_id, nb_tx_desc, conf); 2162 if (ret == 0) 2163 dev->data->tx_queue_state[tx_queue_id] = 2164 RTE_ETH_QUEUE_STATE_HAIRPIN; 2165 return eth_err(port_id, ret); 2166 } 2167 2168 void 2169 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent, 2170 void *userdata __rte_unused) 2171 { 2172 unsigned i; 2173 2174 for (i = 0; i < unsent; i++) 2175 rte_pktmbuf_free(pkts[i]); 2176 } 2177 2178 void 2179 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent, 2180 void *userdata) 2181 { 2182 uint64_t *count = userdata; 2183 unsigned i; 2184 2185 for (i = 0; i < unsent; i++) 2186 rte_pktmbuf_free(pkts[i]); 2187 2188 *count += unsent; 2189 } 2190 2191 int 2192 rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer, 2193 buffer_tx_error_fn cbfn, void *userdata) 2194 { 2195 buffer->error_callback = cbfn; 2196 buffer->error_userdata = userdata; 2197 return 0; 2198 } 2199 2200 int 2201 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size) 2202 { 2203 int ret = 0; 2204 2205 if (buffer == NULL) 2206 return -EINVAL; 2207 2208 buffer->size = size; 2209 if (buffer->error_callback == NULL) { 2210 ret = rte_eth_tx_buffer_set_err_callback( 2211 buffer, rte_eth_tx_buffer_drop_callback, NULL); 2212 } 2213 2214 return ret; 2215 } 2216 2217 int 2218 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt) 2219 { 2220 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 2221 int ret; 2222 2223 /* Validate Input Data. Bail if not valid or not supported. */ 2224 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2225 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_done_cleanup, -ENOTSUP); 2226 2227 /* Call driver to free pending mbufs. */ 2228 ret = (*dev->dev_ops->tx_done_cleanup)(dev->data->tx_queues[queue_id], 2229 free_cnt); 2230 return eth_err(port_id, ret); 2231 } 2232 2233 int 2234 rte_eth_promiscuous_enable(uint16_t port_id) 2235 { 2236 struct rte_eth_dev *dev; 2237 int diag = 0; 2238 2239 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2240 dev = &rte_eth_devices[port_id]; 2241 2242 if (dev->data->promiscuous == 1) 2243 return 0; 2244 2245 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_enable, -ENOTSUP); 2246 2247 diag = (*dev->dev_ops->promiscuous_enable)(dev); 2248 dev->data->promiscuous = (diag == 0) ? 1 : 0; 2249 2250 return eth_err(port_id, diag); 2251 } 2252 2253 int 2254 rte_eth_promiscuous_disable(uint16_t port_id) 2255 { 2256 struct rte_eth_dev *dev; 2257 int diag = 0; 2258 2259 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2260 dev = &rte_eth_devices[port_id]; 2261 2262 if (dev->data->promiscuous == 0) 2263 return 0; 2264 2265 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->promiscuous_disable, -ENOTSUP); 2266 2267 dev->data->promiscuous = 0; 2268 diag = (*dev->dev_ops->promiscuous_disable)(dev); 2269 if (diag != 0) 2270 dev->data->promiscuous = 1; 2271 2272 return eth_err(port_id, diag); 2273 } 2274 2275 int 2276 rte_eth_promiscuous_get(uint16_t port_id) 2277 { 2278 struct rte_eth_dev *dev; 2279 2280 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 2281 2282 dev = &rte_eth_devices[port_id]; 2283 return dev->data->promiscuous; 2284 } 2285 2286 int 2287 rte_eth_allmulticast_enable(uint16_t port_id) 2288 { 2289 struct rte_eth_dev *dev; 2290 int diag; 2291 2292 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2293 dev = &rte_eth_devices[port_id]; 2294 2295 if (dev->data->all_multicast == 1) 2296 return 0; 2297 2298 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_enable, -ENOTSUP); 2299 diag = (*dev->dev_ops->allmulticast_enable)(dev); 2300 dev->data->all_multicast = (diag == 0) ? 1 : 0; 2301 2302 return eth_err(port_id, diag); 2303 } 2304 2305 int 2306 rte_eth_allmulticast_disable(uint16_t port_id) 2307 { 2308 struct rte_eth_dev *dev; 2309 int diag; 2310 2311 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2312 dev = &rte_eth_devices[port_id]; 2313 2314 if (dev->data->all_multicast == 0) 2315 return 0; 2316 2317 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->allmulticast_disable, -ENOTSUP); 2318 dev->data->all_multicast = 0; 2319 diag = (*dev->dev_ops->allmulticast_disable)(dev); 2320 if (diag != 0) 2321 dev->data->all_multicast = 1; 2322 2323 return eth_err(port_id, diag); 2324 } 2325 2326 int 2327 rte_eth_allmulticast_get(uint16_t port_id) 2328 { 2329 struct rte_eth_dev *dev; 2330 2331 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 2332 2333 dev = &rte_eth_devices[port_id]; 2334 return dev->data->all_multicast; 2335 } 2336 2337 int 2338 rte_eth_link_get(uint16_t port_id, struct rte_eth_link *eth_link) 2339 { 2340 struct rte_eth_dev *dev; 2341 2342 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2343 dev = &rte_eth_devices[port_id]; 2344 2345 if (dev->data->dev_conf.intr_conf.lsc && 2346 dev->data->dev_started) 2347 rte_eth_linkstatus_get(dev, eth_link); 2348 else { 2349 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP); 2350 (*dev->dev_ops->link_update)(dev, 1); 2351 *eth_link = dev->data->dev_link; 2352 } 2353 2354 return 0; 2355 } 2356 2357 int 2358 rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *eth_link) 2359 { 2360 struct rte_eth_dev *dev; 2361 2362 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2363 dev = &rte_eth_devices[port_id]; 2364 2365 if (dev->data->dev_conf.intr_conf.lsc && 2366 dev->data->dev_started) 2367 rte_eth_linkstatus_get(dev, eth_link); 2368 else { 2369 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP); 2370 (*dev->dev_ops->link_update)(dev, 0); 2371 *eth_link = dev->data->dev_link; 2372 } 2373 2374 return 0; 2375 } 2376 2377 int 2378 rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats) 2379 { 2380 struct rte_eth_dev *dev; 2381 2382 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 2383 2384 dev = &rte_eth_devices[port_id]; 2385 memset(stats, 0, sizeof(*stats)); 2386 2387 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP); 2388 stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed; 2389 return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats)); 2390 } 2391 2392 int 2393 rte_eth_stats_reset(uint16_t port_id) 2394 { 2395 struct rte_eth_dev *dev; 2396 int ret; 2397 2398 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2399 dev = &rte_eth_devices[port_id]; 2400 2401 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_reset, -ENOTSUP); 2402 ret = (*dev->dev_ops->stats_reset)(dev); 2403 if (ret != 0) 2404 return eth_err(port_id, ret); 2405 2406 dev->data->rx_mbuf_alloc_failed = 0; 2407 2408 return 0; 2409 } 2410 2411 static inline int 2412 get_xstats_basic_count(struct rte_eth_dev *dev) 2413 { 2414 uint16_t nb_rxqs, nb_txqs; 2415 int count; 2416 2417 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2418 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2419 2420 count = RTE_NB_STATS; 2421 count += nb_rxqs * RTE_NB_RXQ_STATS; 2422 count += nb_txqs * RTE_NB_TXQ_STATS; 2423 2424 return count; 2425 } 2426 2427 static int 2428 get_xstats_count(uint16_t port_id) 2429 { 2430 struct rte_eth_dev *dev; 2431 int count; 2432 2433 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 2434 dev = &rte_eth_devices[port_id]; 2435 if (dev->dev_ops->xstats_get_names_by_id != NULL) { 2436 count = (*dev->dev_ops->xstats_get_names_by_id)(dev, NULL, 2437 NULL, 0); 2438 if (count < 0) 2439 return eth_err(port_id, count); 2440 } 2441 if (dev->dev_ops->xstats_get_names != NULL) { 2442 count = (*dev->dev_ops->xstats_get_names)(dev, NULL, 0); 2443 if (count < 0) 2444 return eth_err(port_id, count); 2445 } else 2446 count = 0; 2447 2448 2449 count += get_xstats_basic_count(dev); 2450 2451 return count; 2452 } 2453 2454 int 2455 rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name, 2456 uint64_t *id) 2457 { 2458 int cnt_xstats, idx_xstat; 2459 2460 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2461 2462 if (!id) { 2463 RTE_ETHDEV_LOG(ERR, "Id pointer is NULL\n"); 2464 return -ENOMEM; 2465 } 2466 2467 if (!xstat_name) { 2468 RTE_ETHDEV_LOG(ERR, "xstat_name pointer is NULL\n"); 2469 return -ENOMEM; 2470 } 2471 2472 /* Get count */ 2473 cnt_xstats = rte_eth_xstats_get_names_by_id(port_id, NULL, 0, NULL); 2474 if (cnt_xstats < 0) { 2475 RTE_ETHDEV_LOG(ERR, "Cannot get count of xstats\n"); 2476 return -ENODEV; 2477 } 2478 2479 /* Get id-name lookup table */ 2480 struct rte_eth_xstat_name xstats_names[cnt_xstats]; 2481 2482 if (cnt_xstats != rte_eth_xstats_get_names_by_id( 2483 port_id, xstats_names, cnt_xstats, NULL)) { 2484 RTE_ETHDEV_LOG(ERR, "Cannot get xstats lookup\n"); 2485 return -1; 2486 } 2487 2488 for (idx_xstat = 0; idx_xstat < cnt_xstats; idx_xstat++) { 2489 if (!strcmp(xstats_names[idx_xstat].name, xstat_name)) { 2490 *id = idx_xstat; 2491 return 0; 2492 }; 2493 } 2494 2495 return -EINVAL; 2496 } 2497 2498 /* retrieve basic stats names */ 2499 static int 2500 rte_eth_basic_stats_get_names(struct rte_eth_dev *dev, 2501 struct rte_eth_xstat_name *xstats_names) 2502 { 2503 int cnt_used_entries = 0; 2504 uint32_t idx, id_queue; 2505 uint16_t num_q; 2506 2507 for (idx = 0; idx < RTE_NB_STATS; idx++) { 2508 strlcpy(xstats_names[cnt_used_entries].name, 2509 rte_stats_strings[idx].name, 2510 sizeof(xstats_names[0].name)); 2511 cnt_used_entries++; 2512 } 2513 num_q = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2514 for (id_queue = 0; id_queue < num_q; id_queue++) { 2515 for (idx = 0; idx < RTE_NB_RXQ_STATS; idx++) { 2516 snprintf(xstats_names[cnt_used_entries].name, 2517 sizeof(xstats_names[0].name), 2518 "rx_q%u%s", 2519 id_queue, rte_rxq_stats_strings[idx].name); 2520 cnt_used_entries++; 2521 } 2522 2523 } 2524 num_q = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2525 for (id_queue = 0; id_queue < num_q; id_queue++) { 2526 for (idx = 0; idx < RTE_NB_TXQ_STATS; idx++) { 2527 snprintf(xstats_names[cnt_used_entries].name, 2528 sizeof(xstats_names[0].name), 2529 "tx_q%u%s", 2530 id_queue, rte_txq_stats_strings[idx].name); 2531 cnt_used_entries++; 2532 } 2533 } 2534 return cnt_used_entries; 2535 } 2536 2537 /* retrieve ethdev extended statistics names */ 2538 int 2539 rte_eth_xstats_get_names_by_id(uint16_t port_id, 2540 struct rte_eth_xstat_name *xstats_names, unsigned int size, 2541 uint64_t *ids) 2542 { 2543 struct rte_eth_xstat_name *xstats_names_copy; 2544 unsigned int no_basic_stat_requested = 1; 2545 unsigned int no_ext_stat_requested = 1; 2546 unsigned int expected_entries; 2547 unsigned int basic_count; 2548 struct rte_eth_dev *dev; 2549 unsigned int i; 2550 int ret; 2551 2552 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2553 dev = &rte_eth_devices[port_id]; 2554 2555 basic_count = get_xstats_basic_count(dev); 2556 ret = get_xstats_count(port_id); 2557 if (ret < 0) 2558 return ret; 2559 expected_entries = (unsigned int)ret; 2560 2561 /* Return max number of stats if no ids given */ 2562 if (!ids) { 2563 if (!xstats_names) 2564 return expected_entries; 2565 else if (xstats_names && size < expected_entries) 2566 return expected_entries; 2567 } 2568 2569 if (ids && !xstats_names) 2570 return -EINVAL; 2571 2572 if (ids && dev->dev_ops->xstats_get_names_by_id != NULL && size > 0) { 2573 uint64_t ids_copy[size]; 2574 2575 for (i = 0; i < size; i++) { 2576 if (ids[i] < basic_count) { 2577 no_basic_stat_requested = 0; 2578 break; 2579 } 2580 2581 /* 2582 * Convert ids to xstats ids that PMD knows. 2583 * ids known by user are basic + extended stats. 2584 */ 2585 ids_copy[i] = ids[i] - basic_count; 2586 } 2587 2588 if (no_basic_stat_requested) 2589 return (*dev->dev_ops->xstats_get_names_by_id)(dev, 2590 xstats_names, ids_copy, size); 2591 } 2592 2593 /* Retrieve all stats */ 2594 if (!ids) { 2595 int num_stats = rte_eth_xstats_get_names(port_id, xstats_names, 2596 expected_entries); 2597 if (num_stats < 0 || num_stats > (int)expected_entries) 2598 return num_stats; 2599 else 2600 return expected_entries; 2601 } 2602 2603 xstats_names_copy = calloc(expected_entries, 2604 sizeof(struct rte_eth_xstat_name)); 2605 2606 if (!xstats_names_copy) { 2607 RTE_ETHDEV_LOG(ERR, "Can't allocate memory\n"); 2608 return -ENOMEM; 2609 } 2610 2611 if (ids) { 2612 for (i = 0; i < size; i++) { 2613 if (ids[i] >= basic_count) { 2614 no_ext_stat_requested = 0; 2615 break; 2616 } 2617 } 2618 } 2619 2620 /* Fill xstats_names_copy structure */ 2621 if (ids && no_ext_stat_requested) { 2622 rte_eth_basic_stats_get_names(dev, xstats_names_copy); 2623 } else { 2624 ret = rte_eth_xstats_get_names(port_id, xstats_names_copy, 2625 expected_entries); 2626 if (ret < 0) { 2627 free(xstats_names_copy); 2628 return ret; 2629 } 2630 } 2631 2632 /* Filter stats */ 2633 for (i = 0; i < size; i++) { 2634 if (ids[i] >= expected_entries) { 2635 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n"); 2636 free(xstats_names_copy); 2637 return -1; 2638 } 2639 xstats_names[i] = xstats_names_copy[ids[i]]; 2640 } 2641 2642 free(xstats_names_copy); 2643 return size; 2644 } 2645 2646 int 2647 rte_eth_xstats_get_names(uint16_t port_id, 2648 struct rte_eth_xstat_name *xstats_names, 2649 unsigned int size) 2650 { 2651 struct rte_eth_dev *dev; 2652 int cnt_used_entries; 2653 int cnt_expected_entries; 2654 int cnt_driver_entries; 2655 2656 cnt_expected_entries = get_xstats_count(port_id); 2657 if (xstats_names == NULL || cnt_expected_entries < 0 || 2658 (int)size < cnt_expected_entries) 2659 return cnt_expected_entries; 2660 2661 /* port_id checked in get_xstats_count() */ 2662 dev = &rte_eth_devices[port_id]; 2663 2664 cnt_used_entries = rte_eth_basic_stats_get_names( 2665 dev, xstats_names); 2666 2667 if (dev->dev_ops->xstats_get_names != NULL) { 2668 /* If there are any driver-specific xstats, append them 2669 * to end of list. 2670 */ 2671 cnt_driver_entries = (*dev->dev_ops->xstats_get_names)( 2672 dev, 2673 xstats_names + cnt_used_entries, 2674 size - cnt_used_entries); 2675 if (cnt_driver_entries < 0) 2676 return eth_err(port_id, cnt_driver_entries); 2677 cnt_used_entries += cnt_driver_entries; 2678 } 2679 2680 return cnt_used_entries; 2681 } 2682 2683 2684 static int 2685 rte_eth_basic_stats_get(uint16_t port_id, struct rte_eth_xstat *xstats) 2686 { 2687 struct rte_eth_dev *dev; 2688 struct rte_eth_stats eth_stats; 2689 unsigned int count = 0, i, q; 2690 uint64_t val, *stats_ptr; 2691 uint16_t nb_rxqs, nb_txqs; 2692 int ret; 2693 2694 ret = rte_eth_stats_get(port_id, ð_stats); 2695 if (ret < 0) 2696 return ret; 2697 2698 dev = &rte_eth_devices[port_id]; 2699 2700 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2701 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2702 2703 /* global stats */ 2704 for (i = 0; i < RTE_NB_STATS; i++) { 2705 stats_ptr = RTE_PTR_ADD(ð_stats, 2706 rte_stats_strings[i].offset); 2707 val = *stats_ptr; 2708 xstats[count++].value = val; 2709 } 2710 2711 /* per-rxq stats */ 2712 for (q = 0; q < nb_rxqs; q++) { 2713 for (i = 0; i < RTE_NB_RXQ_STATS; i++) { 2714 stats_ptr = RTE_PTR_ADD(ð_stats, 2715 rte_rxq_stats_strings[i].offset + 2716 q * sizeof(uint64_t)); 2717 val = *stats_ptr; 2718 xstats[count++].value = val; 2719 } 2720 } 2721 2722 /* per-txq stats */ 2723 for (q = 0; q < nb_txqs; q++) { 2724 for (i = 0; i < RTE_NB_TXQ_STATS; i++) { 2725 stats_ptr = RTE_PTR_ADD(ð_stats, 2726 rte_txq_stats_strings[i].offset + 2727 q * sizeof(uint64_t)); 2728 val = *stats_ptr; 2729 xstats[count++].value = val; 2730 } 2731 } 2732 return count; 2733 } 2734 2735 /* retrieve ethdev extended statistics */ 2736 int 2737 rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids, 2738 uint64_t *values, unsigned int size) 2739 { 2740 unsigned int no_basic_stat_requested = 1; 2741 unsigned int no_ext_stat_requested = 1; 2742 unsigned int num_xstats_filled; 2743 unsigned int basic_count; 2744 uint16_t expected_entries; 2745 struct rte_eth_dev *dev; 2746 unsigned int i; 2747 int ret; 2748 2749 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2750 ret = get_xstats_count(port_id); 2751 if (ret < 0) 2752 return ret; 2753 expected_entries = (uint16_t)ret; 2754 struct rte_eth_xstat xstats[expected_entries]; 2755 dev = &rte_eth_devices[port_id]; 2756 basic_count = get_xstats_basic_count(dev); 2757 2758 /* Return max number of stats if no ids given */ 2759 if (!ids) { 2760 if (!values) 2761 return expected_entries; 2762 else if (values && size < expected_entries) 2763 return expected_entries; 2764 } 2765 2766 if (ids && !values) 2767 return -EINVAL; 2768 2769 if (ids && dev->dev_ops->xstats_get_by_id != NULL && size) { 2770 unsigned int basic_count = get_xstats_basic_count(dev); 2771 uint64_t ids_copy[size]; 2772 2773 for (i = 0; i < size; i++) { 2774 if (ids[i] < basic_count) { 2775 no_basic_stat_requested = 0; 2776 break; 2777 } 2778 2779 /* 2780 * Convert ids to xstats ids that PMD knows. 2781 * ids known by user are basic + extended stats. 2782 */ 2783 ids_copy[i] = ids[i] - basic_count; 2784 } 2785 2786 if (no_basic_stat_requested) 2787 return (*dev->dev_ops->xstats_get_by_id)(dev, ids_copy, 2788 values, size); 2789 } 2790 2791 if (ids) { 2792 for (i = 0; i < size; i++) { 2793 if (ids[i] >= basic_count) { 2794 no_ext_stat_requested = 0; 2795 break; 2796 } 2797 } 2798 } 2799 2800 /* Fill the xstats structure */ 2801 if (ids && no_ext_stat_requested) 2802 ret = rte_eth_basic_stats_get(port_id, xstats); 2803 else 2804 ret = rte_eth_xstats_get(port_id, xstats, expected_entries); 2805 2806 if (ret < 0) 2807 return ret; 2808 num_xstats_filled = (unsigned int)ret; 2809 2810 /* Return all stats */ 2811 if (!ids) { 2812 for (i = 0; i < num_xstats_filled; i++) 2813 values[i] = xstats[i].value; 2814 return expected_entries; 2815 } 2816 2817 /* Filter stats */ 2818 for (i = 0; i < size; i++) { 2819 if (ids[i] >= expected_entries) { 2820 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n"); 2821 return -1; 2822 } 2823 values[i] = xstats[ids[i]].value; 2824 } 2825 return size; 2826 } 2827 2828 int 2829 rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats, 2830 unsigned int n) 2831 { 2832 struct rte_eth_dev *dev; 2833 unsigned int count = 0, i; 2834 signed int xcount = 0; 2835 uint16_t nb_rxqs, nb_txqs; 2836 int ret; 2837 2838 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 2839 2840 dev = &rte_eth_devices[port_id]; 2841 2842 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2843 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2844 2845 /* Return generic statistics */ 2846 count = RTE_NB_STATS + (nb_rxqs * RTE_NB_RXQ_STATS) + 2847 (nb_txqs * RTE_NB_TXQ_STATS); 2848 2849 /* implemented by the driver */ 2850 if (dev->dev_ops->xstats_get != NULL) { 2851 /* Retrieve the xstats from the driver at the end of the 2852 * xstats struct. 2853 */ 2854 xcount = (*dev->dev_ops->xstats_get)(dev, 2855 xstats ? xstats + count : NULL, 2856 (n > count) ? n - count : 0); 2857 2858 if (xcount < 0) 2859 return eth_err(port_id, xcount); 2860 } 2861 2862 if (n < count + xcount || xstats == NULL) 2863 return count + xcount; 2864 2865 /* now fill the xstats structure */ 2866 ret = rte_eth_basic_stats_get(port_id, xstats); 2867 if (ret < 0) 2868 return ret; 2869 count = ret; 2870 2871 for (i = 0; i < count; i++) 2872 xstats[i].id = i; 2873 /* add an offset to driver-specific stats */ 2874 for ( ; i < count + xcount; i++) 2875 xstats[i].id += count; 2876 2877 return count + xcount; 2878 } 2879 2880 /* reset ethdev extended statistics */ 2881 int 2882 rte_eth_xstats_reset(uint16_t port_id) 2883 { 2884 struct rte_eth_dev *dev; 2885 2886 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2887 dev = &rte_eth_devices[port_id]; 2888 2889 /* implemented by the driver */ 2890 if (dev->dev_ops->xstats_reset != NULL) 2891 return eth_err(port_id, (*dev->dev_ops->xstats_reset)(dev)); 2892 2893 /* fallback to default */ 2894 return rte_eth_stats_reset(port_id); 2895 } 2896 2897 static int 2898 set_queue_stats_mapping(uint16_t port_id, uint16_t queue_id, uint8_t stat_idx, 2899 uint8_t is_rx) 2900 { 2901 struct rte_eth_dev *dev; 2902 2903 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2904 2905 dev = &rte_eth_devices[port_id]; 2906 2907 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->queue_stats_mapping_set, -ENOTSUP); 2908 2909 if (is_rx && (queue_id >= dev->data->nb_rx_queues)) 2910 return -EINVAL; 2911 2912 if (!is_rx && (queue_id >= dev->data->nb_tx_queues)) 2913 return -EINVAL; 2914 2915 if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 2916 return -EINVAL; 2917 2918 return (*dev->dev_ops->queue_stats_mapping_set) 2919 (dev, queue_id, stat_idx, is_rx); 2920 } 2921 2922 2923 int 2924 rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id, 2925 uint8_t stat_idx) 2926 { 2927 return eth_err(port_id, set_queue_stats_mapping(port_id, tx_queue_id, 2928 stat_idx, STAT_QMAP_TX)); 2929 } 2930 2931 2932 int 2933 rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id, 2934 uint8_t stat_idx) 2935 { 2936 return eth_err(port_id, set_queue_stats_mapping(port_id, rx_queue_id, 2937 stat_idx, STAT_QMAP_RX)); 2938 } 2939 2940 int 2941 rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size) 2942 { 2943 struct rte_eth_dev *dev; 2944 2945 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2946 dev = &rte_eth_devices[port_id]; 2947 2948 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fw_version_get, -ENOTSUP); 2949 return eth_err(port_id, (*dev->dev_ops->fw_version_get)(dev, 2950 fw_version, fw_size)); 2951 } 2952 2953 int 2954 rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info) 2955 { 2956 struct rte_eth_dev *dev; 2957 const struct rte_eth_desc_lim lim = { 2958 .nb_max = UINT16_MAX, 2959 .nb_min = 0, 2960 .nb_align = 1, 2961 .nb_seg_max = UINT16_MAX, 2962 .nb_mtu_seg_max = UINT16_MAX, 2963 }; 2964 int diag; 2965 2966 /* 2967 * Init dev_info before port_id check since caller does not have 2968 * return status and does not know if get is successful or not. 2969 */ 2970 memset(dev_info, 0, sizeof(struct rte_eth_dev_info)); 2971 dev_info->switch_info.domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 2972 2973 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2974 dev = &rte_eth_devices[port_id]; 2975 2976 dev_info->rx_desc_lim = lim; 2977 dev_info->tx_desc_lim = lim; 2978 dev_info->device = dev->device; 2979 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 2980 dev_info->max_mtu = UINT16_MAX; 2981 2982 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP); 2983 diag = (*dev->dev_ops->dev_infos_get)(dev, dev_info); 2984 if (diag != 0) { 2985 /* Cleanup already filled in device information */ 2986 memset(dev_info, 0, sizeof(struct rte_eth_dev_info)); 2987 return eth_err(port_id, diag); 2988 } 2989 2990 /* Maximum number of queues should be <= RTE_MAX_QUEUES_PER_PORT */ 2991 dev_info->max_rx_queues = RTE_MIN(dev_info->max_rx_queues, 2992 RTE_MAX_QUEUES_PER_PORT); 2993 dev_info->max_tx_queues = RTE_MIN(dev_info->max_tx_queues, 2994 RTE_MAX_QUEUES_PER_PORT); 2995 2996 dev_info->driver_name = dev->device->driver->name; 2997 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 2998 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 2999 3000 dev_info->dev_flags = &dev->data->dev_flags; 3001 3002 return 0; 3003 } 3004 3005 int 3006 rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask, 3007 uint32_t *ptypes, int num) 3008 { 3009 int i, j; 3010 struct rte_eth_dev *dev; 3011 const uint32_t *all_ptypes; 3012 3013 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3014 dev = &rte_eth_devices[port_id]; 3015 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_supported_ptypes_get, 0); 3016 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev); 3017 3018 if (!all_ptypes) 3019 return 0; 3020 3021 for (i = 0, j = 0; all_ptypes[i] != RTE_PTYPE_UNKNOWN; ++i) 3022 if (all_ptypes[i] & ptype_mask) { 3023 if (j < num) 3024 ptypes[j] = all_ptypes[i]; 3025 j++; 3026 } 3027 3028 return j; 3029 } 3030 3031 int 3032 rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask, 3033 uint32_t *set_ptypes, unsigned int num) 3034 { 3035 const uint32_t valid_ptype_masks[] = { 3036 RTE_PTYPE_L2_MASK, 3037 RTE_PTYPE_L3_MASK, 3038 RTE_PTYPE_L4_MASK, 3039 RTE_PTYPE_TUNNEL_MASK, 3040 RTE_PTYPE_INNER_L2_MASK, 3041 RTE_PTYPE_INNER_L3_MASK, 3042 RTE_PTYPE_INNER_L4_MASK, 3043 }; 3044 const uint32_t *all_ptypes; 3045 struct rte_eth_dev *dev; 3046 uint32_t unused_mask; 3047 unsigned int i, j; 3048 int ret; 3049 3050 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3051 dev = &rte_eth_devices[port_id]; 3052 3053 if (num > 0 && set_ptypes == NULL) 3054 return -EINVAL; 3055 3056 if (*dev->dev_ops->dev_supported_ptypes_get == NULL || 3057 *dev->dev_ops->dev_ptypes_set == NULL) { 3058 ret = 0; 3059 goto ptype_unknown; 3060 } 3061 3062 if (ptype_mask == 0) { 3063 ret = (*dev->dev_ops->dev_ptypes_set)(dev, 3064 ptype_mask); 3065 goto ptype_unknown; 3066 } 3067 3068 unused_mask = ptype_mask; 3069 for (i = 0; i < RTE_DIM(valid_ptype_masks); i++) { 3070 uint32_t mask = ptype_mask & valid_ptype_masks[i]; 3071 if (mask && mask != valid_ptype_masks[i]) { 3072 ret = -EINVAL; 3073 goto ptype_unknown; 3074 } 3075 unused_mask &= ~valid_ptype_masks[i]; 3076 } 3077 3078 if (unused_mask) { 3079 ret = -EINVAL; 3080 goto ptype_unknown; 3081 } 3082 3083 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev); 3084 if (all_ptypes == NULL) { 3085 ret = 0; 3086 goto ptype_unknown; 3087 } 3088 3089 /* 3090 * Accommodate as many set_ptypes as possible. If the supplied 3091 * set_ptypes array is insufficient fill it partially. 3092 */ 3093 for (i = 0, j = 0; set_ptypes != NULL && 3094 (all_ptypes[i] != RTE_PTYPE_UNKNOWN); ++i) { 3095 if (ptype_mask & all_ptypes[i]) { 3096 if (j < num - 1) { 3097 set_ptypes[j] = all_ptypes[i]; 3098 j++; 3099 continue; 3100 } 3101 break; 3102 } 3103 } 3104 3105 if (set_ptypes != NULL && j < num) 3106 set_ptypes[j] = RTE_PTYPE_UNKNOWN; 3107 3108 return (*dev->dev_ops->dev_ptypes_set)(dev, ptype_mask); 3109 3110 ptype_unknown: 3111 if (num > 0) 3112 set_ptypes[0] = RTE_PTYPE_UNKNOWN; 3113 3114 return ret; 3115 } 3116 3117 int 3118 rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr) 3119 { 3120 struct rte_eth_dev *dev; 3121 3122 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3123 dev = &rte_eth_devices[port_id]; 3124 rte_ether_addr_copy(&dev->data->mac_addrs[0], mac_addr); 3125 3126 return 0; 3127 } 3128 3129 int 3130 rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu) 3131 { 3132 struct rte_eth_dev *dev; 3133 3134 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3135 3136 dev = &rte_eth_devices[port_id]; 3137 *mtu = dev->data->mtu; 3138 return 0; 3139 } 3140 3141 int 3142 rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu) 3143 { 3144 int ret; 3145 struct rte_eth_dev_info dev_info; 3146 struct rte_eth_dev *dev; 3147 3148 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3149 dev = &rte_eth_devices[port_id]; 3150 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mtu_set, -ENOTSUP); 3151 3152 /* 3153 * Check if the device supports dev_infos_get, if it does not 3154 * skip min_mtu/max_mtu validation here as this requires values 3155 * that are populated within the call to rte_eth_dev_info_get() 3156 * which relies on dev->dev_ops->dev_infos_get. 3157 */ 3158 if (*dev->dev_ops->dev_infos_get != NULL) { 3159 ret = rte_eth_dev_info_get(port_id, &dev_info); 3160 if (ret != 0) 3161 return ret; 3162 3163 if (mtu < dev_info.min_mtu || mtu > dev_info.max_mtu) 3164 return -EINVAL; 3165 } 3166 3167 ret = (*dev->dev_ops->mtu_set)(dev, mtu); 3168 if (!ret) 3169 dev->data->mtu = mtu; 3170 3171 return eth_err(port_id, ret); 3172 } 3173 3174 int 3175 rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on) 3176 { 3177 struct rte_eth_dev *dev; 3178 int ret; 3179 3180 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3181 dev = &rte_eth_devices[port_id]; 3182 if (!(dev->data->dev_conf.rxmode.offloads & 3183 DEV_RX_OFFLOAD_VLAN_FILTER)) { 3184 RTE_ETHDEV_LOG(ERR, "Port %u: vlan-filtering disabled\n", 3185 port_id); 3186 return -ENOSYS; 3187 } 3188 3189 if (vlan_id > 4095) { 3190 RTE_ETHDEV_LOG(ERR, "Port_id=%u invalid vlan_id=%u > 4095\n", 3191 port_id, vlan_id); 3192 return -EINVAL; 3193 } 3194 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_filter_set, -ENOTSUP); 3195 3196 ret = (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on); 3197 if (ret == 0) { 3198 struct rte_vlan_filter_conf *vfc; 3199 int vidx; 3200 int vbit; 3201 3202 vfc = &dev->data->vlan_filter_conf; 3203 vidx = vlan_id / 64; 3204 vbit = vlan_id % 64; 3205 3206 if (on) 3207 vfc->ids[vidx] |= UINT64_C(1) << vbit; 3208 else 3209 vfc->ids[vidx] &= ~(UINT64_C(1) << vbit); 3210 } 3211 3212 return eth_err(port_id, ret); 3213 } 3214 3215 int 3216 rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id, 3217 int on) 3218 { 3219 struct rte_eth_dev *dev; 3220 3221 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3222 dev = &rte_eth_devices[port_id]; 3223 if (rx_queue_id >= dev->data->nb_rx_queues) { 3224 RTE_ETHDEV_LOG(ERR, "Invalid rx_queue_id=%u\n", rx_queue_id); 3225 return -EINVAL; 3226 } 3227 3228 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP); 3229 (*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on); 3230 3231 return 0; 3232 } 3233 3234 int 3235 rte_eth_dev_set_vlan_ether_type(uint16_t port_id, 3236 enum rte_vlan_type vlan_type, 3237 uint16_t tpid) 3238 { 3239 struct rte_eth_dev *dev; 3240 3241 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3242 dev = &rte_eth_devices[port_id]; 3243 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_tpid_set, -ENOTSUP); 3244 3245 return eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type, 3246 tpid)); 3247 } 3248 3249 int 3250 rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask) 3251 { 3252 struct rte_eth_dev *dev; 3253 int ret = 0; 3254 int mask = 0; 3255 int cur, org = 0; 3256 uint64_t orig_offloads; 3257 uint64_t dev_offloads; 3258 3259 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3260 dev = &rte_eth_devices[port_id]; 3261 3262 /* save original values in case of failure */ 3263 orig_offloads = dev->data->dev_conf.rxmode.offloads; 3264 dev_offloads = orig_offloads; 3265 3266 /*check which option changed by application*/ 3267 cur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD); 3268 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 3269 if (cur != org) { 3270 if (cur) 3271 dev_offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 3272 else 3273 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 3274 mask |= ETH_VLAN_STRIP_MASK; 3275 } 3276 3277 cur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD); 3278 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER); 3279 if (cur != org) { 3280 if (cur) 3281 dev_offloads |= DEV_RX_OFFLOAD_VLAN_FILTER; 3282 else 3283 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_FILTER; 3284 mask |= ETH_VLAN_FILTER_MASK; 3285 } 3286 3287 cur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD); 3288 org = !!(dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND); 3289 if (cur != org) { 3290 if (cur) 3291 dev_offloads |= DEV_RX_OFFLOAD_VLAN_EXTEND; 3292 else 3293 dev_offloads &= ~DEV_RX_OFFLOAD_VLAN_EXTEND; 3294 mask |= ETH_VLAN_EXTEND_MASK; 3295 } 3296 3297 cur = !!(offload_mask & ETH_QINQ_STRIP_OFFLOAD); 3298 org = !!(dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP); 3299 if (cur != org) { 3300 if (cur) 3301 dev_offloads |= DEV_RX_OFFLOAD_QINQ_STRIP; 3302 else 3303 dev_offloads &= ~DEV_RX_OFFLOAD_QINQ_STRIP; 3304 mask |= ETH_QINQ_STRIP_MASK; 3305 } 3306 3307 /*no change*/ 3308 if (mask == 0) 3309 return ret; 3310 3311 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_offload_set, -ENOTSUP); 3312 dev->data->dev_conf.rxmode.offloads = dev_offloads; 3313 ret = (*dev->dev_ops->vlan_offload_set)(dev, mask); 3314 if (ret) { 3315 /* hit an error restore original values */ 3316 dev->data->dev_conf.rxmode.offloads = orig_offloads; 3317 } 3318 3319 return eth_err(port_id, ret); 3320 } 3321 3322 int 3323 rte_eth_dev_get_vlan_offload(uint16_t port_id) 3324 { 3325 struct rte_eth_dev *dev; 3326 uint64_t *dev_offloads; 3327 int ret = 0; 3328 3329 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3330 dev = &rte_eth_devices[port_id]; 3331 dev_offloads = &dev->data->dev_conf.rxmode.offloads; 3332 3333 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 3334 ret |= ETH_VLAN_STRIP_OFFLOAD; 3335 3336 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 3337 ret |= ETH_VLAN_FILTER_OFFLOAD; 3338 3339 if (*dev_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 3340 ret |= ETH_VLAN_EXTEND_OFFLOAD; 3341 3342 if (*dev_offloads & DEV_RX_OFFLOAD_QINQ_STRIP) 3343 ret |= ETH_QINQ_STRIP_OFFLOAD; 3344 3345 return ret; 3346 } 3347 3348 int 3349 rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on) 3350 { 3351 struct rte_eth_dev *dev; 3352 3353 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3354 dev = &rte_eth_devices[port_id]; 3355 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP); 3356 3357 return eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on)); 3358 } 3359 3360 int 3361 rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf) 3362 { 3363 struct rte_eth_dev *dev; 3364 3365 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3366 dev = &rte_eth_devices[port_id]; 3367 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_get, -ENOTSUP); 3368 memset(fc_conf, 0, sizeof(*fc_conf)); 3369 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf)); 3370 } 3371 3372 int 3373 rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf) 3374 { 3375 struct rte_eth_dev *dev; 3376 3377 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3378 if ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) { 3379 RTE_ETHDEV_LOG(ERR, "Invalid send_xon, only 0/1 allowed\n"); 3380 return -EINVAL; 3381 } 3382 3383 dev = &rte_eth_devices[port_id]; 3384 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_set, -ENOTSUP); 3385 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf)); 3386 } 3387 3388 int 3389 rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id, 3390 struct rte_eth_pfc_conf *pfc_conf) 3391 { 3392 struct rte_eth_dev *dev; 3393 3394 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3395 if (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) { 3396 RTE_ETHDEV_LOG(ERR, "Invalid priority, only 0-7 allowed\n"); 3397 return -EINVAL; 3398 } 3399 3400 dev = &rte_eth_devices[port_id]; 3401 /* High water, low water validation are device specific */ 3402 if (*dev->dev_ops->priority_flow_ctrl_set) 3403 return eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set) 3404 (dev, pfc_conf)); 3405 return -ENOTSUP; 3406 } 3407 3408 static int 3409 rte_eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf, 3410 uint16_t reta_size) 3411 { 3412 uint16_t i, num; 3413 3414 if (!reta_conf) 3415 return -EINVAL; 3416 3417 num = (reta_size + RTE_RETA_GROUP_SIZE - 1) / RTE_RETA_GROUP_SIZE; 3418 for (i = 0; i < num; i++) { 3419 if (reta_conf[i].mask) 3420 return 0; 3421 } 3422 3423 return -EINVAL; 3424 } 3425 3426 static int 3427 rte_eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf, 3428 uint16_t reta_size, 3429 uint16_t max_rxq) 3430 { 3431 uint16_t i, idx, shift; 3432 3433 if (!reta_conf) 3434 return -EINVAL; 3435 3436 if (max_rxq == 0) { 3437 RTE_ETHDEV_LOG(ERR, "No receive queue is available\n"); 3438 return -EINVAL; 3439 } 3440 3441 for (i = 0; i < reta_size; i++) { 3442 idx = i / RTE_RETA_GROUP_SIZE; 3443 shift = i % RTE_RETA_GROUP_SIZE; 3444 if ((reta_conf[idx].mask & (1ULL << shift)) && 3445 (reta_conf[idx].reta[shift] >= max_rxq)) { 3446 RTE_ETHDEV_LOG(ERR, 3447 "reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u\n", 3448 idx, shift, 3449 reta_conf[idx].reta[shift], max_rxq); 3450 return -EINVAL; 3451 } 3452 } 3453 3454 return 0; 3455 } 3456 3457 int 3458 rte_eth_dev_rss_reta_update(uint16_t port_id, 3459 struct rte_eth_rss_reta_entry64 *reta_conf, 3460 uint16_t reta_size) 3461 { 3462 struct rte_eth_dev *dev; 3463 int ret; 3464 3465 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3466 /* Check mask bits */ 3467 ret = rte_eth_check_reta_mask(reta_conf, reta_size); 3468 if (ret < 0) 3469 return ret; 3470 3471 dev = &rte_eth_devices[port_id]; 3472 3473 /* Check entry value */ 3474 ret = rte_eth_check_reta_entry(reta_conf, reta_size, 3475 dev->data->nb_rx_queues); 3476 if (ret < 0) 3477 return ret; 3478 3479 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP); 3480 return eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf, 3481 reta_size)); 3482 } 3483 3484 int 3485 rte_eth_dev_rss_reta_query(uint16_t port_id, 3486 struct rte_eth_rss_reta_entry64 *reta_conf, 3487 uint16_t reta_size) 3488 { 3489 struct rte_eth_dev *dev; 3490 int ret; 3491 3492 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3493 3494 /* Check mask bits */ 3495 ret = rte_eth_check_reta_mask(reta_conf, reta_size); 3496 if (ret < 0) 3497 return ret; 3498 3499 dev = &rte_eth_devices[port_id]; 3500 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP); 3501 return eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf, 3502 reta_size)); 3503 } 3504 3505 int 3506 rte_eth_dev_rss_hash_update(uint16_t port_id, 3507 struct rte_eth_rss_conf *rss_conf) 3508 { 3509 struct rte_eth_dev *dev; 3510 struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, }; 3511 int ret; 3512 3513 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3514 3515 ret = rte_eth_dev_info_get(port_id, &dev_info); 3516 if (ret != 0) 3517 return ret; 3518 3519 rss_conf->rss_hf = rte_eth_rss_hf_refine(rss_conf->rss_hf); 3520 3521 dev = &rte_eth_devices[port_id]; 3522 if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) != 3523 dev_info.flow_type_rss_offloads) { 3524 RTE_ETHDEV_LOG(ERR, 3525 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n", 3526 port_id, rss_conf->rss_hf, 3527 dev_info.flow_type_rss_offloads); 3528 return -EINVAL; 3529 } 3530 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_update, -ENOTSUP); 3531 return eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev, 3532 rss_conf)); 3533 } 3534 3535 int 3536 rte_eth_dev_rss_hash_conf_get(uint16_t port_id, 3537 struct rte_eth_rss_conf *rss_conf) 3538 { 3539 struct rte_eth_dev *dev; 3540 3541 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3542 dev = &rte_eth_devices[port_id]; 3543 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_conf_get, -ENOTSUP); 3544 return eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev, 3545 rss_conf)); 3546 } 3547 3548 int 3549 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id, 3550 struct rte_eth_udp_tunnel *udp_tunnel) 3551 { 3552 struct rte_eth_dev *dev; 3553 3554 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3555 if (udp_tunnel == NULL) { 3556 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n"); 3557 return -EINVAL; 3558 } 3559 3560 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) { 3561 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 3562 return -EINVAL; 3563 } 3564 3565 dev = &rte_eth_devices[port_id]; 3566 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_add, -ENOTSUP); 3567 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev, 3568 udp_tunnel)); 3569 } 3570 3571 int 3572 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id, 3573 struct rte_eth_udp_tunnel *udp_tunnel) 3574 { 3575 struct rte_eth_dev *dev; 3576 3577 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3578 dev = &rte_eth_devices[port_id]; 3579 3580 if (udp_tunnel == NULL) { 3581 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n"); 3582 return -EINVAL; 3583 } 3584 3585 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) { 3586 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 3587 return -EINVAL; 3588 } 3589 3590 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_del, -ENOTSUP); 3591 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev, 3592 udp_tunnel)); 3593 } 3594 3595 int 3596 rte_eth_led_on(uint16_t port_id) 3597 { 3598 struct rte_eth_dev *dev; 3599 3600 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3601 dev = &rte_eth_devices[port_id]; 3602 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_on, -ENOTSUP); 3603 return eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev)); 3604 } 3605 3606 int 3607 rte_eth_led_off(uint16_t port_id) 3608 { 3609 struct rte_eth_dev *dev; 3610 3611 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3612 dev = &rte_eth_devices[port_id]; 3613 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_off, -ENOTSUP); 3614 return eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev)); 3615 } 3616 3617 /* 3618 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find 3619 * an empty spot. 3620 */ 3621 static int 3622 get_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr) 3623 { 3624 struct rte_eth_dev_info dev_info; 3625 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3626 unsigned i; 3627 int ret; 3628 3629 ret = rte_eth_dev_info_get(port_id, &dev_info); 3630 if (ret != 0) 3631 return -1; 3632 3633 for (i = 0; i < dev_info.max_mac_addrs; i++) 3634 if (memcmp(addr, &dev->data->mac_addrs[i], 3635 RTE_ETHER_ADDR_LEN) == 0) 3636 return i; 3637 3638 return -1; 3639 } 3640 3641 static const struct rte_ether_addr null_mac_addr; 3642 3643 int 3644 rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr, 3645 uint32_t pool) 3646 { 3647 struct rte_eth_dev *dev; 3648 int index; 3649 uint64_t pool_mask; 3650 int ret; 3651 3652 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3653 dev = &rte_eth_devices[port_id]; 3654 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_add, -ENOTSUP); 3655 3656 if (rte_is_zero_ether_addr(addr)) { 3657 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n", 3658 port_id); 3659 return -EINVAL; 3660 } 3661 if (pool >= ETH_64_POOLS) { 3662 RTE_ETHDEV_LOG(ERR, "Pool id must be 0-%d\n", ETH_64_POOLS - 1); 3663 return -EINVAL; 3664 } 3665 3666 index = get_mac_addr_index(port_id, addr); 3667 if (index < 0) { 3668 index = get_mac_addr_index(port_id, &null_mac_addr); 3669 if (index < 0) { 3670 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n", 3671 port_id); 3672 return -ENOSPC; 3673 } 3674 } else { 3675 pool_mask = dev->data->mac_pool_sel[index]; 3676 3677 /* Check if both MAC address and pool is already there, and do nothing */ 3678 if (pool_mask & (1ULL << pool)) 3679 return 0; 3680 } 3681 3682 /* Update NIC */ 3683 ret = (*dev->dev_ops->mac_addr_add)(dev, addr, index, pool); 3684 3685 if (ret == 0) { 3686 /* Update address in NIC data structure */ 3687 rte_ether_addr_copy(addr, &dev->data->mac_addrs[index]); 3688 3689 /* Update pool bitmap in NIC data structure */ 3690 dev->data->mac_pool_sel[index] |= (1ULL << pool); 3691 } 3692 3693 return eth_err(port_id, ret); 3694 } 3695 3696 int 3697 rte_eth_dev_mac_addr_remove(uint16_t port_id, struct rte_ether_addr *addr) 3698 { 3699 struct rte_eth_dev *dev; 3700 int index; 3701 3702 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3703 dev = &rte_eth_devices[port_id]; 3704 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_remove, -ENOTSUP); 3705 3706 index = get_mac_addr_index(port_id, addr); 3707 if (index == 0) { 3708 RTE_ETHDEV_LOG(ERR, 3709 "Port %u: Cannot remove default MAC address\n", 3710 port_id); 3711 return -EADDRINUSE; 3712 } else if (index < 0) 3713 return 0; /* Do nothing if address wasn't found */ 3714 3715 /* Update NIC */ 3716 (*dev->dev_ops->mac_addr_remove)(dev, index); 3717 3718 /* Update address in NIC data structure */ 3719 rte_ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]); 3720 3721 /* reset pool bitmap */ 3722 dev->data->mac_pool_sel[index] = 0; 3723 3724 return 0; 3725 } 3726 3727 int 3728 rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct rte_ether_addr *addr) 3729 { 3730 struct rte_eth_dev *dev; 3731 int ret; 3732 3733 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3734 3735 if (!rte_is_valid_assigned_ether_addr(addr)) 3736 return -EINVAL; 3737 3738 dev = &rte_eth_devices[port_id]; 3739 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_set, -ENOTSUP); 3740 3741 ret = (*dev->dev_ops->mac_addr_set)(dev, addr); 3742 if (ret < 0) 3743 return ret; 3744 3745 /* Update default address in NIC data structure */ 3746 rte_ether_addr_copy(addr, &dev->data->mac_addrs[0]); 3747 3748 return 0; 3749 } 3750 3751 3752 /* 3753 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find 3754 * an empty spot. 3755 */ 3756 static int 3757 get_hash_mac_addr_index(uint16_t port_id, const struct rte_ether_addr *addr) 3758 { 3759 struct rte_eth_dev_info dev_info; 3760 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3761 unsigned i; 3762 int ret; 3763 3764 ret = rte_eth_dev_info_get(port_id, &dev_info); 3765 if (ret != 0) 3766 return -1; 3767 3768 if (!dev->data->hash_mac_addrs) 3769 return -1; 3770 3771 for (i = 0; i < dev_info.max_hash_mac_addrs; i++) 3772 if (memcmp(addr, &dev->data->hash_mac_addrs[i], 3773 RTE_ETHER_ADDR_LEN) == 0) 3774 return i; 3775 3776 return -1; 3777 } 3778 3779 int 3780 rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr, 3781 uint8_t on) 3782 { 3783 int index; 3784 int ret; 3785 struct rte_eth_dev *dev; 3786 3787 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3788 3789 dev = &rte_eth_devices[port_id]; 3790 if (rte_is_zero_ether_addr(addr)) { 3791 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n", 3792 port_id); 3793 return -EINVAL; 3794 } 3795 3796 index = get_hash_mac_addr_index(port_id, addr); 3797 /* Check if it's already there, and do nothing */ 3798 if ((index >= 0) && on) 3799 return 0; 3800 3801 if (index < 0) { 3802 if (!on) { 3803 RTE_ETHDEV_LOG(ERR, 3804 "Port %u: the MAC address was not set in UTA\n", 3805 port_id); 3806 return -EINVAL; 3807 } 3808 3809 index = get_hash_mac_addr_index(port_id, &null_mac_addr); 3810 if (index < 0) { 3811 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n", 3812 port_id); 3813 return -ENOSPC; 3814 } 3815 } 3816 3817 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_hash_table_set, -ENOTSUP); 3818 ret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on); 3819 if (ret == 0) { 3820 /* Update address in NIC data structure */ 3821 if (on) 3822 rte_ether_addr_copy(addr, 3823 &dev->data->hash_mac_addrs[index]); 3824 else 3825 rte_ether_addr_copy(&null_mac_addr, 3826 &dev->data->hash_mac_addrs[index]); 3827 } 3828 3829 return eth_err(port_id, ret); 3830 } 3831 3832 int 3833 rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on) 3834 { 3835 struct rte_eth_dev *dev; 3836 3837 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3838 3839 dev = &rte_eth_devices[port_id]; 3840 3841 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_all_hash_table_set, -ENOTSUP); 3842 return eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev, 3843 on)); 3844 } 3845 3846 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx, 3847 uint16_t tx_rate) 3848 { 3849 struct rte_eth_dev *dev; 3850 struct rte_eth_dev_info dev_info; 3851 struct rte_eth_link link; 3852 int ret; 3853 3854 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3855 3856 ret = rte_eth_dev_info_get(port_id, &dev_info); 3857 if (ret != 0) 3858 return ret; 3859 3860 dev = &rte_eth_devices[port_id]; 3861 link = dev->data->dev_link; 3862 3863 if (queue_idx > dev_info.max_tx_queues) { 3864 RTE_ETHDEV_LOG(ERR, 3865 "Set queue rate limit:port %u: invalid queue id=%u\n", 3866 port_id, queue_idx); 3867 return -EINVAL; 3868 } 3869 3870 if (tx_rate > link.link_speed) { 3871 RTE_ETHDEV_LOG(ERR, 3872 "Set queue rate limit:invalid tx_rate=%u, bigger than link speed= %d\n", 3873 tx_rate, link.link_speed); 3874 return -EINVAL; 3875 } 3876 3877 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_queue_rate_limit, -ENOTSUP); 3878 return eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev, 3879 queue_idx, tx_rate)); 3880 } 3881 3882 int 3883 rte_eth_mirror_rule_set(uint16_t port_id, 3884 struct rte_eth_mirror_conf *mirror_conf, 3885 uint8_t rule_id, uint8_t on) 3886 { 3887 struct rte_eth_dev *dev; 3888 3889 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3890 if (mirror_conf->rule_type == 0) { 3891 RTE_ETHDEV_LOG(ERR, "Mirror rule type can not be 0\n"); 3892 return -EINVAL; 3893 } 3894 3895 if (mirror_conf->dst_pool >= ETH_64_POOLS) { 3896 RTE_ETHDEV_LOG(ERR, "Invalid dst pool, pool id must be 0-%d\n", 3897 ETH_64_POOLS - 1); 3898 return -EINVAL; 3899 } 3900 3901 if ((mirror_conf->rule_type & (ETH_MIRROR_VIRTUAL_POOL_UP | 3902 ETH_MIRROR_VIRTUAL_POOL_DOWN)) && 3903 (mirror_conf->pool_mask == 0)) { 3904 RTE_ETHDEV_LOG(ERR, 3905 "Invalid mirror pool, pool mask can not be 0\n"); 3906 return -EINVAL; 3907 } 3908 3909 if ((mirror_conf->rule_type & ETH_MIRROR_VLAN) && 3910 mirror_conf->vlan.vlan_mask == 0) { 3911 RTE_ETHDEV_LOG(ERR, 3912 "Invalid vlan mask, vlan mask can not be 0\n"); 3913 return -EINVAL; 3914 } 3915 3916 dev = &rte_eth_devices[port_id]; 3917 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_set, -ENOTSUP); 3918 3919 return eth_err(port_id, (*dev->dev_ops->mirror_rule_set)(dev, 3920 mirror_conf, rule_id, on)); 3921 } 3922 3923 int 3924 rte_eth_mirror_rule_reset(uint16_t port_id, uint8_t rule_id) 3925 { 3926 struct rte_eth_dev *dev; 3927 3928 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3929 3930 dev = &rte_eth_devices[port_id]; 3931 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_reset, -ENOTSUP); 3932 3933 return eth_err(port_id, (*dev->dev_ops->mirror_rule_reset)(dev, 3934 rule_id)); 3935 } 3936 3937 RTE_INIT(eth_dev_init_cb_lists) 3938 { 3939 int i; 3940 3941 for (i = 0; i < RTE_MAX_ETHPORTS; i++) 3942 TAILQ_INIT(&rte_eth_devices[i].link_intr_cbs); 3943 } 3944 3945 int 3946 rte_eth_dev_callback_register(uint16_t port_id, 3947 enum rte_eth_event_type event, 3948 rte_eth_dev_cb_fn cb_fn, void *cb_arg) 3949 { 3950 struct rte_eth_dev *dev; 3951 struct rte_eth_dev_callback *user_cb; 3952 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */ 3953 uint16_t last_port; 3954 3955 if (!cb_fn) 3956 return -EINVAL; 3957 3958 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) { 3959 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id); 3960 return -EINVAL; 3961 } 3962 3963 if (port_id == RTE_ETH_ALL) { 3964 next_port = 0; 3965 last_port = RTE_MAX_ETHPORTS - 1; 3966 } else { 3967 next_port = last_port = port_id; 3968 } 3969 3970 rte_spinlock_lock(&rte_eth_dev_cb_lock); 3971 3972 do { 3973 dev = &rte_eth_devices[next_port]; 3974 3975 TAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) { 3976 if (user_cb->cb_fn == cb_fn && 3977 user_cb->cb_arg == cb_arg && 3978 user_cb->event == event) { 3979 break; 3980 } 3981 } 3982 3983 /* create a new callback. */ 3984 if (user_cb == NULL) { 3985 user_cb = rte_zmalloc("INTR_USER_CALLBACK", 3986 sizeof(struct rte_eth_dev_callback), 0); 3987 if (user_cb != NULL) { 3988 user_cb->cb_fn = cb_fn; 3989 user_cb->cb_arg = cb_arg; 3990 user_cb->event = event; 3991 TAILQ_INSERT_TAIL(&(dev->link_intr_cbs), 3992 user_cb, next); 3993 } else { 3994 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 3995 rte_eth_dev_callback_unregister(port_id, event, 3996 cb_fn, cb_arg); 3997 return -ENOMEM; 3998 } 3999 4000 } 4001 } while (++next_port <= last_port); 4002 4003 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 4004 return 0; 4005 } 4006 4007 int 4008 rte_eth_dev_callback_unregister(uint16_t port_id, 4009 enum rte_eth_event_type event, 4010 rte_eth_dev_cb_fn cb_fn, void *cb_arg) 4011 { 4012 int ret; 4013 struct rte_eth_dev *dev; 4014 struct rte_eth_dev_callback *cb, *next; 4015 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */ 4016 uint16_t last_port; 4017 4018 if (!cb_fn) 4019 return -EINVAL; 4020 4021 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) { 4022 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id); 4023 return -EINVAL; 4024 } 4025 4026 if (port_id == RTE_ETH_ALL) { 4027 next_port = 0; 4028 last_port = RTE_MAX_ETHPORTS - 1; 4029 } else { 4030 next_port = last_port = port_id; 4031 } 4032 4033 rte_spinlock_lock(&rte_eth_dev_cb_lock); 4034 4035 do { 4036 dev = &rte_eth_devices[next_port]; 4037 ret = 0; 4038 for (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL; 4039 cb = next) { 4040 4041 next = TAILQ_NEXT(cb, next); 4042 4043 if (cb->cb_fn != cb_fn || cb->event != event || 4044 (cb_arg != (void *)-1 && cb->cb_arg != cb_arg)) 4045 continue; 4046 4047 /* 4048 * if this callback is not executing right now, 4049 * then remove it. 4050 */ 4051 if (cb->active == 0) { 4052 TAILQ_REMOVE(&(dev->link_intr_cbs), cb, next); 4053 rte_free(cb); 4054 } else { 4055 ret = -EAGAIN; 4056 } 4057 } 4058 } while (++next_port <= last_port); 4059 4060 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 4061 return ret; 4062 } 4063 4064 int 4065 _rte_eth_dev_callback_process(struct rte_eth_dev *dev, 4066 enum rte_eth_event_type event, void *ret_param) 4067 { 4068 struct rte_eth_dev_callback *cb_lst; 4069 struct rte_eth_dev_callback dev_cb; 4070 int rc = 0; 4071 4072 rte_spinlock_lock(&rte_eth_dev_cb_lock); 4073 TAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) { 4074 if (cb_lst->cb_fn == NULL || cb_lst->event != event) 4075 continue; 4076 dev_cb = *cb_lst; 4077 cb_lst->active = 1; 4078 if (ret_param != NULL) 4079 dev_cb.ret_param = ret_param; 4080 4081 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 4082 rc = dev_cb.cb_fn(dev->data->port_id, dev_cb.event, 4083 dev_cb.cb_arg, dev_cb.ret_param); 4084 rte_spinlock_lock(&rte_eth_dev_cb_lock); 4085 cb_lst->active = 0; 4086 } 4087 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 4088 return rc; 4089 } 4090 4091 void 4092 rte_eth_dev_probing_finish(struct rte_eth_dev *dev) 4093 { 4094 if (dev == NULL) 4095 return; 4096 4097 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_NEW, NULL); 4098 4099 dev->state = RTE_ETH_DEV_ATTACHED; 4100 } 4101 4102 int 4103 rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data) 4104 { 4105 uint32_t vec; 4106 struct rte_eth_dev *dev; 4107 struct rte_intr_handle *intr_handle; 4108 uint16_t qid; 4109 int rc; 4110 4111 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4112 4113 dev = &rte_eth_devices[port_id]; 4114 4115 if (!dev->intr_handle) { 4116 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 4117 return -ENOTSUP; 4118 } 4119 4120 intr_handle = dev->intr_handle; 4121 if (!intr_handle->intr_vec) { 4122 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 4123 return -EPERM; 4124 } 4125 4126 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) { 4127 vec = intr_handle->intr_vec[qid]; 4128 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); 4129 if (rc && rc != -EEXIST) { 4130 RTE_ETHDEV_LOG(ERR, 4131 "p %u q %u rx ctl error op %d epfd %d vec %u\n", 4132 port_id, qid, op, epfd, vec); 4133 } 4134 } 4135 4136 return 0; 4137 } 4138 4139 int 4140 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id) 4141 { 4142 struct rte_intr_handle *intr_handle; 4143 struct rte_eth_dev *dev; 4144 unsigned int efd_idx; 4145 uint32_t vec; 4146 int fd; 4147 4148 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1); 4149 4150 dev = &rte_eth_devices[port_id]; 4151 4152 if (queue_id >= dev->data->nb_rx_queues) { 4153 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 4154 return -1; 4155 } 4156 4157 if (!dev->intr_handle) { 4158 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 4159 return -1; 4160 } 4161 4162 intr_handle = dev->intr_handle; 4163 if (!intr_handle->intr_vec) { 4164 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 4165 return -1; 4166 } 4167 4168 vec = intr_handle->intr_vec[queue_id]; 4169 efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ? 4170 (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec; 4171 fd = intr_handle->efds[efd_idx]; 4172 4173 return fd; 4174 } 4175 4176 const struct rte_memzone * 4177 rte_eth_dma_zone_reserve(const struct rte_eth_dev *dev, const char *ring_name, 4178 uint16_t queue_id, size_t size, unsigned align, 4179 int socket_id) 4180 { 4181 char z_name[RTE_MEMZONE_NAMESIZE]; 4182 const struct rte_memzone *mz; 4183 int rc; 4184 4185 rc = snprintf(z_name, sizeof(z_name), "eth_p%d_q%d_%s", 4186 dev->data->port_id, queue_id, ring_name); 4187 if (rc >= RTE_MEMZONE_NAMESIZE) { 4188 RTE_ETHDEV_LOG(ERR, "ring name too long\n"); 4189 rte_errno = ENAMETOOLONG; 4190 return NULL; 4191 } 4192 4193 mz = rte_memzone_lookup(z_name); 4194 if (mz) 4195 return mz; 4196 4197 return rte_memzone_reserve_aligned(z_name, size, socket_id, 4198 RTE_MEMZONE_IOVA_CONTIG, align); 4199 } 4200 4201 int 4202 rte_eth_dev_create(struct rte_device *device, const char *name, 4203 size_t priv_data_size, 4204 ethdev_bus_specific_init ethdev_bus_specific_init, 4205 void *bus_init_params, 4206 ethdev_init_t ethdev_init, void *init_params) 4207 { 4208 struct rte_eth_dev *ethdev; 4209 int retval; 4210 4211 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_init, -EINVAL); 4212 4213 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 4214 ethdev = rte_eth_dev_allocate(name); 4215 if (!ethdev) 4216 return -ENODEV; 4217 4218 if (priv_data_size) { 4219 ethdev->data->dev_private = rte_zmalloc_socket( 4220 name, priv_data_size, RTE_CACHE_LINE_SIZE, 4221 device->numa_node); 4222 4223 if (!ethdev->data->dev_private) { 4224 RTE_LOG(ERR, EAL, "failed to allocate private data"); 4225 retval = -ENOMEM; 4226 goto probe_failed; 4227 } 4228 } 4229 } else { 4230 ethdev = rte_eth_dev_attach_secondary(name); 4231 if (!ethdev) { 4232 RTE_LOG(ERR, EAL, "secondary process attach failed, " 4233 "ethdev doesn't exist"); 4234 return -ENODEV; 4235 } 4236 } 4237 4238 ethdev->device = device; 4239 4240 if (ethdev_bus_specific_init) { 4241 retval = ethdev_bus_specific_init(ethdev, bus_init_params); 4242 if (retval) { 4243 RTE_LOG(ERR, EAL, 4244 "ethdev bus specific initialisation failed"); 4245 goto probe_failed; 4246 } 4247 } 4248 4249 retval = ethdev_init(ethdev, init_params); 4250 if (retval) { 4251 RTE_LOG(ERR, EAL, "ethdev initialisation failed"); 4252 goto probe_failed; 4253 } 4254 4255 rte_eth_dev_probing_finish(ethdev); 4256 4257 return retval; 4258 4259 probe_failed: 4260 rte_eth_dev_release_port(ethdev); 4261 return retval; 4262 } 4263 4264 int 4265 rte_eth_dev_destroy(struct rte_eth_dev *ethdev, 4266 ethdev_uninit_t ethdev_uninit) 4267 { 4268 int ret; 4269 4270 ethdev = rte_eth_dev_allocated(ethdev->data->name); 4271 if (!ethdev) 4272 return -ENODEV; 4273 4274 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_uninit, -EINVAL); 4275 4276 ret = ethdev_uninit(ethdev); 4277 if (ret) 4278 return ret; 4279 4280 return rte_eth_dev_release_port(ethdev); 4281 } 4282 4283 int 4284 rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id, 4285 int epfd, int op, void *data) 4286 { 4287 uint32_t vec; 4288 struct rte_eth_dev *dev; 4289 struct rte_intr_handle *intr_handle; 4290 int rc; 4291 4292 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4293 4294 dev = &rte_eth_devices[port_id]; 4295 if (queue_id >= dev->data->nb_rx_queues) { 4296 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 4297 return -EINVAL; 4298 } 4299 4300 if (!dev->intr_handle) { 4301 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 4302 return -ENOTSUP; 4303 } 4304 4305 intr_handle = dev->intr_handle; 4306 if (!intr_handle->intr_vec) { 4307 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 4308 return -EPERM; 4309 } 4310 4311 vec = intr_handle->intr_vec[queue_id]; 4312 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); 4313 if (rc && rc != -EEXIST) { 4314 RTE_ETHDEV_LOG(ERR, 4315 "p %u q %u rx ctl error op %d epfd %d vec %u\n", 4316 port_id, queue_id, op, epfd, vec); 4317 return rc; 4318 } 4319 4320 return 0; 4321 } 4322 4323 int 4324 rte_eth_dev_rx_intr_enable(uint16_t port_id, 4325 uint16_t queue_id) 4326 { 4327 struct rte_eth_dev *dev; 4328 4329 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4330 4331 dev = &rte_eth_devices[port_id]; 4332 4333 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_enable, -ENOTSUP); 4334 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev, 4335 queue_id)); 4336 } 4337 4338 int 4339 rte_eth_dev_rx_intr_disable(uint16_t port_id, 4340 uint16_t queue_id) 4341 { 4342 struct rte_eth_dev *dev; 4343 4344 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4345 4346 dev = &rte_eth_devices[port_id]; 4347 4348 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_disable, -ENOTSUP); 4349 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev, 4350 queue_id)); 4351 } 4352 4353 4354 int 4355 rte_eth_dev_filter_supported(uint16_t port_id, 4356 enum rte_filter_type filter_type) 4357 { 4358 struct rte_eth_dev *dev; 4359 4360 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4361 4362 dev = &rte_eth_devices[port_id]; 4363 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP); 4364 return (*dev->dev_ops->filter_ctrl)(dev, filter_type, 4365 RTE_ETH_FILTER_NOP, NULL); 4366 } 4367 4368 int 4369 rte_eth_dev_filter_ctrl(uint16_t port_id, enum rte_filter_type filter_type, 4370 enum rte_filter_op filter_op, void *arg) 4371 { 4372 struct rte_eth_dev *dev; 4373 4374 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4375 4376 dev = &rte_eth_devices[port_id]; 4377 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP); 4378 return eth_err(port_id, (*dev->dev_ops->filter_ctrl)(dev, filter_type, 4379 filter_op, arg)); 4380 } 4381 4382 const struct rte_eth_rxtx_callback * 4383 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id, 4384 rte_rx_callback_fn fn, void *user_param) 4385 { 4386 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 4387 rte_errno = ENOTSUP; 4388 return NULL; 4389 #endif 4390 struct rte_eth_dev *dev; 4391 4392 /* check input parameters */ 4393 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 4394 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) { 4395 rte_errno = EINVAL; 4396 return NULL; 4397 } 4398 dev = &rte_eth_devices[port_id]; 4399 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) { 4400 rte_errno = EINVAL; 4401 return NULL; 4402 } 4403 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 4404 4405 if (cb == NULL) { 4406 rte_errno = ENOMEM; 4407 return NULL; 4408 } 4409 4410 cb->fn.rx = fn; 4411 cb->param = user_param; 4412 4413 rte_spinlock_lock(&rte_eth_rx_cb_lock); 4414 /* Add the callbacks in fifo order. */ 4415 struct rte_eth_rxtx_callback *tail = 4416 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; 4417 4418 if (!tail) { 4419 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id] = cb; 4420 4421 } else { 4422 while (tail->next) 4423 tail = tail->next; 4424 tail->next = cb; 4425 } 4426 rte_spinlock_unlock(&rte_eth_rx_cb_lock); 4427 4428 return cb; 4429 } 4430 4431 const struct rte_eth_rxtx_callback * 4432 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id, 4433 rte_rx_callback_fn fn, void *user_param) 4434 { 4435 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 4436 rte_errno = ENOTSUP; 4437 return NULL; 4438 #endif 4439 /* check input parameters */ 4440 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 4441 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) { 4442 rte_errno = EINVAL; 4443 return NULL; 4444 } 4445 4446 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 4447 4448 if (cb == NULL) { 4449 rte_errno = ENOMEM; 4450 return NULL; 4451 } 4452 4453 cb->fn.rx = fn; 4454 cb->param = user_param; 4455 4456 rte_spinlock_lock(&rte_eth_rx_cb_lock); 4457 /* Add the callbacks at fisrt position*/ 4458 cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; 4459 rte_smp_wmb(); 4460 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id] = cb; 4461 rte_spinlock_unlock(&rte_eth_rx_cb_lock); 4462 4463 return cb; 4464 } 4465 4466 const struct rte_eth_rxtx_callback * 4467 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id, 4468 rte_tx_callback_fn fn, void *user_param) 4469 { 4470 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 4471 rte_errno = ENOTSUP; 4472 return NULL; 4473 #endif 4474 struct rte_eth_dev *dev; 4475 4476 /* check input parameters */ 4477 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 4478 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) { 4479 rte_errno = EINVAL; 4480 return NULL; 4481 } 4482 4483 dev = &rte_eth_devices[port_id]; 4484 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) { 4485 rte_errno = EINVAL; 4486 return NULL; 4487 } 4488 4489 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 4490 4491 if (cb == NULL) { 4492 rte_errno = ENOMEM; 4493 return NULL; 4494 } 4495 4496 cb->fn.tx = fn; 4497 cb->param = user_param; 4498 4499 rte_spinlock_lock(&rte_eth_tx_cb_lock); 4500 /* Add the callbacks in fifo order. */ 4501 struct rte_eth_rxtx_callback *tail = 4502 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id]; 4503 4504 if (!tail) { 4505 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id] = cb; 4506 4507 } else { 4508 while (tail->next) 4509 tail = tail->next; 4510 tail->next = cb; 4511 } 4512 rte_spinlock_unlock(&rte_eth_tx_cb_lock); 4513 4514 return cb; 4515 } 4516 4517 int 4518 rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id, 4519 const struct rte_eth_rxtx_callback *user_cb) 4520 { 4521 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 4522 return -ENOTSUP; 4523 #endif 4524 /* Check input parameters. */ 4525 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 4526 if (user_cb == NULL || 4527 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) 4528 return -EINVAL; 4529 4530 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 4531 struct rte_eth_rxtx_callback *cb; 4532 struct rte_eth_rxtx_callback **prev_cb; 4533 int ret = -EINVAL; 4534 4535 rte_spinlock_lock(&rte_eth_rx_cb_lock); 4536 prev_cb = &dev->post_rx_burst_cbs[queue_id]; 4537 for (; *prev_cb != NULL; prev_cb = &cb->next) { 4538 cb = *prev_cb; 4539 if (cb == user_cb) { 4540 /* Remove the user cb from the callback list. */ 4541 *prev_cb = cb->next; 4542 ret = 0; 4543 break; 4544 } 4545 } 4546 rte_spinlock_unlock(&rte_eth_rx_cb_lock); 4547 4548 return ret; 4549 } 4550 4551 int 4552 rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id, 4553 const struct rte_eth_rxtx_callback *user_cb) 4554 { 4555 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 4556 return -ENOTSUP; 4557 #endif 4558 /* Check input parameters. */ 4559 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 4560 if (user_cb == NULL || 4561 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) 4562 return -EINVAL; 4563 4564 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 4565 int ret = -EINVAL; 4566 struct rte_eth_rxtx_callback *cb; 4567 struct rte_eth_rxtx_callback **prev_cb; 4568 4569 rte_spinlock_lock(&rte_eth_tx_cb_lock); 4570 prev_cb = &dev->pre_tx_burst_cbs[queue_id]; 4571 for (; *prev_cb != NULL; prev_cb = &cb->next) { 4572 cb = *prev_cb; 4573 if (cb == user_cb) { 4574 /* Remove the user cb from the callback list. */ 4575 *prev_cb = cb->next; 4576 ret = 0; 4577 break; 4578 } 4579 } 4580 rte_spinlock_unlock(&rte_eth_tx_cb_lock); 4581 4582 return ret; 4583 } 4584 4585 int 4586 rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id, 4587 struct rte_eth_rxq_info *qinfo) 4588 { 4589 struct rte_eth_dev *dev; 4590 4591 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4592 4593 if (qinfo == NULL) 4594 return -EINVAL; 4595 4596 dev = &rte_eth_devices[port_id]; 4597 if (queue_id >= dev->data->nb_rx_queues) { 4598 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 4599 return -EINVAL; 4600 } 4601 4602 if (rte_eth_dev_is_rx_hairpin_queue(dev, queue_id)) { 4603 RTE_ETHDEV_LOG(INFO, 4604 "Can't get hairpin Rx queue %"PRIu16" info of device with port_id=%"PRIu16"\n", 4605 queue_id, port_id); 4606 return -EINVAL; 4607 } 4608 4609 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rxq_info_get, -ENOTSUP); 4610 4611 memset(qinfo, 0, sizeof(*qinfo)); 4612 dev->dev_ops->rxq_info_get(dev, queue_id, qinfo); 4613 return 0; 4614 } 4615 4616 int 4617 rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id, 4618 struct rte_eth_txq_info *qinfo) 4619 { 4620 struct rte_eth_dev *dev; 4621 4622 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4623 4624 if (qinfo == NULL) 4625 return -EINVAL; 4626 4627 dev = &rte_eth_devices[port_id]; 4628 if (queue_id >= dev->data->nb_tx_queues) { 4629 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id); 4630 return -EINVAL; 4631 } 4632 4633 if (rte_eth_dev_is_tx_hairpin_queue(dev, queue_id)) { 4634 RTE_ETHDEV_LOG(INFO, 4635 "Can't get hairpin Tx queue %"PRIu16" info of device with port_id=%"PRIu16"\n", 4636 queue_id, port_id); 4637 return -EINVAL; 4638 } 4639 4640 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->txq_info_get, -ENOTSUP); 4641 4642 memset(qinfo, 0, sizeof(*qinfo)); 4643 dev->dev_ops->txq_info_get(dev, queue_id, qinfo); 4644 4645 return 0; 4646 } 4647 4648 int 4649 rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id, 4650 struct rte_eth_burst_mode *mode) 4651 { 4652 struct rte_eth_dev *dev; 4653 4654 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4655 4656 if (mode == NULL) 4657 return -EINVAL; 4658 4659 dev = &rte_eth_devices[port_id]; 4660 4661 if (queue_id >= dev->data->nb_rx_queues) { 4662 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 4663 return -EINVAL; 4664 } 4665 4666 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_burst_mode_get, -ENOTSUP); 4667 memset(mode, 0, sizeof(*mode)); 4668 return eth_err(port_id, 4669 dev->dev_ops->rx_burst_mode_get(dev, queue_id, mode)); 4670 } 4671 4672 int 4673 rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id, 4674 struct rte_eth_burst_mode *mode) 4675 { 4676 struct rte_eth_dev *dev; 4677 4678 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4679 4680 if (mode == NULL) 4681 return -EINVAL; 4682 4683 dev = &rte_eth_devices[port_id]; 4684 4685 if (queue_id >= dev->data->nb_tx_queues) { 4686 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id); 4687 return -EINVAL; 4688 } 4689 4690 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_burst_mode_get, -ENOTSUP); 4691 memset(mode, 0, sizeof(*mode)); 4692 return eth_err(port_id, 4693 dev->dev_ops->tx_burst_mode_get(dev, queue_id, mode)); 4694 } 4695 4696 int 4697 rte_eth_dev_set_mc_addr_list(uint16_t port_id, 4698 struct rte_ether_addr *mc_addr_set, 4699 uint32_t nb_mc_addr) 4700 { 4701 struct rte_eth_dev *dev; 4702 4703 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4704 4705 dev = &rte_eth_devices[port_id]; 4706 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP); 4707 return eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev, 4708 mc_addr_set, nb_mc_addr)); 4709 } 4710 4711 int 4712 rte_eth_timesync_enable(uint16_t port_id) 4713 { 4714 struct rte_eth_dev *dev; 4715 4716 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4717 dev = &rte_eth_devices[port_id]; 4718 4719 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP); 4720 return eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev)); 4721 } 4722 4723 int 4724 rte_eth_timesync_disable(uint16_t port_id) 4725 { 4726 struct rte_eth_dev *dev; 4727 4728 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4729 dev = &rte_eth_devices[port_id]; 4730 4731 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP); 4732 return eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev)); 4733 } 4734 4735 int 4736 rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp, 4737 uint32_t flags) 4738 { 4739 struct rte_eth_dev *dev; 4740 4741 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4742 dev = &rte_eth_devices[port_id]; 4743 4744 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp, -ENOTSUP); 4745 return eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp) 4746 (dev, timestamp, flags)); 4747 } 4748 4749 int 4750 rte_eth_timesync_read_tx_timestamp(uint16_t port_id, 4751 struct timespec *timestamp) 4752 { 4753 struct rte_eth_dev *dev; 4754 4755 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4756 dev = &rte_eth_devices[port_id]; 4757 4758 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp, -ENOTSUP); 4759 return eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp) 4760 (dev, timestamp)); 4761 } 4762 4763 int 4764 rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta) 4765 { 4766 struct rte_eth_dev *dev; 4767 4768 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4769 dev = &rte_eth_devices[port_id]; 4770 4771 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_adjust_time, -ENOTSUP); 4772 return eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev, 4773 delta)); 4774 } 4775 4776 int 4777 rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp) 4778 { 4779 struct rte_eth_dev *dev; 4780 4781 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4782 dev = &rte_eth_devices[port_id]; 4783 4784 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_time, -ENOTSUP); 4785 return eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev, 4786 timestamp)); 4787 } 4788 4789 int 4790 rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp) 4791 { 4792 struct rte_eth_dev *dev; 4793 4794 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4795 dev = &rte_eth_devices[port_id]; 4796 4797 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_write_time, -ENOTSUP); 4798 return eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev, 4799 timestamp)); 4800 } 4801 4802 int 4803 rte_eth_read_clock(uint16_t port_id, uint64_t *clock) 4804 { 4805 struct rte_eth_dev *dev; 4806 4807 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4808 dev = &rte_eth_devices[port_id]; 4809 4810 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->read_clock, -ENOTSUP); 4811 return eth_err(port_id, (*dev->dev_ops->read_clock)(dev, clock)); 4812 } 4813 4814 int 4815 rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info) 4816 { 4817 struct rte_eth_dev *dev; 4818 4819 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4820 4821 dev = &rte_eth_devices[port_id]; 4822 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg, -ENOTSUP); 4823 return eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info)); 4824 } 4825 4826 int 4827 rte_eth_dev_get_eeprom_length(uint16_t port_id) 4828 { 4829 struct rte_eth_dev *dev; 4830 4831 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4832 4833 dev = &rte_eth_devices[port_id]; 4834 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom_length, -ENOTSUP); 4835 return eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev)); 4836 } 4837 4838 int 4839 rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info) 4840 { 4841 struct rte_eth_dev *dev; 4842 4843 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4844 4845 dev = &rte_eth_devices[port_id]; 4846 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom, -ENOTSUP); 4847 return eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info)); 4848 } 4849 4850 int 4851 rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info) 4852 { 4853 struct rte_eth_dev *dev; 4854 4855 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4856 4857 dev = &rte_eth_devices[port_id]; 4858 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_eeprom, -ENOTSUP); 4859 return eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info)); 4860 } 4861 4862 int 4863 rte_eth_dev_get_module_info(uint16_t port_id, 4864 struct rte_eth_dev_module_info *modinfo) 4865 { 4866 struct rte_eth_dev *dev; 4867 4868 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4869 4870 dev = &rte_eth_devices[port_id]; 4871 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_info, -ENOTSUP); 4872 return (*dev->dev_ops->get_module_info)(dev, modinfo); 4873 } 4874 4875 int 4876 rte_eth_dev_get_module_eeprom(uint16_t port_id, 4877 struct rte_dev_eeprom_info *info) 4878 { 4879 struct rte_eth_dev *dev; 4880 4881 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4882 4883 dev = &rte_eth_devices[port_id]; 4884 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_eeprom, -ENOTSUP); 4885 return (*dev->dev_ops->get_module_eeprom)(dev, info); 4886 } 4887 4888 int 4889 rte_eth_dev_get_dcb_info(uint16_t port_id, 4890 struct rte_eth_dcb_info *dcb_info) 4891 { 4892 struct rte_eth_dev *dev; 4893 4894 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4895 4896 dev = &rte_eth_devices[port_id]; 4897 memset(dcb_info, 0, sizeof(struct rte_eth_dcb_info)); 4898 4899 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_dcb_info, -ENOTSUP); 4900 return eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info)); 4901 } 4902 4903 int 4904 rte_eth_dev_l2_tunnel_eth_type_conf(uint16_t port_id, 4905 struct rte_eth_l2_tunnel_conf *l2_tunnel) 4906 { 4907 struct rte_eth_dev *dev; 4908 4909 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4910 if (l2_tunnel == NULL) { 4911 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n"); 4912 return -EINVAL; 4913 } 4914 4915 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) { 4916 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 4917 return -EINVAL; 4918 } 4919 4920 dev = &rte_eth_devices[port_id]; 4921 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_eth_type_conf, 4922 -ENOTSUP); 4923 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_eth_type_conf)(dev, 4924 l2_tunnel)); 4925 } 4926 4927 int 4928 rte_eth_dev_l2_tunnel_offload_set(uint16_t port_id, 4929 struct rte_eth_l2_tunnel_conf *l2_tunnel, 4930 uint32_t mask, 4931 uint8_t en) 4932 { 4933 struct rte_eth_dev *dev; 4934 4935 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4936 4937 if (l2_tunnel == NULL) { 4938 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n"); 4939 return -EINVAL; 4940 } 4941 4942 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) { 4943 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 4944 return -EINVAL; 4945 } 4946 4947 if (mask == 0) { 4948 RTE_ETHDEV_LOG(ERR, "Mask should have a value\n"); 4949 return -EINVAL; 4950 } 4951 4952 dev = &rte_eth_devices[port_id]; 4953 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_offload_set, 4954 -ENOTSUP); 4955 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_offload_set)(dev, 4956 l2_tunnel, mask, en)); 4957 } 4958 4959 static void 4960 rte_eth_dev_adjust_nb_desc(uint16_t *nb_desc, 4961 const struct rte_eth_desc_lim *desc_lim) 4962 { 4963 if (desc_lim->nb_align != 0) 4964 *nb_desc = RTE_ALIGN_CEIL(*nb_desc, desc_lim->nb_align); 4965 4966 if (desc_lim->nb_max != 0) 4967 *nb_desc = RTE_MIN(*nb_desc, desc_lim->nb_max); 4968 4969 *nb_desc = RTE_MAX(*nb_desc, desc_lim->nb_min); 4970 } 4971 4972 int 4973 rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id, 4974 uint16_t *nb_rx_desc, 4975 uint16_t *nb_tx_desc) 4976 { 4977 struct rte_eth_dev_info dev_info; 4978 int ret; 4979 4980 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4981 4982 ret = rte_eth_dev_info_get(port_id, &dev_info); 4983 if (ret != 0) 4984 return ret; 4985 4986 if (nb_rx_desc != NULL) 4987 rte_eth_dev_adjust_nb_desc(nb_rx_desc, &dev_info.rx_desc_lim); 4988 4989 if (nb_tx_desc != NULL) 4990 rte_eth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim); 4991 4992 return 0; 4993 } 4994 4995 int 4996 rte_eth_dev_hairpin_capability_get(uint16_t port_id, 4997 struct rte_eth_hairpin_cap *cap) 4998 { 4999 struct rte_eth_dev *dev; 5000 5001 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 5002 5003 dev = &rte_eth_devices[port_id]; 5004 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->hairpin_cap_get, -ENOTSUP); 5005 memset(cap, 0, sizeof(*cap)); 5006 return eth_err(port_id, (*dev->dev_ops->hairpin_cap_get)(dev, cap)); 5007 } 5008 5009 int 5010 rte_eth_dev_is_rx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id) 5011 { 5012 if (dev->data->rx_queue_state[queue_id] == 5013 RTE_ETH_QUEUE_STATE_HAIRPIN) 5014 return 1; 5015 return 0; 5016 } 5017 5018 int 5019 rte_eth_dev_is_tx_hairpin_queue(struct rte_eth_dev *dev, uint16_t queue_id) 5020 { 5021 if (dev->data->tx_queue_state[queue_id] == 5022 RTE_ETH_QUEUE_STATE_HAIRPIN) 5023 return 1; 5024 return 0; 5025 } 5026 5027 int 5028 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool) 5029 { 5030 struct rte_eth_dev *dev; 5031 5032 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 5033 5034 if (pool == NULL) 5035 return -EINVAL; 5036 5037 dev = &rte_eth_devices[port_id]; 5038 5039 if (*dev->dev_ops->pool_ops_supported == NULL) 5040 return 1; /* all pools are supported */ 5041 5042 return (*dev->dev_ops->pool_ops_supported)(dev, pool); 5043 } 5044 5045 /** 5046 * A set of values to describe the possible states of a switch domain. 5047 */ 5048 enum rte_eth_switch_domain_state { 5049 RTE_ETH_SWITCH_DOMAIN_UNUSED = 0, 5050 RTE_ETH_SWITCH_DOMAIN_ALLOCATED 5051 }; 5052 5053 /** 5054 * Array of switch domains available for allocation. Array is sized to 5055 * RTE_MAX_ETHPORTS elements as there cannot be more active switch domains than 5056 * ethdev ports in a single process. 5057 */ 5058 static struct rte_eth_dev_switch { 5059 enum rte_eth_switch_domain_state state; 5060 } rte_eth_switch_domains[RTE_MAX_ETHPORTS]; 5061 5062 int 5063 rte_eth_switch_domain_alloc(uint16_t *domain_id) 5064 { 5065 unsigned int i; 5066 5067 *domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 5068 5069 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 5070 if (rte_eth_switch_domains[i].state == 5071 RTE_ETH_SWITCH_DOMAIN_UNUSED) { 5072 rte_eth_switch_domains[i].state = 5073 RTE_ETH_SWITCH_DOMAIN_ALLOCATED; 5074 *domain_id = i; 5075 return 0; 5076 } 5077 } 5078 5079 return -ENOSPC; 5080 } 5081 5082 int 5083 rte_eth_switch_domain_free(uint16_t domain_id) 5084 { 5085 if (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID || 5086 domain_id >= RTE_MAX_ETHPORTS) 5087 return -EINVAL; 5088 5089 if (rte_eth_switch_domains[domain_id].state != 5090 RTE_ETH_SWITCH_DOMAIN_ALLOCATED) 5091 return -EINVAL; 5092 5093 rte_eth_switch_domains[domain_id].state = RTE_ETH_SWITCH_DOMAIN_UNUSED; 5094 5095 return 0; 5096 } 5097 5098 static int 5099 rte_eth_devargs_tokenise(struct rte_kvargs *arglist, const char *str_in) 5100 { 5101 int state; 5102 struct rte_kvargs_pair *pair; 5103 char *letter; 5104 5105 arglist->str = strdup(str_in); 5106 if (arglist->str == NULL) 5107 return -ENOMEM; 5108 5109 letter = arglist->str; 5110 state = 0; 5111 arglist->count = 0; 5112 pair = &arglist->pairs[0]; 5113 while (1) { 5114 switch (state) { 5115 case 0: /* Initial */ 5116 if (*letter == '=') 5117 return -EINVAL; 5118 else if (*letter == '\0') 5119 return 0; 5120 5121 state = 1; 5122 pair->key = letter; 5123 /* fall-thru */ 5124 5125 case 1: /* Parsing key */ 5126 if (*letter == '=') { 5127 *letter = '\0'; 5128 pair->value = letter + 1; 5129 state = 2; 5130 } else if (*letter == ',' || *letter == '\0') 5131 return -EINVAL; 5132 break; 5133 5134 5135 case 2: /* Parsing value */ 5136 if (*letter == '[') 5137 state = 3; 5138 else if (*letter == ',') { 5139 *letter = '\0'; 5140 arglist->count++; 5141 pair = &arglist->pairs[arglist->count]; 5142 state = 0; 5143 } else if (*letter == '\0') { 5144 letter--; 5145 arglist->count++; 5146 pair = &arglist->pairs[arglist->count]; 5147 state = 0; 5148 } 5149 break; 5150 5151 case 3: /* Parsing list */ 5152 if (*letter == ']') 5153 state = 2; 5154 else if (*letter == '\0') 5155 return -EINVAL; 5156 break; 5157 } 5158 letter++; 5159 } 5160 } 5161 5162 int 5163 rte_eth_devargs_parse(const char *dargs, struct rte_eth_devargs *eth_da) 5164 { 5165 struct rte_kvargs args; 5166 struct rte_kvargs_pair *pair; 5167 unsigned int i; 5168 int result = 0; 5169 5170 memset(eth_da, 0, sizeof(*eth_da)); 5171 5172 result = rte_eth_devargs_tokenise(&args, dargs); 5173 if (result < 0) 5174 goto parse_cleanup; 5175 5176 for (i = 0; i < args.count; i++) { 5177 pair = &args.pairs[i]; 5178 if (strcmp("representor", pair->key) == 0) { 5179 result = rte_eth_devargs_parse_list(pair->value, 5180 rte_eth_devargs_parse_representor_ports, 5181 eth_da); 5182 if (result < 0) 5183 goto parse_cleanup; 5184 } 5185 } 5186 5187 parse_cleanup: 5188 if (args.str) 5189 free(args.str); 5190 5191 return result; 5192 } 5193 5194 RTE_INIT(ethdev_init_log) 5195 { 5196 rte_eth_dev_logtype = rte_log_register("lib.ethdev"); 5197 if (rte_eth_dev_logtype >= 0) 5198 rte_log_set_level(rte_eth_dev_logtype, RTE_LOG_INFO); 5199 } 5200