1*d30ea906Sjfb8856606 /* SPDX-License-Identifier: BSD-3-Clause 2*d30ea906Sjfb8856606 * Copyright(c) 2010-2017 Intel Corporation 3*d30ea906Sjfb8856606 */ 4*d30ea906Sjfb8856606 5*d30ea906Sjfb8856606 #include <sys/types.h> 6*d30ea906Sjfb8856606 #include <sys/queue.h> 7*d30ea906Sjfb8856606 #include <ctype.h> 8*d30ea906Sjfb8856606 #include <stdio.h> 9*d30ea906Sjfb8856606 #include <stdlib.h> 10*d30ea906Sjfb8856606 #include <string.h> 11*d30ea906Sjfb8856606 #include <stdarg.h> 12*d30ea906Sjfb8856606 #include <errno.h> 13*d30ea906Sjfb8856606 #include <stdbool.h> 14*d30ea906Sjfb8856606 #include <stdint.h> 15*d30ea906Sjfb8856606 #include <inttypes.h> 16*d30ea906Sjfb8856606 #include <netinet/in.h> 17*d30ea906Sjfb8856606 18*d30ea906Sjfb8856606 #include <rte_byteorder.h> 19*d30ea906Sjfb8856606 #include <rte_log.h> 20*d30ea906Sjfb8856606 #include <rte_debug.h> 21*d30ea906Sjfb8856606 #include <rte_interrupts.h> 22*d30ea906Sjfb8856606 #include <rte_memory.h> 23*d30ea906Sjfb8856606 #include <rte_memcpy.h> 24*d30ea906Sjfb8856606 #include <rte_memzone.h> 25*d30ea906Sjfb8856606 #include <rte_launch.h> 26*d30ea906Sjfb8856606 #include <rte_eal.h> 27*d30ea906Sjfb8856606 #include <rte_per_lcore.h> 28*d30ea906Sjfb8856606 #include <rte_lcore.h> 29*d30ea906Sjfb8856606 #include <rte_atomic.h> 30*d30ea906Sjfb8856606 #include <rte_branch_prediction.h> 31*d30ea906Sjfb8856606 #include <rte_common.h> 32*d30ea906Sjfb8856606 #include <rte_mempool.h> 33*d30ea906Sjfb8856606 #include <rte_malloc.h> 34*d30ea906Sjfb8856606 #include <rte_mbuf.h> 35*d30ea906Sjfb8856606 #include <rte_errno.h> 36*d30ea906Sjfb8856606 #include <rte_spinlock.h> 37*d30ea906Sjfb8856606 #include <rte_string_fns.h> 38*d30ea906Sjfb8856606 #include <rte_kvargs.h> 39*d30ea906Sjfb8856606 #include <rte_class.h> 40*d30ea906Sjfb8856606 41*d30ea906Sjfb8856606 #include "rte_ether.h" 42*d30ea906Sjfb8856606 #include "rte_ethdev.h" 43*d30ea906Sjfb8856606 #include "rte_ethdev_driver.h" 44*d30ea906Sjfb8856606 #include "ethdev_profile.h" 45*d30ea906Sjfb8856606 #include "ethdev_private.h" 46*d30ea906Sjfb8856606 47*d30ea906Sjfb8856606 int rte_eth_dev_logtype; 48*d30ea906Sjfb8856606 49*d30ea906Sjfb8856606 static const char *MZ_RTE_ETH_DEV_DATA = "rte_eth_dev_data"; 50*d30ea906Sjfb8856606 struct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS]; 51*d30ea906Sjfb8856606 static uint16_t eth_dev_last_created_port; 52*d30ea906Sjfb8856606 53*d30ea906Sjfb8856606 /* spinlock for eth device callbacks */ 54*d30ea906Sjfb8856606 static rte_spinlock_t rte_eth_dev_cb_lock = RTE_SPINLOCK_INITIALIZER; 55*d30ea906Sjfb8856606 56*d30ea906Sjfb8856606 /* spinlock for add/remove rx callbacks */ 57*d30ea906Sjfb8856606 static rte_spinlock_t rte_eth_rx_cb_lock = RTE_SPINLOCK_INITIALIZER; 58*d30ea906Sjfb8856606 59*d30ea906Sjfb8856606 /* spinlock for add/remove tx callbacks */ 60*d30ea906Sjfb8856606 static rte_spinlock_t rte_eth_tx_cb_lock = RTE_SPINLOCK_INITIALIZER; 61*d30ea906Sjfb8856606 62*d30ea906Sjfb8856606 /* spinlock for shared data allocation */ 63*d30ea906Sjfb8856606 static rte_spinlock_t rte_eth_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 64*d30ea906Sjfb8856606 65*d30ea906Sjfb8856606 /* store statistics names and its offset in stats structure */ 66*d30ea906Sjfb8856606 struct rte_eth_xstats_name_off { 67*d30ea906Sjfb8856606 char name[RTE_ETH_XSTATS_NAME_SIZE]; 68*d30ea906Sjfb8856606 unsigned offset; 69*d30ea906Sjfb8856606 }; 70*d30ea906Sjfb8856606 71*d30ea906Sjfb8856606 /* Shared memory between primary and secondary processes. */ 72*d30ea906Sjfb8856606 static struct { 73*d30ea906Sjfb8856606 uint64_t next_owner_id; 74*d30ea906Sjfb8856606 rte_spinlock_t ownership_lock; 75*d30ea906Sjfb8856606 struct rte_eth_dev_data data[RTE_MAX_ETHPORTS]; 76*d30ea906Sjfb8856606 } *rte_eth_dev_shared_data; 77*d30ea906Sjfb8856606 78*d30ea906Sjfb8856606 static const struct rte_eth_xstats_name_off rte_stats_strings[] = { 79*d30ea906Sjfb8856606 {"rx_good_packets", offsetof(struct rte_eth_stats, ipackets)}, 80*d30ea906Sjfb8856606 {"tx_good_packets", offsetof(struct rte_eth_stats, opackets)}, 81*d30ea906Sjfb8856606 {"rx_good_bytes", offsetof(struct rte_eth_stats, ibytes)}, 82*d30ea906Sjfb8856606 {"tx_good_bytes", offsetof(struct rte_eth_stats, obytes)}, 83*d30ea906Sjfb8856606 {"rx_missed_errors", offsetof(struct rte_eth_stats, imissed)}, 84*d30ea906Sjfb8856606 {"rx_errors", offsetof(struct rte_eth_stats, ierrors)}, 85*d30ea906Sjfb8856606 {"tx_errors", offsetof(struct rte_eth_stats, oerrors)}, 86*d30ea906Sjfb8856606 {"rx_mbuf_allocation_errors", offsetof(struct rte_eth_stats, 87*d30ea906Sjfb8856606 rx_nombuf)}, 88*d30ea906Sjfb8856606 }; 89*d30ea906Sjfb8856606 90*d30ea906Sjfb8856606 #define RTE_NB_STATS (sizeof(rte_stats_strings) / sizeof(rte_stats_strings[0])) 91*d30ea906Sjfb8856606 92*d30ea906Sjfb8856606 static const struct rte_eth_xstats_name_off rte_rxq_stats_strings[] = { 93*d30ea906Sjfb8856606 {"packets", offsetof(struct rte_eth_stats, q_ipackets)}, 94*d30ea906Sjfb8856606 {"bytes", offsetof(struct rte_eth_stats, q_ibytes)}, 95*d30ea906Sjfb8856606 {"errors", offsetof(struct rte_eth_stats, q_errors)}, 96*d30ea906Sjfb8856606 }; 97*d30ea906Sjfb8856606 98*d30ea906Sjfb8856606 #define RTE_NB_RXQ_STATS (sizeof(rte_rxq_stats_strings) / \ 99*d30ea906Sjfb8856606 sizeof(rte_rxq_stats_strings[0])) 100*d30ea906Sjfb8856606 101*d30ea906Sjfb8856606 static const struct rte_eth_xstats_name_off rte_txq_stats_strings[] = { 102*d30ea906Sjfb8856606 {"packets", offsetof(struct rte_eth_stats, q_opackets)}, 103*d30ea906Sjfb8856606 {"bytes", offsetof(struct rte_eth_stats, q_obytes)}, 104*d30ea906Sjfb8856606 }; 105*d30ea906Sjfb8856606 #define RTE_NB_TXQ_STATS (sizeof(rte_txq_stats_strings) / \ 106*d30ea906Sjfb8856606 sizeof(rte_txq_stats_strings[0])) 107*d30ea906Sjfb8856606 108*d30ea906Sjfb8856606 #define RTE_RX_OFFLOAD_BIT2STR(_name) \ 109*d30ea906Sjfb8856606 { DEV_RX_OFFLOAD_##_name, #_name } 110*d30ea906Sjfb8856606 111*d30ea906Sjfb8856606 static const struct { 112*d30ea906Sjfb8856606 uint64_t offload; 113*d30ea906Sjfb8856606 const char *name; 114*d30ea906Sjfb8856606 } rte_rx_offload_names[] = { 115*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(VLAN_STRIP), 116*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(IPV4_CKSUM), 117*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(UDP_CKSUM), 118*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(TCP_CKSUM), 119*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(TCP_LRO), 120*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(QINQ_STRIP), 121*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM), 122*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(MACSEC_STRIP), 123*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(HEADER_SPLIT), 124*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(VLAN_FILTER), 125*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(VLAN_EXTEND), 126*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(JUMBO_FRAME), 127*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(SCATTER), 128*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(TIMESTAMP), 129*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(SECURITY), 130*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC), 131*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM), 132*d30ea906Sjfb8856606 RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), 133*d30ea906Sjfb8856606 }; 134*d30ea906Sjfb8856606 135*d30ea906Sjfb8856606 #undef RTE_RX_OFFLOAD_BIT2STR 136*d30ea906Sjfb8856606 137*d30ea906Sjfb8856606 #define RTE_TX_OFFLOAD_BIT2STR(_name) \ 138*d30ea906Sjfb8856606 { DEV_TX_OFFLOAD_##_name, #_name } 139*d30ea906Sjfb8856606 140*d30ea906Sjfb8856606 static const struct { 141*d30ea906Sjfb8856606 uint64_t offload; 142*d30ea906Sjfb8856606 const char *name; 143*d30ea906Sjfb8856606 } rte_tx_offload_names[] = { 144*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(VLAN_INSERT), 145*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(IPV4_CKSUM), 146*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(UDP_CKSUM), 147*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(TCP_CKSUM), 148*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(SCTP_CKSUM), 149*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(TCP_TSO), 150*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(UDP_TSO), 151*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM), 152*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(QINQ_INSERT), 153*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(VXLAN_TNL_TSO), 154*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(GRE_TNL_TSO), 155*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(IPIP_TNL_TSO), 156*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(GENEVE_TNL_TSO), 157*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(MACSEC_INSERT), 158*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(MT_LOCKFREE), 159*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(MULTI_SEGS), 160*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(MBUF_FAST_FREE), 161*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(SECURITY), 162*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO), 163*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO), 164*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM), 165*d30ea906Sjfb8856606 RTE_TX_OFFLOAD_BIT2STR(MATCH_METADATA), 166*d30ea906Sjfb8856606 }; 167*d30ea906Sjfb8856606 168*d30ea906Sjfb8856606 #undef RTE_TX_OFFLOAD_BIT2STR 169*d30ea906Sjfb8856606 170*d30ea906Sjfb8856606 /** 171*d30ea906Sjfb8856606 * The user application callback description. 172*d30ea906Sjfb8856606 * 173*d30ea906Sjfb8856606 * It contains callback address to be registered by user application, 174*d30ea906Sjfb8856606 * the pointer to the parameters for callback, and the event type. 175*d30ea906Sjfb8856606 */ 176*d30ea906Sjfb8856606 struct rte_eth_dev_callback { 177*d30ea906Sjfb8856606 TAILQ_ENTRY(rte_eth_dev_callback) next; /**< Callbacks list */ 178*d30ea906Sjfb8856606 rte_eth_dev_cb_fn cb_fn; /**< Callback address */ 179*d30ea906Sjfb8856606 void *cb_arg; /**< Parameter for callback */ 180*d30ea906Sjfb8856606 void *ret_param; /**< Return parameter */ 181*d30ea906Sjfb8856606 enum rte_eth_event_type event; /**< Interrupt event type */ 182*d30ea906Sjfb8856606 uint32_t active; /**< Callback is executing */ 183*d30ea906Sjfb8856606 }; 184*d30ea906Sjfb8856606 185*d30ea906Sjfb8856606 enum { 186*d30ea906Sjfb8856606 STAT_QMAP_TX = 0, 187*d30ea906Sjfb8856606 STAT_QMAP_RX 188*d30ea906Sjfb8856606 }; 189*d30ea906Sjfb8856606 190*d30ea906Sjfb8856606 int 191*d30ea906Sjfb8856606 rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs_str) 192*d30ea906Sjfb8856606 { 193*d30ea906Sjfb8856606 int ret; 194*d30ea906Sjfb8856606 struct rte_devargs devargs = {.args = NULL}; 195*d30ea906Sjfb8856606 const char *bus_param_key; 196*d30ea906Sjfb8856606 char *bus_str = NULL; 197*d30ea906Sjfb8856606 char *cls_str = NULL; 198*d30ea906Sjfb8856606 int str_size; 199*d30ea906Sjfb8856606 200*d30ea906Sjfb8856606 memset(iter, 0, sizeof(*iter)); 201*d30ea906Sjfb8856606 202*d30ea906Sjfb8856606 /* 203*d30ea906Sjfb8856606 * The devargs string may use various syntaxes: 204*d30ea906Sjfb8856606 * - 0000:08:00.0,representor=[1-3] 205*d30ea906Sjfb8856606 * - pci:0000:06:00.0,representor=[0,5] 206*d30ea906Sjfb8856606 * - class=eth,mac=00:11:22:33:44:55 207*d30ea906Sjfb8856606 * A new syntax is in development (not yet supported): 208*d30ea906Sjfb8856606 * - bus=X,paramX=x/class=Y,paramY=y/driver=Z,paramZ=z 209*d30ea906Sjfb8856606 */ 210*d30ea906Sjfb8856606 211*d30ea906Sjfb8856606 /* 212*d30ea906Sjfb8856606 * Handle pure class filter (i.e. without any bus-level argument), 213*d30ea906Sjfb8856606 * from future new syntax. 214*d30ea906Sjfb8856606 * rte_devargs_parse() is not yet supporting the new syntax, 215*d30ea906Sjfb8856606 * that's why this simple case is temporarily parsed here. 216*d30ea906Sjfb8856606 */ 217*d30ea906Sjfb8856606 #define iter_anybus_str "class=eth," 218*d30ea906Sjfb8856606 if (strncmp(devargs_str, iter_anybus_str, 219*d30ea906Sjfb8856606 strlen(iter_anybus_str)) == 0) { 220*d30ea906Sjfb8856606 iter->cls_str = devargs_str + strlen(iter_anybus_str); 221*d30ea906Sjfb8856606 goto end; 222*d30ea906Sjfb8856606 } 223*d30ea906Sjfb8856606 224*d30ea906Sjfb8856606 /* Split bus, device and parameters. */ 225*d30ea906Sjfb8856606 ret = rte_devargs_parse(&devargs, devargs_str); 226*d30ea906Sjfb8856606 if (ret != 0) 227*d30ea906Sjfb8856606 goto error; 228*d30ea906Sjfb8856606 229*d30ea906Sjfb8856606 /* 230*d30ea906Sjfb8856606 * Assume parameters of old syntax can match only at ethdev level. 231*d30ea906Sjfb8856606 * Extra parameters will be ignored, thanks to "+" prefix. 232*d30ea906Sjfb8856606 */ 233*d30ea906Sjfb8856606 str_size = strlen(devargs.args) + 2; 234*d30ea906Sjfb8856606 cls_str = malloc(str_size); 235*d30ea906Sjfb8856606 if (cls_str == NULL) { 236*d30ea906Sjfb8856606 ret = -ENOMEM; 237*d30ea906Sjfb8856606 goto error; 238*d30ea906Sjfb8856606 } 239*d30ea906Sjfb8856606 ret = snprintf(cls_str, str_size, "+%s", devargs.args); 240*d30ea906Sjfb8856606 if (ret != str_size - 1) { 241*d30ea906Sjfb8856606 ret = -EINVAL; 242*d30ea906Sjfb8856606 goto error; 243*d30ea906Sjfb8856606 } 244*d30ea906Sjfb8856606 iter->cls_str = cls_str; 245*d30ea906Sjfb8856606 free(devargs.args); /* allocated by rte_devargs_parse() */ 246*d30ea906Sjfb8856606 devargs.args = NULL; 247*d30ea906Sjfb8856606 248*d30ea906Sjfb8856606 iter->bus = devargs.bus; 249*d30ea906Sjfb8856606 if (iter->bus->dev_iterate == NULL) { 250*d30ea906Sjfb8856606 ret = -ENOTSUP; 251*d30ea906Sjfb8856606 goto error; 252*d30ea906Sjfb8856606 } 253*d30ea906Sjfb8856606 254*d30ea906Sjfb8856606 /* Convert bus args to new syntax for use with new API dev_iterate. */ 255*d30ea906Sjfb8856606 if (strcmp(iter->bus->name, "vdev") == 0) { 256*d30ea906Sjfb8856606 bus_param_key = "name"; 257*d30ea906Sjfb8856606 } else if (strcmp(iter->bus->name, "pci") == 0) { 258*d30ea906Sjfb8856606 bus_param_key = "addr"; 259*d30ea906Sjfb8856606 } else { 260*d30ea906Sjfb8856606 ret = -ENOTSUP; 261*d30ea906Sjfb8856606 goto error; 262*d30ea906Sjfb8856606 } 263*d30ea906Sjfb8856606 str_size = strlen(bus_param_key) + strlen(devargs.name) + 2; 264*d30ea906Sjfb8856606 bus_str = malloc(str_size); 265*d30ea906Sjfb8856606 if (bus_str == NULL) { 266*d30ea906Sjfb8856606 ret = -ENOMEM; 267*d30ea906Sjfb8856606 goto error; 268*d30ea906Sjfb8856606 } 269*d30ea906Sjfb8856606 ret = snprintf(bus_str, str_size, "%s=%s", 270*d30ea906Sjfb8856606 bus_param_key, devargs.name); 271*d30ea906Sjfb8856606 if (ret != str_size - 1) { 272*d30ea906Sjfb8856606 ret = -EINVAL; 273*d30ea906Sjfb8856606 goto error; 274*d30ea906Sjfb8856606 } 275*d30ea906Sjfb8856606 iter->bus_str = bus_str; 276*d30ea906Sjfb8856606 277*d30ea906Sjfb8856606 end: 278*d30ea906Sjfb8856606 iter->cls = rte_class_find_by_name("eth"); 279*d30ea906Sjfb8856606 return 0; 280*d30ea906Sjfb8856606 281*d30ea906Sjfb8856606 error: 282*d30ea906Sjfb8856606 if (ret == -ENOTSUP) 283*d30ea906Sjfb8856606 RTE_LOG(ERR, EAL, "Bus %s does not support iterating.\n", 284*d30ea906Sjfb8856606 iter->bus->name); 285*d30ea906Sjfb8856606 free(devargs.args); 286*d30ea906Sjfb8856606 free(bus_str); 287*d30ea906Sjfb8856606 free(cls_str); 288*d30ea906Sjfb8856606 return ret; 289*d30ea906Sjfb8856606 } 290*d30ea906Sjfb8856606 291*d30ea906Sjfb8856606 uint16_t 292*d30ea906Sjfb8856606 rte_eth_iterator_next(struct rte_dev_iterator *iter) 293*d30ea906Sjfb8856606 { 294*d30ea906Sjfb8856606 if (iter->cls == NULL) /* invalid ethdev iterator */ 295*d30ea906Sjfb8856606 return RTE_MAX_ETHPORTS; 296*d30ea906Sjfb8856606 297*d30ea906Sjfb8856606 do { /* loop to try all matching rte_device */ 298*d30ea906Sjfb8856606 /* If not pure ethdev filter and */ 299*d30ea906Sjfb8856606 if (iter->bus != NULL && 300*d30ea906Sjfb8856606 /* not in middle of rte_eth_dev iteration, */ 301*d30ea906Sjfb8856606 iter->class_device == NULL) { 302*d30ea906Sjfb8856606 /* get next rte_device to try. */ 303*d30ea906Sjfb8856606 iter->device = iter->bus->dev_iterate( 304*d30ea906Sjfb8856606 iter->device, iter->bus_str, iter); 305*d30ea906Sjfb8856606 if (iter->device == NULL) 306*d30ea906Sjfb8856606 break; /* no more rte_device candidate */ 307*d30ea906Sjfb8856606 } 308*d30ea906Sjfb8856606 /* A device is matching bus part, need to check ethdev part. */ 309*d30ea906Sjfb8856606 iter->class_device = iter->cls->dev_iterate( 310*d30ea906Sjfb8856606 iter->class_device, iter->cls_str, iter); 311*d30ea906Sjfb8856606 if (iter->class_device != NULL) 312*d30ea906Sjfb8856606 return eth_dev_to_id(iter->class_device); /* match */ 313*d30ea906Sjfb8856606 } while (iter->bus != NULL); /* need to try next rte_device */ 314*d30ea906Sjfb8856606 315*d30ea906Sjfb8856606 /* No more ethdev port to iterate. */ 316*d30ea906Sjfb8856606 rte_eth_iterator_cleanup(iter); 317*d30ea906Sjfb8856606 return RTE_MAX_ETHPORTS; 318*d30ea906Sjfb8856606 } 319*d30ea906Sjfb8856606 320*d30ea906Sjfb8856606 void 321*d30ea906Sjfb8856606 rte_eth_iterator_cleanup(struct rte_dev_iterator *iter) 322*d30ea906Sjfb8856606 { 323*d30ea906Sjfb8856606 if (iter->bus_str == NULL) 324*d30ea906Sjfb8856606 return; /* nothing to free in pure class filter */ 325*d30ea906Sjfb8856606 free(RTE_CAST_FIELD(iter, bus_str, char *)); /* workaround const */ 326*d30ea906Sjfb8856606 free(RTE_CAST_FIELD(iter, cls_str, char *)); /* workaround const */ 327*d30ea906Sjfb8856606 memset(iter, 0, sizeof(*iter)); 328*d30ea906Sjfb8856606 } 329*d30ea906Sjfb8856606 330*d30ea906Sjfb8856606 uint16_t 331*d30ea906Sjfb8856606 rte_eth_find_next(uint16_t port_id) 332*d30ea906Sjfb8856606 { 333*d30ea906Sjfb8856606 while (port_id < RTE_MAX_ETHPORTS && 334*d30ea906Sjfb8856606 rte_eth_devices[port_id].state != RTE_ETH_DEV_ATTACHED && 335*d30ea906Sjfb8856606 rte_eth_devices[port_id].state != RTE_ETH_DEV_REMOVED) 336*d30ea906Sjfb8856606 port_id++; 337*d30ea906Sjfb8856606 338*d30ea906Sjfb8856606 if (port_id >= RTE_MAX_ETHPORTS) 339*d30ea906Sjfb8856606 return RTE_MAX_ETHPORTS; 340*d30ea906Sjfb8856606 341*d30ea906Sjfb8856606 return port_id; 342*d30ea906Sjfb8856606 } 343*d30ea906Sjfb8856606 344*d30ea906Sjfb8856606 static void 345*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(void) 346*d30ea906Sjfb8856606 { 347*d30ea906Sjfb8856606 const unsigned flags = 0; 348*d30ea906Sjfb8856606 const struct rte_memzone *mz; 349*d30ea906Sjfb8856606 350*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_shared_data_lock); 351*d30ea906Sjfb8856606 352*d30ea906Sjfb8856606 if (rte_eth_dev_shared_data == NULL) { 353*d30ea906Sjfb8856606 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 354*d30ea906Sjfb8856606 /* Allocate port data and ownership shared memory. */ 355*d30ea906Sjfb8856606 mz = rte_memzone_reserve(MZ_RTE_ETH_DEV_DATA, 356*d30ea906Sjfb8856606 sizeof(*rte_eth_dev_shared_data), 357*d30ea906Sjfb8856606 rte_socket_id(), flags); 358*d30ea906Sjfb8856606 } else 359*d30ea906Sjfb8856606 mz = rte_memzone_lookup(MZ_RTE_ETH_DEV_DATA); 360*d30ea906Sjfb8856606 if (mz == NULL) 361*d30ea906Sjfb8856606 rte_panic("Cannot allocate ethdev shared data\n"); 362*d30ea906Sjfb8856606 363*d30ea906Sjfb8856606 rte_eth_dev_shared_data = mz->addr; 364*d30ea906Sjfb8856606 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 365*d30ea906Sjfb8856606 rte_eth_dev_shared_data->next_owner_id = 366*d30ea906Sjfb8856606 RTE_ETH_DEV_NO_OWNER + 1; 367*d30ea906Sjfb8856606 rte_spinlock_init(&rte_eth_dev_shared_data->ownership_lock); 368*d30ea906Sjfb8856606 memset(rte_eth_dev_shared_data->data, 0, 369*d30ea906Sjfb8856606 sizeof(rte_eth_dev_shared_data->data)); 370*d30ea906Sjfb8856606 } 371*d30ea906Sjfb8856606 } 372*d30ea906Sjfb8856606 373*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_shared_data_lock); 374*d30ea906Sjfb8856606 } 375*d30ea906Sjfb8856606 376*d30ea906Sjfb8856606 static bool 377*d30ea906Sjfb8856606 is_allocated(const struct rte_eth_dev *ethdev) 378*d30ea906Sjfb8856606 { 379*d30ea906Sjfb8856606 return ethdev->data->name[0] != '\0'; 380*d30ea906Sjfb8856606 } 381*d30ea906Sjfb8856606 382*d30ea906Sjfb8856606 static struct rte_eth_dev * 383*d30ea906Sjfb8856606 _rte_eth_dev_allocated(const char *name) 384*d30ea906Sjfb8856606 { 385*d30ea906Sjfb8856606 unsigned i; 386*d30ea906Sjfb8856606 387*d30ea906Sjfb8856606 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 388*d30ea906Sjfb8856606 if (rte_eth_devices[i].data != NULL && 389*d30ea906Sjfb8856606 strcmp(rte_eth_devices[i].data->name, name) == 0) 390*d30ea906Sjfb8856606 return &rte_eth_devices[i]; 391*d30ea906Sjfb8856606 } 392*d30ea906Sjfb8856606 return NULL; 393*d30ea906Sjfb8856606 } 394*d30ea906Sjfb8856606 395*d30ea906Sjfb8856606 struct rte_eth_dev * 396*d30ea906Sjfb8856606 rte_eth_dev_allocated(const char *name) 397*d30ea906Sjfb8856606 { 398*d30ea906Sjfb8856606 struct rte_eth_dev *ethdev; 399*d30ea906Sjfb8856606 400*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 401*d30ea906Sjfb8856606 402*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 403*d30ea906Sjfb8856606 404*d30ea906Sjfb8856606 ethdev = _rte_eth_dev_allocated(name); 405*d30ea906Sjfb8856606 406*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 407*d30ea906Sjfb8856606 408*d30ea906Sjfb8856606 return ethdev; 409*d30ea906Sjfb8856606 } 410*d30ea906Sjfb8856606 411*d30ea906Sjfb8856606 static uint16_t 412*d30ea906Sjfb8856606 rte_eth_dev_find_free_port(void) 413*d30ea906Sjfb8856606 { 414*d30ea906Sjfb8856606 unsigned i; 415*d30ea906Sjfb8856606 416*d30ea906Sjfb8856606 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 417*d30ea906Sjfb8856606 /* Using shared name field to find a free port. */ 418*d30ea906Sjfb8856606 if (rte_eth_dev_shared_data->data[i].name[0] == '\0') { 419*d30ea906Sjfb8856606 RTE_ASSERT(rte_eth_devices[i].state == 420*d30ea906Sjfb8856606 RTE_ETH_DEV_UNUSED); 421*d30ea906Sjfb8856606 return i; 422*d30ea906Sjfb8856606 } 423*d30ea906Sjfb8856606 } 424*d30ea906Sjfb8856606 return RTE_MAX_ETHPORTS; 425*d30ea906Sjfb8856606 } 426*d30ea906Sjfb8856606 427*d30ea906Sjfb8856606 static struct rte_eth_dev * 428*d30ea906Sjfb8856606 eth_dev_get(uint16_t port_id) 429*d30ea906Sjfb8856606 { 430*d30ea906Sjfb8856606 struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id]; 431*d30ea906Sjfb8856606 432*d30ea906Sjfb8856606 eth_dev->data = &rte_eth_dev_shared_data->data[port_id]; 433*d30ea906Sjfb8856606 434*d30ea906Sjfb8856606 eth_dev_last_created_port = port_id; 435*d30ea906Sjfb8856606 436*d30ea906Sjfb8856606 return eth_dev; 437*d30ea906Sjfb8856606 } 438*d30ea906Sjfb8856606 439*d30ea906Sjfb8856606 struct rte_eth_dev * 440*d30ea906Sjfb8856606 rte_eth_dev_allocate(const char *name) 441*d30ea906Sjfb8856606 { 442*d30ea906Sjfb8856606 uint16_t port_id; 443*d30ea906Sjfb8856606 struct rte_eth_dev *eth_dev = NULL; 444*d30ea906Sjfb8856606 445*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 446*d30ea906Sjfb8856606 447*d30ea906Sjfb8856606 /* Synchronize port creation between primary and secondary threads. */ 448*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 449*d30ea906Sjfb8856606 450*d30ea906Sjfb8856606 if (_rte_eth_dev_allocated(name) != NULL) { 451*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 452*d30ea906Sjfb8856606 "Ethernet device with name %s already allocated\n", 453*d30ea906Sjfb8856606 name); 454*d30ea906Sjfb8856606 goto unlock; 455*d30ea906Sjfb8856606 } 456*d30ea906Sjfb8856606 457*d30ea906Sjfb8856606 port_id = rte_eth_dev_find_free_port(); 458*d30ea906Sjfb8856606 if (port_id == RTE_MAX_ETHPORTS) { 459*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 460*d30ea906Sjfb8856606 "Reached maximum number of Ethernet ports\n"); 461*d30ea906Sjfb8856606 goto unlock; 462*d30ea906Sjfb8856606 } 463*d30ea906Sjfb8856606 464*d30ea906Sjfb8856606 eth_dev = eth_dev_get(port_id); 465*d30ea906Sjfb8856606 snprintf(eth_dev->data->name, sizeof(eth_dev->data->name), "%s", name); 466*d30ea906Sjfb8856606 eth_dev->data->port_id = port_id; 467*d30ea906Sjfb8856606 eth_dev->data->mtu = ETHER_MTU; 468*d30ea906Sjfb8856606 469*d30ea906Sjfb8856606 unlock: 470*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 471*d30ea906Sjfb8856606 472*d30ea906Sjfb8856606 return eth_dev; 473*d30ea906Sjfb8856606 } 474*d30ea906Sjfb8856606 475*d30ea906Sjfb8856606 /* 476*d30ea906Sjfb8856606 * Attach to a port already registered by the primary process, which 477*d30ea906Sjfb8856606 * makes sure that the same device would have the same port id both 478*d30ea906Sjfb8856606 * in the primary and secondary process. 479*d30ea906Sjfb8856606 */ 480*d30ea906Sjfb8856606 struct rte_eth_dev * 481*d30ea906Sjfb8856606 rte_eth_dev_attach_secondary(const char *name) 482*d30ea906Sjfb8856606 { 483*d30ea906Sjfb8856606 uint16_t i; 484*d30ea906Sjfb8856606 struct rte_eth_dev *eth_dev = NULL; 485*d30ea906Sjfb8856606 486*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 487*d30ea906Sjfb8856606 488*d30ea906Sjfb8856606 /* Synchronize port attachment to primary port creation and release. */ 489*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 490*d30ea906Sjfb8856606 491*d30ea906Sjfb8856606 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 492*d30ea906Sjfb8856606 if (strcmp(rte_eth_dev_shared_data->data[i].name, name) == 0) 493*d30ea906Sjfb8856606 break; 494*d30ea906Sjfb8856606 } 495*d30ea906Sjfb8856606 if (i == RTE_MAX_ETHPORTS) { 496*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 497*d30ea906Sjfb8856606 "Device %s is not driven by the primary process\n", 498*d30ea906Sjfb8856606 name); 499*d30ea906Sjfb8856606 } else { 500*d30ea906Sjfb8856606 eth_dev = eth_dev_get(i); 501*d30ea906Sjfb8856606 RTE_ASSERT(eth_dev->data->port_id == i); 502*d30ea906Sjfb8856606 } 503*d30ea906Sjfb8856606 504*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 505*d30ea906Sjfb8856606 return eth_dev; 506*d30ea906Sjfb8856606 } 507*d30ea906Sjfb8856606 508*d30ea906Sjfb8856606 int 509*d30ea906Sjfb8856606 rte_eth_dev_release_port(struct rte_eth_dev *eth_dev) 510*d30ea906Sjfb8856606 { 511*d30ea906Sjfb8856606 if (eth_dev == NULL) 512*d30ea906Sjfb8856606 return -EINVAL; 513*d30ea906Sjfb8856606 514*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 515*d30ea906Sjfb8856606 516*d30ea906Sjfb8856606 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 517*d30ea906Sjfb8856606 _rte_eth_dev_callback_process(eth_dev, 518*d30ea906Sjfb8856606 RTE_ETH_EVENT_DESTROY, NULL); 519*d30ea906Sjfb8856606 520*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 521*d30ea906Sjfb8856606 522*d30ea906Sjfb8856606 eth_dev->state = RTE_ETH_DEV_UNUSED; 523*d30ea906Sjfb8856606 524*d30ea906Sjfb8856606 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 525*d30ea906Sjfb8856606 rte_free(eth_dev->data->rx_queues); 526*d30ea906Sjfb8856606 rte_free(eth_dev->data->tx_queues); 527*d30ea906Sjfb8856606 rte_free(eth_dev->data->mac_addrs); 528*d30ea906Sjfb8856606 rte_free(eth_dev->data->hash_mac_addrs); 529*d30ea906Sjfb8856606 rte_free(eth_dev->data->dev_private); 530*d30ea906Sjfb8856606 memset(eth_dev->data, 0, sizeof(struct rte_eth_dev_data)); 531*d30ea906Sjfb8856606 } 532*d30ea906Sjfb8856606 533*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 534*d30ea906Sjfb8856606 535*d30ea906Sjfb8856606 return 0; 536*d30ea906Sjfb8856606 } 537*d30ea906Sjfb8856606 538*d30ea906Sjfb8856606 int 539*d30ea906Sjfb8856606 rte_eth_dev_is_valid_port(uint16_t port_id) 540*d30ea906Sjfb8856606 { 541*d30ea906Sjfb8856606 if (port_id >= RTE_MAX_ETHPORTS || 542*d30ea906Sjfb8856606 (rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED)) 543*d30ea906Sjfb8856606 return 0; 544*d30ea906Sjfb8856606 else 545*d30ea906Sjfb8856606 return 1; 546*d30ea906Sjfb8856606 } 547*d30ea906Sjfb8856606 548*d30ea906Sjfb8856606 static int 549*d30ea906Sjfb8856606 rte_eth_is_valid_owner_id(uint64_t owner_id) 550*d30ea906Sjfb8856606 { 551*d30ea906Sjfb8856606 if (owner_id == RTE_ETH_DEV_NO_OWNER || 552*d30ea906Sjfb8856606 rte_eth_dev_shared_data->next_owner_id <= owner_id) 553*d30ea906Sjfb8856606 return 0; 554*d30ea906Sjfb8856606 return 1; 555*d30ea906Sjfb8856606 } 556*d30ea906Sjfb8856606 557*d30ea906Sjfb8856606 uint64_t 558*d30ea906Sjfb8856606 rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id) 559*d30ea906Sjfb8856606 { 560*d30ea906Sjfb8856606 while (port_id < RTE_MAX_ETHPORTS && 561*d30ea906Sjfb8856606 ((rte_eth_devices[port_id].state != RTE_ETH_DEV_ATTACHED && 562*d30ea906Sjfb8856606 rte_eth_devices[port_id].state != RTE_ETH_DEV_REMOVED) || 563*d30ea906Sjfb8856606 rte_eth_devices[port_id].data->owner.id != owner_id)) 564*d30ea906Sjfb8856606 port_id++; 565*d30ea906Sjfb8856606 566*d30ea906Sjfb8856606 if (port_id >= RTE_MAX_ETHPORTS) 567*d30ea906Sjfb8856606 return RTE_MAX_ETHPORTS; 568*d30ea906Sjfb8856606 569*d30ea906Sjfb8856606 return port_id; 570*d30ea906Sjfb8856606 } 571*d30ea906Sjfb8856606 572*d30ea906Sjfb8856606 int __rte_experimental 573*d30ea906Sjfb8856606 rte_eth_dev_owner_new(uint64_t *owner_id) 574*d30ea906Sjfb8856606 { 575*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 576*d30ea906Sjfb8856606 577*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 578*d30ea906Sjfb8856606 579*d30ea906Sjfb8856606 *owner_id = rte_eth_dev_shared_data->next_owner_id++; 580*d30ea906Sjfb8856606 581*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 582*d30ea906Sjfb8856606 return 0; 583*d30ea906Sjfb8856606 } 584*d30ea906Sjfb8856606 585*d30ea906Sjfb8856606 static int 586*d30ea906Sjfb8856606 _rte_eth_dev_owner_set(const uint16_t port_id, const uint64_t old_owner_id, 587*d30ea906Sjfb8856606 const struct rte_eth_dev_owner *new_owner) 588*d30ea906Sjfb8856606 { 589*d30ea906Sjfb8856606 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id]; 590*d30ea906Sjfb8856606 struct rte_eth_dev_owner *port_owner; 591*d30ea906Sjfb8856606 int sret; 592*d30ea906Sjfb8856606 593*d30ea906Sjfb8856606 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) { 594*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n", 595*d30ea906Sjfb8856606 port_id); 596*d30ea906Sjfb8856606 return -ENODEV; 597*d30ea906Sjfb8856606 } 598*d30ea906Sjfb8856606 599*d30ea906Sjfb8856606 if (!rte_eth_is_valid_owner_id(new_owner->id) && 600*d30ea906Sjfb8856606 !rte_eth_is_valid_owner_id(old_owner_id)) { 601*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 602*d30ea906Sjfb8856606 "Invalid owner old_id=%016"PRIx64" new_id=%016"PRIx64"\n", 603*d30ea906Sjfb8856606 old_owner_id, new_owner->id); 604*d30ea906Sjfb8856606 return -EINVAL; 605*d30ea906Sjfb8856606 } 606*d30ea906Sjfb8856606 607*d30ea906Sjfb8856606 port_owner = &rte_eth_devices[port_id].data->owner; 608*d30ea906Sjfb8856606 if (port_owner->id != old_owner_id) { 609*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 610*d30ea906Sjfb8856606 "Cannot set owner to port %u already owned by %s_%016"PRIX64"\n", 611*d30ea906Sjfb8856606 port_id, port_owner->name, port_owner->id); 612*d30ea906Sjfb8856606 return -EPERM; 613*d30ea906Sjfb8856606 } 614*d30ea906Sjfb8856606 615*d30ea906Sjfb8856606 sret = snprintf(port_owner->name, RTE_ETH_MAX_OWNER_NAME_LEN, "%s", 616*d30ea906Sjfb8856606 new_owner->name); 617*d30ea906Sjfb8856606 if (sret < 0 || sret >= RTE_ETH_MAX_OWNER_NAME_LEN) 618*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port %u owner name was truncated\n", 619*d30ea906Sjfb8856606 port_id); 620*d30ea906Sjfb8856606 621*d30ea906Sjfb8856606 port_owner->id = new_owner->id; 622*d30ea906Sjfb8856606 623*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(DEBUG, "Port %u owner is %s_%016"PRIx64"\n", 624*d30ea906Sjfb8856606 port_id, new_owner->name, new_owner->id); 625*d30ea906Sjfb8856606 626*d30ea906Sjfb8856606 return 0; 627*d30ea906Sjfb8856606 } 628*d30ea906Sjfb8856606 629*d30ea906Sjfb8856606 int __rte_experimental 630*d30ea906Sjfb8856606 rte_eth_dev_owner_set(const uint16_t port_id, 631*d30ea906Sjfb8856606 const struct rte_eth_dev_owner *owner) 632*d30ea906Sjfb8856606 { 633*d30ea906Sjfb8856606 int ret; 634*d30ea906Sjfb8856606 635*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 636*d30ea906Sjfb8856606 637*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 638*d30ea906Sjfb8856606 639*d30ea906Sjfb8856606 ret = _rte_eth_dev_owner_set(port_id, RTE_ETH_DEV_NO_OWNER, owner); 640*d30ea906Sjfb8856606 641*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 642*d30ea906Sjfb8856606 return ret; 643*d30ea906Sjfb8856606 } 644*d30ea906Sjfb8856606 645*d30ea906Sjfb8856606 int __rte_experimental 646*d30ea906Sjfb8856606 rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id) 647*d30ea906Sjfb8856606 { 648*d30ea906Sjfb8856606 const struct rte_eth_dev_owner new_owner = (struct rte_eth_dev_owner) 649*d30ea906Sjfb8856606 {.id = RTE_ETH_DEV_NO_OWNER, .name = ""}; 650*d30ea906Sjfb8856606 int ret; 651*d30ea906Sjfb8856606 652*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 653*d30ea906Sjfb8856606 654*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 655*d30ea906Sjfb8856606 656*d30ea906Sjfb8856606 ret = _rte_eth_dev_owner_set(port_id, owner_id, &new_owner); 657*d30ea906Sjfb8856606 658*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 659*d30ea906Sjfb8856606 return ret; 660*d30ea906Sjfb8856606 } 661*d30ea906Sjfb8856606 662*d30ea906Sjfb8856606 void __rte_experimental 663*d30ea906Sjfb8856606 rte_eth_dev_owner_delete(const uint64_t owner_id) 664*d30ea906Sjfb8856606 { 665*d30ea906Sjfb8856606 uint16_t port_id; 666*d30ea906Sjfb8856606 667*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 668*d30ea906Sjfb8856606 669*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 670*d30ea906Sjfb8856606 671*d30ea906Sjfb8856606 if (rte_eth_is_valid_owner_id(owner_id)) { 672*d30ea906Sjfb8856606 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) 673*d30ea906Sjfb8856606 if (rte_eth_devices[port_id].data->owner.id == owner_id) 674*d30ea906Sjfb8856606 memset(&rte_eth_devices[port_id].data->owner, 0, 675*d30ea906Sjfb8856606 sizeof(struct rte_eth_dev_owner)); 676*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(NOTICE, 677*d30ea906Sjfb8856606 "All port owners owned by %016"PRIx64" identifier have removed\n", 678*d30ea906Sjfb8856606 owner_id); 679*d30ea906Sjfb8856606 } else { 680*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 681*d30ea906Sjfb8856606 "Invalid owner id=%016"PRIx64"\n", 682*d30ea906Sjfb8856606 owner_id); 683*d30ea906Sjfb8856606 } 684*d30ea906Sjfb8856606 685*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 686*d30ea906Sjfb8856606 } 687*d30ea906Sjfb8856606 688*d30ea906Sjfb8856606 int __rte_experimental 689*d30ea906Sjfb8856606 rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner) 690*d30ea906Sjfb8856606 { 691*d30ea906Sjfb8856606 int ret = 0; 692*d30ea906Sjfb8856606 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id]; 693*d30ea906Sjfb8856606 694*d30ea906Sjfb8856606 rte_eth_dev_shared_data_prepare(); 695*d30ea906Sjfb8856606 696*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock); 697*d30ea906Sjfb8856606 698*d30ea906Sjfb8856606 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) { 699*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n", 700*d30ea906Sjfb8856606 port_id); 701*d30ea906Sjfb8856606 ret = -ENODEV; 702*d30ea906Sjfb8856606 } else { 703*d30ea906Sjfb8856606 rte_memcpy(owner, ðdev->data->owner, sizeof(*owner)); 704*d30ea906Sjfb8856606 } 705*d30ea906Sjfb8856606 706*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock); 707*d30ea906Sjfb8856606 return ret; 708*d30ea906Sjfb8856606 } 709*d30ea906Sjfb8856606 710*d30ea906Sjfb8856606 int 711*d30ea906Sjfb8856606 rte_eth_dev_socket_id(uint16_t port_id) 712*d30ea906Sjfb8856606 { 713*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1); 714*d30ea906Sjfb8856606 return rte_eth_devices[port_id].data->numa_node; 715*d30ea906Sjfb8856606 } 716*d30ea906Sjfb8856606 717*d30ea906Sjfb8856606 void * 718*d30ea906Sjfb8856606 rte_eth_dev_get_sec_ctx(uint16_t port_id) 719*d30ea906Sjfb8856606 { 720*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL); 721*d30ea906Sjfb8856606 return rte_eth_devices[port_id].security_ctx; 722*d30ea906Sjfb8856606 } 723*d30ea906Sjfb8856606 724*d30ea906Sjfb8856606 uint16_t 725*d30ea906Sjfb8856606 rte_eth_dev_count(void) 726*d30ea906Sjfb8856606 { 727*d30ea906Sjfb8856606 return rte_eth_dev_count_avail(); 728*d30ea906Sjfb8856606 } 729*d30ea906Sjfb8856606 730*d30ea906Sjfb8856606 uint16_t 731*d30ea906Sjfb8856606 rte_eth_dev_count_avail(void) 732*d30ea906Sjfb8856606 { 733*d30ea906Sjfb8856606 uint16_t p; 734*d30ea906Sjfb8856606 uint16_t count; 735*d30ea906Sjfb8856606 736*d30ea906Sjfb8856606 count = 0; 737*d30ea906Sjfb8856606 738*d30ea906Sjfb8856606 RTE_ETH_FOREACH_DEV(p) 739*d30ea906Sjfb8856606 count++; 740*d30ea906Sjfb8856606 741*d30ea906Sjfb8856606 return count; 742*d30ea906Sjfb8856606 } 743*d30ea906Sjfb8856606 744*d30ea906Sjfb8856606 uint16_t __rte_experimental 745*d30ea906Sjfb8856606 rte_eth_dev_count_total(void) 746*d30ea906Sjfb8856606 { 747*d30ea906Sjfb8856606 uint16_t port, count = 0; 748*d30ea906Sjfb8856606 749*d30ea906Sjfb8856606 for (port = 0; port < RTE_MAX_ETHPORTS; port++) 750*d30ea906Sjfb8856606 if (rte_eth_devices[port].state != RTE_ETH_DEV_UNUSED) 751*d30ea906Sjfb8856606 count++; 752*d30ea906Sjfb8856606 753*d30ea906Sjfb8856606 return count; 754*d30ea906Sjfb8856606 } 755*d30ea906Sjfb8856606 756*d30ea906Sjfb8856606 int 757*d30ea906Sjfb8856606 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name) 758*d30ea906Sjfb8856606 { 759*d30ea906Sjfb8856606 char *tmp; 760*d30ea906Sjfb8856606 761*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 762*d30ea906Sjfb8856606 763*d30ea906Sjfb8856606 if (name == NULL) { 764*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n"); 765*d30ea906Sjfb8856606 return -EINVAL; 766*d30ea906Sjfb8856606 } 767*d30ea906Sjfb8856606 768*d30ea906Sjfb8856606 /* shouldn't check 'rte_eth_devices[i].data', 769*d30ea906Sjfb8856606 * because it might be overwritten by VDEV PMD */ 770*d30ea906Sjfb8856606 tmp = rte_eth_dev_shared_data->data[port_id].name; 771*d30ea906Sjfb8856606 strcpy(name, tmp); 772*d30ea906Sjfb8856606 return 0; 773*d30ea906Sjfb8856606 } 774*d30ea906Sjfb8856606 775*d30ea906Sjfb8856606 int 776*d30ea906Sjfb8856606 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id) 777*d30ea906Sjfb8856606 { 778*d30ea906Sjfb8856606 uint32_t pid; 779*d30ea906Sjfb8856606 780*d30ea906Sjfb8856606 if (name == NULL) { 781*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n"); 782*d30ea906Sjfb8856606 return -EINVAL; 783*d30ea906Sjfb8856606 } 784*d30ea906Sjfb8856606 785*d30ea906Sjfb8856606 for (pid = 0; pid < RTE_MAX_ETHPORTS; pid++) { 786*d30ea906Sjfb8856606 if (rte_eth_devices[pid].state != RTE_ETH_DEV_UNUSED && 787*d30ea906Sjfb8856606 !strcmp(name, rte_eth_dev_shared_data->data[pid].name)) { 788*d30ea906Sjfb8856606 *port_id = pid; 789*d30ea906Sjfb8856606 return 0; 790*d30ea906Sjfb8856606 } 791*d30ea906Sjfb8856606 } 792*d30ea906Sjfb8856606 793*d30ea906Sjfb8856606 return -ENODEV; 794*d30ea906Sjfb8856606 } 795*d30ea906Sjfb8856606 796*d30ea906Sjfb8856606 static int 797*d30ea906Sjfb8856606 eth_err(uint16_t port_id, int ret) 798*d30ea906Sjfb8856606 { 799*d30ea906Sjfb8856606 if (ret == 0) 800*d30ea906Sjfb8856606 return 0; 801*d30ea906Sjfb8856606 if (rte_eth_dev_is_removed(port_id)) 802*d30ea906Sjfb8856606 return -EIO; 803*d30ea906Sjfb8856606 return ret; 804*d30ea906Sjfb8856606 } 805*d30ea906Sjfb8856606 806*d30ea906Sjfb8856606 static int 807*d30ea906Sjfb8856606 rte_eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues) 808*d30ea906Sjfb8856606 { 809*d30ea906Sjfb8856606 uint16_t old_nb_queues = dev->data->nb_rx_queues; 810*d30ea906Sjfb8856606 void **rxq; 811*d30ea906Sjfb8856606 unsigned i; 812*d30ea906Sjfb8856606 813*d30ea906Sjfb8856606 if (dev->data->rx_queues == NULL && nb_queues != 0) { /* first time configuration */ 814*d30ea906Sjfb8856606 dev->data->rx_queues = rte_zmalloc("ethdev->rx_queues", 815*d30ea906Sjfb8856606 sizeof(dev->data->rx_queues[0]) * nb_queues, 816*d30ea906Sjfb8856606 RTE_CACHE_LINE_SIZE); 817*d30ea906Sjfb8856606 if (dev->data->rx_queues == NULL) { 818*d30ea906Sjfb8856606 dev->data->nb_rx_queues = 0; 819*d30ea906Sjfb8856606 return -(ENOMEM); 820*d30ea906Sjfb8856606 } 821*d30ea906Sjfb8856606 } else if (dev->data->rx_queues != NULL && nb_queues != 0) { /* re-configure */ 822*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP); 823*d30ea906Sjfb8856606 824*d30ea906Sjfb8856606 rxq = dev->data->rx_queues; 825*d30ea906Sjfb8856606 826*d30ea906Sjfb8856606 for (i = nb_queues; i < old_nb_queues; i++) 827*d30ea906Sjfb8856606 (*dev->dev_ops->rx_queue_release)(rxq[i]); 828*d30ea906Sjfb8856606 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues, 829*d30ea906Sjfb8856606 RTE_CACHE_LINE_SIZE); 830*d30ea906Sjfb8856606 if (rxq == NULL) 831*d30ea906Sjfb8856606 return -(ENOMEM); 832*d30ea906Sjfb8856606 if (nb_queues > old_nb_queues) { 833*d30ea906Sjfb8856606 uint16_t new_qs = nb_queues - old_nb_queues; 834*d30ea906Sjfb8856606 835*d30ea906Sjfb8856606 memset(rxq + old_nb_queues, 0, 836*d30ea906Sjfb8856606 sizeof(rxq[0]) * new_qs); 837*d30ea906Sjfb8856606 } 838*d30ea906Sjfb8856606 839*d30ea906Sjfb8856606 dev->data->rx_queues = rxq; 840*d30ea906Sjfb8856606 841*d30ea906Sjfb8856606 } else if (dev->data->rx_queues != NULL && nb_queues == 0) { 842*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP); 843*d30ea906Sjfb8856606 844*d30ea906Sjfb8856606 rxq = dev->data->rx_queues; 845*d30ea906Sjfb8856606 846*d30ea906Sjfb8856606 for (i = nb_queues; i < old_nb_queues; i++) 847*d30ea906Sjfb8856606 (*dev->dev_ops->rx_queue_release)(rxq[i]); 848*d30ea906Sjfb8856606 849*d30ea906Sjfb8856606 rte_free(dev->data->rx_queues); 850*d30ea906Sjfb8856606 dev->data->rx_queues = NULL; 851*d30ea906Sjfb8856606 } 852*d30ea906Sjfb8856606 dev->data->nb_rx_queues = nb_queues; 853*d30ea906Sjfb8856606 return 0; 854*d30ea906Sjfb8856606 } 855*d30ea906Sjfb8856606 856*d30ea906Sjfb8856606 int 857*d30ea906Sjfb8856606 rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id) 858*d30ea906Sjfb8856606 { 859*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 860*d30ea906Sjfb8856606 861*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 862*d30ea906Sjfb8856606 863*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 864*d30ea906Sjfb8856606 if (!dev->data->dev_started) { 865*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 866*d30ea906Sjfb8856606 "Port %u must be started before start any queue\n", 867*d30ea906Sjfb8856606 port_id); 868*d30ea906Sjfb8856606 return -EINVAL; 869*d30ea906Sjfb8856606 } 870*d30ea906Sjfb8856606 871*d30ea906Sjfb8856606 if (rx_queue_id >= dev->data->nb_rx_queues) { 872*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 873*d30ea906Sjfb8856606 return -EINVAL; 874*d30ea906Sjfb8856606 } 875*d30ea906Sjfb8856606 876*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP); 877*d30ea906Sjfb8856606 878*d30ea906Sjfb8856606 if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) { 879*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(INFO, 880*d30ea906Sjfb8856606 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n", 881*d30ea906Sjfb8856606 rx_queue_id, port_id); 882*d30ea906Sjfb8856606 return 0; 883*d30ea906Sjfb8856606 } 884*d30ea906Sjfb8856606 885*d30ea906Sjfb8856606 return eth_err(port_id, dev->dev_ops->rx_queue_start(dev, 886*d30ea906Sjfb8856606 rx_queue_id)); 887*d30ea906Sjfb8856606 888*d30ea906Sjfb8856606 } 889*d30ea906Sjfb8856606 890*d30ea906Sjfb8856606 int 891*d30ea906Sjfb8856606 rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id) 892*d30ea906Sjfb8856606 { 893*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 894*d30ea906Sjfb8856606 895*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 896*d30ea906Sjfb8856606 897*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 898*d30ea906Sjfb8856606 if (rx_queue_id >= dev->data->nb_rx_queues) { 899*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 900*d30ea906Sjfb8856606 return -EINVAL; 901*d30ea906Sjfb8856606 } 902*d30ea906Sjfb8856606 903*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP); 904*d30ea906Sjfb8856606 905*d30ea906Sjfb8856606 if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) { 906*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(INFO, 907*d30ea906Sjfb8856606 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n", 908*d30ea906Sjfb8856606 rx_queue_id, port_id); 909*d30ea906Sjfb8856606 return 0; 910*d30ea906Sjfb8856606 } 911*d30ea906Sjfb8856606 912*d30ea906Sjfb8856606 return eth_err(port_id, dev->dev_ops->rx_queue_stop(dev, rx_queue_id)); 913*d30ea906Sjfb8856606 914*d30ea906Sjfb8856606 } 915*d30ea906Sjfb8856606 916*d30ea906Sjfb8856606 int 917*d30ea906Sjfb8856606 rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id) 918*d30ea906Sjfb8856606 { 919*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 920*d30ea906Sjfb8856606 921*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 922*d30ea906Sjfb8856606 923*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 924*d30ea906Sjfb8856606 if (!dev->data->dev_started) { 925*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 926*d30ea906Sjfb8856606 "Port %u must be started before start any queue\n", 927*d30ea906Sjfb8856606 port_id); 928*d30ea906Sjfb8856606 return -EINVAL; 929*d30ea906Sjfb8856606 } 930*d30ea906Sjfb8856606 931*d30ea906Sjfb8856606 if (tx_queue_id >= dev->data->nb_tx_queues) { 932*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 933*d30ea906Sjfb8856606 return -EINVAL; 934*d30ea906Sjfb8856606 } 935*d30ea906Sjfb8856606 936*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP); 937*d30ea906Sjfb8856606 938*d30ea906Sjfb8856606 if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) { 939*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(INFO, 940*d30ea906Sjfb8856606 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n", 941*d30ea906Sjfb8856606 tx_queue_id, port_id); 942*d30ea906Sjfb8856606 return 0; 943*d30ea906Sjfb8856606 } 944*d30ea906Sjfb8856606 945*d30ea906Sjfb8856606 return eth_err(port_id, dev->dev_ops->tx_queue_start(dev, tx_queue_id)); 946*d30ea906Sjfb8856606 } 947*d30ea906Sjfb8856606 948*d30ea906Sjfb8856606 int 949*d30ea906Sjfb8856606 rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id) 950*d30ea906Sjfb8856606 { 951*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 952*d30ea906Sjfb8856606 953*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 954*d30ea906Sjfb8856606 955*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 956*d30ea906Sjfb8856606 if (tx_queue_id >= dev->data->nb_tx_queues) { 957*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 958*d30ea906Sjfb8856606 return -EINVAL; 959*d30ea906Sjfb8856606 } 960*d30ea906Sjfb8856606 961*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP); 962*d30ea906Sjfb8856606 963*d30ea906Sjfb8856606 if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) { 964*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(INFO, 965*d30ea906Sjfb8856606 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n", 966*d30ea906Sjfb8856606 tx_queue_id, port_id); 967*d30ea906Sjfb8856606 return 0; 968*d30ea906Sjfb8856606 } 969*d30ea906Sjfb8856606 970*d30ea906Sjfb8856606 return eth_err(port_id, dev->dev_ops->tx_queue_stop(dev, tx_queue_id)); 971*d30ea906Sjfb8856606 972*d30ea906Sjfb8856606 } 973*d30ea906Sjfb8856606 974*d30ea906Sjfb8856606 static int 975*d30ea906Sjfb8856606 rte_eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues) 976*d30ea906Sjfb8856606 { 977*d30ea906Sjfb8856606 uint16_t old_nb_queues = dev->data->nb_tx_queues; 978*d30ea906Sjfb8856606 void **txq; 979*d30ea906Sjfb8856606 unsigned i; 980*d30ea906Sjfb8856606 981*d30ea906Sjfb8856606 if (dev->data->tx_queues == NULL && nb_queues != 0) { /* first time configuration */ 982*d30ea906Sjfb8856606 dev->data->tx_queues = rte_zmalloc("ethdev->tx_queues", 983*d30ea906Sjfb8856606 sizeof(dev->data->tx_queues[0]) * nb_queues, 984*d30ea906Sjfb8856606 RTE_CACHE_LINE_SIZE); 985*d30ea906Sjfb8856606 if (dev->data->tx_queues == NULL) { 986*d30ea906Sjfb8856606 dev->data->nb_tx_queues = 0; 987*d30ea906Sjfb8856606 return -(ENOMEM); 988*d30ea906Sjfb8856606 } 989*d30ea906Sjfb8856606 } else if (dev->data->tx_queues != NULL && nb_queues != 0) { /* re-configure */ 990*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP); 991*d30ea906Sjfb8856606 992*d30ea906Sjfb8856606 txq = dev->data->tx_queues; 993*d30ea906Sjfb8856606 994*d30ea906Sjfb8856606 for (i = nb_queues; i < old_nb_queues; i++) 995*d30ea906Sjfb8856606 (*dev->dev_ops->tx_queue_release)(txq[i]); 996*d30ea906Sjfb8856606 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues, 997*d30ea906Sjfb8856606 RTE_CACHE_LINE_SIZE); 998*d30ea906Sjfb8856606 if (txq == NULL) 999*d30ea906Sjfb8856606 return -ENOMEM; 1000*d30ea906Sjfb8856606 if (nb_queues > old_nb_queues) { 1001*d30ea906Sjfb8856606 uint16_t new_qs = nb_queues - old_nb_queues; 1002*d30ea906Sjfb8856606 1003*d30ea906Sjfb8856606 memset(txq + old_nb_queues, 0, 1004*d30ea906Sjfb8856606 sizeof(txq[0]) * new_qs); 1005*d30ea906Sjfb8856606 } 1006*d30ea906Sjfb8856606 1007*d30ea906Sjfb8856606 dev->data->tx_queues = txq; 1008*d30ea906Sjfb8856606 1009*d30ea906Sjfb8856606 } else if (dev->data->tx_queues != NULL && nb_queues == 0) { 1010*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP); 1011*d30ea906Sjfb8856606 1012*d30ea906Sjfb8856606 txq = dev->data->tx_queues; 1013*d30ea906Sjfb8856606 1014*d30ea906Sjfb8856606 for (i = nb_queues; i < old_nb_queues; i++) 1015*d30ea906Sjfb8856606 (*dev->dev_ops->tx_queue_release)(txq[i]); 1016*d30ea906Sjfb8856606 1017*d30ea906Sjfb8856606 rte_free(dev->data->tx_queues); 1018*d30ea906Sjfb8856606 dev->data->tx_queues = NULL; 1019*d30ea906Sjfb8856606 } 1020*d30ea906Sjfb8856606 dev->data->nb_tx_queues = nb_queues; 1021*d30ea906Sjfb8856606 return 0; 1022*d30ea906Sjfb8856606 } 1023*d30ea906Sjfb8856606 1024*d30ea906Sjfb8856606 uint32_t 1025*d30ea906Sjfb8856606 rte_eth_speed_bitflag(uint32_t speed, int duplex) 1026*d30ea906Sjfb8856606 { 1027*d30ea906Sjfb8856606 switch (speed) { 1028*d30ea906Sjfb8856606 case ETH_SPEED_NUM_10M: 1029*d30ea906Sjfb8856606 return duplex ? ETH_LINK_SPEED_10M : ETH_LINK_SPEED_10M_HD; 1030*d30ea906Sjfb8856606 case ETH_SPEED_NUM_100M: 1031*d30ea906Sjfb8856606 return duplex ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_100M_HD; 1032*d30ea906Sjfb8856606 case ETH_SPEED_NUM_1G: 1033*d30ea906Sjfb8856606 return ETH_LINK_SPEED_1G; 1034*d30ea906Sjfb8856606 case ETH_SPEED_NUM_2_5G: 1035*d30ea906Sjfb8856606 return ETH_LINK_SPEED_2_5G; 1036*d30ea906Sjfb8856606 case ETH_SPEED_NUM_5G: 1037*d30ea906Sjfb8856606 return ETH_LINK_SPEED_5G; 1038*d30ea906Sjfb8856606 case ETH_SPEED_NUM_10G: 1039*d30ea906Sjfb8856606 return ETH_LINK_SPEED_10G; 1040*d30ea906Sjfb8856606 case ETH_SPEED_NUM_20G: 1041*d30ea906Sjfb8856606 return ETH_LINK_SPEED_20G; 1042*d30ea906Sjfb8856606 case ETH_SPEED_NUM_25G: 1043*d30ea906Sjfb8856606 return ETH_LINK_SPEED_25G; 1044*d30ea906Sjfb8856606 case ETH_SPEED_NUM_40G: 1045*d30ea906Sjfb8856606 return ETH_LINK_SPEED_40G; 1046*d30ea906Sjfb8856606 case ETH_SPEED_NUM_50G: 1047*d30ea906Sjfb8856606 return ETH_LINK_SPEED_50G; 1048*d30ea906Sjfb8856606 case ETH_SPEED_NUM_56G: 1049*d30ea906Sjfb8856606 return ETH_LINK_SPEED_56G; 1050*d30ea906Sjfb8856606 case ETH_SPEED_NUM_100G: 1051*d30ea906Sjfb8856606 return ETH_LINK_SPEED_100G; 1052*d30ea906Sjfb8856606 default: 1053*d30ea906Sjfb8856606 return 0; 1054*d30ea906Sjfb8856606 } 1055*d30ea906Sjfb8856606 } 1056*d30ea906Sjfb8856606 1057*d30ea906Sjfb8856606 const char * 1058*d30ea906Sjfb8856606 rte_eth_dev_rx_offload_name(uint64_t offload) 1059*d30ea906Sjfb8856606 { 1060*d30ea906Sjfb8856606 const char *name = "UNKNOWN"; 1061*d30ea906Sjfb8856606 unsigned int i; 1062*d30ea906Sjfb8856606 1063*d30ea906Sjfb8856606 for (i = 0; i < RTE_DIM(rte_rx_offload_names); ++i) { 1064*d30ea906Sjfb8856606 if (offload == rte_rx_offload_names[i].offload) { 1065*d30ea906Sjfb8856606 name = rte_rx_offload_names[i].name; 1066*d30ea906Sjfb8856606 break; 1067*d30ea906Sjfb8856606 } 1068*d30ea906Sjfb8856606 } 1069*d30ea906Sjfb8856606 1070*d30ea906Sjfb8856606 return name; 1071*d30ea906Sjfb8856606 } 1072*d30ea906Sjfb8856606 1073*d30ea906Sjfb8856606 const char * 1074*d30ea906Sjfb8856606 rte_eth_dev_tx_offload_name(uint64_t offload) 1075*d30ea906Sjfb8856606 { 1076*d30ea906Sjfb8856606 const char *name = "UNKNOWN"; 1077*d30ea906Sjfb8856606 unsigned int i; 1078*d30ea906Sjfb8856606 1079*d30ea906Sjfb8856606 for (i = 0; i < RTE_DIM(rte_tx_offload_names); ++i) { 1080*d30ea906Sjfb8856606 if (offload == rte_tx_offload_names[i].offload) { 1081*d30ea906Sjfb8856606 name = rte_tx_offload_names[i].name; 1082*d30ea906Sjfb8856606 break; 1083*d30ea906Sjfb8856606 } 1084*d30ea906Sjfb8856606 } 1085*d30ea906Sjfb8856606 1086*d30ea906Sjfb8856606 return name; 1087*d30ea906Sjfb8856606 } 1088*d30ea906Sjfb8856606 1089*d30ea906Sjfb8856606 int 1090*d30ea906Sjfb8856606 rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q, 1091*d30ea906Sjfb8856606 const struct rte_eth_conf *dev_conf) 1092*d30ea906Sjfb8856606 { 1093*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1094*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info; 1095*d30ea906Sjfb8856606 struct rte_eth_conf orig_conf; 1096*d30ea906Sjfb8856606 int diag; 1097*d30ea906Sjfb8856606 int ret; 1098*d30ea906Sjfb8856606 1099*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1100*d30ea906Sjfb8856606 1101*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1102*d30ea906Sjfb8856606 1103*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP); 1104*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_configure, -ENOTSUP); 1105*d30ea906Sjfb8856606 1106*d30ea906Sjfb8856606 if (dev->data->dev_started) { 1107*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1108*d30ea906Sjfb8856606 "Port %u must be stopped to allow configuration\n", 1109*d30ea906Sjfb8856606 port_id); 1110*d30ea906Sjfb8856606 return -EBUSY; 1111*d30ea906Sjfb8856606 } 1112*d30ea906Sjfb8856606 1113*d30ea906Sjfb8856606 /* Store original config, as rollback required on failure */ 1114*d30ea906Sjfb8856606 memcpy(&orig_conf, &dev->data->dev_conf, sizeof(dev->data->dev_conf)); 1115*d30ea906Sjfb8856606 1116*d30ea906Sjfb8856606 /* 1117*d30ea906Sjfb8856606 * Copy the dev_conf parameter into the dev structure. 1118*d30ea906Sjfb8856606 * rte_eth_dev_info_get() requires dev_conf, copy it before dev_info get 1119*d30ea906Sjfb8856606 */ 1120*d30ea906Sjfb8856606 memcpy(&dev->data->dev_conf, dev_conf, sizeof(dev->data->dev_conf)); 1121*d30ea906Sjfb8856606 1122*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 1123*d30ea906Sjfb8856606 1124*d30ea906Sjfb8856606 /* If number of queues specified by application for both Rx and Tx is 1125*d30ea906Sjfb8856606 * zero, use driver preferred values. This cannot be done individually 1126*d30ea906Sjfb8856606 * as it is valid for either Tx or Rx (but not both) to be zero. 1127*d30ea906Sjfb8856606 * If driver does not provide any preferred valued, fall back on 1128*d30ea906Sjfb8856606 * EAL defaults. 1129*d30ea906Sjfb8856606 */ 1130*d30ea906Sjfb8856606 if (nb_rx_q == 0 && nb_tx_q == 0) { 1131*d30ea906Sjfb8856606 nb_rx_q = dev_info.default_rxportconf.nb_queues; 1132*d30ea906Sjfb8856606 if (nb_rx_q == 0) 1133*d30ea906Sjfb8856606 nb_rx_q = RTE_ETH_DEV_FALLBACK_RX_NBQUEUES; 1134*d30ea906Sjfb8856606 nb_tx_q = dev_info.default_txportconf.nb_queues; 1135*d30ea906Sjfb8856606 if (nb_tx_q == 0) 1136*d30ea906Sjfb8856606 nb_tx_q = RTE_ETH_DEV_FALLBACK_TX_NBQUEUES; 1137*d30ea906Sjfb8856606 } 1138*d30ea906Sjfb8856606 1139*d30ea906Sjfb8856606 if (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) { 1140*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1141*d30ea906Sjfb8856606 "Number of RX queues requested (%u) is greater than max supported(%d)\n", 1142*d30ea906Sjfb8856606 nb_rx_q, RTE_MAX_QUEUES_PER_PORT); 1143*d30ea906Sjfb8856606 ret = -EINVAL; 1144*d30ea906Sjfb8856606 goto rollback; 1145*d30ea906Sjfb8856606 } 1146*d30ea906Sjfb8856606 1147*d30ea906Sjfb8856606 if (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) { 1148*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1149*d30ea906Sjfb8856606 "Number of TX queues requested (%u) is greater than max supported(%d)\n", 1150*d30ea906Sjfb8856606 nb_tx_q, RTE_MAX_QUEUES_PER_PORT); 1151*d30ea906Sjfb8856606 ret = -EINVAL; 1152*d30ea906Sjfb8856606 goto rollback; 1153*d30ea906Sjfb8856606 } 1154*d30ea906Sjfb8856606 1155*d30ea906Sjfb8856606 /* 1156*d30ea906Sjfb8856606 * Check that the numbers of RX and TX queues are not greater 1157*d30ea906Sjfb8856606 * than the maximum number of RX and TX queues supported by the 1158*d30ea906Sjfb8856606 * configured device. 1159*d30ea906Sjfb8856606 */ 1160*d30ea906Sjfb8856606 if (nb_rx_q > dev_info.max_rx_queues) { 1161*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_rx_queues=%u > %u\n", 1162*d30ea906Sjfb8856606 port_id, nb_rx_q, dev_info.max_rx_queues); 1163*d30ea906Sjfb8856606 ret = -EINVAL; 1164*d30ea906Sjfb8856606 goto rollback; 1165*d30ea906Sjfb8856606 } 1166*d30ea906Sjfb8856606 1167*d30ea906Sjfb8856606 if (nb_tx_q > dev_info.max_tx_queues) { 1168*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_tx_queues=%u > %u\n", 1169*d30ea906Sjfb8856606 port_id, nb_tx_q, dev_info.max_tx_queues); 1170*d30ea906Sjfb8856606 ret = -EINVAL; 1171*d30ea906Sjfb8856606 goto rollback; 1172*d30ea906Sjfb8856606 } 1173*d30ea906Sjfb8856606 1174*d30ea906Sjfb8856606 /* Check that the device supports requested interrupts */ 1175*d30ea906Sjfb8856606 if ((dev_conf->intr_conf.lsc == 1) && 1176*d30ea906Sjfb8856606 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC))) { 1177*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Driver %s does not support lsc\n", 1178*d30ea906Sjfb8856606 dev->device->driver->name); 1179*d30ea906Sjfb8856606 ret = -EINVAL; 1180*d30ea906Sjfb8856606 goto rollback; 1181*d30ea906Sjfb8856606 } 1182*d30ea906Sjfb8856606 if ((dev_conf->intr_conf.rmv == 1) && 1183*d30ea906Sjfb8856606 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_RMV))) { 1184*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Driver %s does not support rmv\n", 1185*d30ea906Sjfb8856606 dev->device->driver->name); 1186*d30ea906Sjfb8856606 ret = -EINVAL; 1187*d30ea906Sjfb8856606 goto rollback; 1188*d30ea906Sjfb8856606 } 1189*d30ea906Sjfb8856606 1190*d30ea906Sjfb8856606 /* 1191*d30ea906Sjfb8856606 * If jumbo frames are enabled, check that the maximum RX packet 1192*d30ea906Sjfb8856606 * length is supported by the configured device. 1193*d30ea906Sjfb8856606 */ 1194*d30ea906Sjfb8856606 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1195*d30ea906Sjfb8856606 if (dev_conf->rxmode.max_rx_pkt_len > dev_info.max_rx_pktlen) { 1196*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1197*d30ea906Sjfb8856606 "Ethdev port_id=%u max_rx_pkt_len %u > max valid value %u\n", 1198*d30ea906Sjfb8856606 port_id, dev_conf->rxmode.max_rx_pkt_len, 1199*d30ea906Sjfb8856606 dev_info.max_rx_pktlen); 1200*d30ea906Sjfb8856606 ret = -EINVAL; 1201*d30ea906Sjfb8856606 goto rollback; 1202*d30ea906Sjfb8856606 } else if (dev_conf->rxmode.max_rx_pkt_len < ETHER_MIN_LEN) { 1203*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1204*d30ea906Sjfb8856606 "Ethdev port_id=%u max_rx_pkt_len %u < min valid value %u\n", 1205*d30ea906Sjfb8856606 port_id, dev_conf->rxmode.max_rx_pkt_len, 1206*d30ea906Sjfb8856606 (unsigned)ETHER_MIN_LEN); 1207*d30ea906Sjfb8856606 ret = -EINVAL; 1208*d30ea906Sjfb8856606 goto rollback; 1209*d30ea906Sjfb8856606 } 1210*d30ea906Sjfb8856606 } else { 1211*d30ea906Sjfb8856606 if (dev_conf->rxmode.max_rx_pkt_len < ETHER_MIN_LEN || 1212*d30ea906Sjfb8856606 dev_conf->rxmode.max_rx_pkt_len > ETHER_MAX_LEN) 1213*d30ea906Sjfb8856606 /* Use default value */ 1214*d30ea906Sjfb8856606 dev->data->dev_conf.rxmode.max_rx_pkt_len = 1215*d30ea906Sjfb8856606 ETHER_MAX_LEN; 1216*d30ea906Sjfb8856606 } 1217*d30ea906Sjfb8856606 1218*d30ea906Sjfb8856606 /* Any requested offloading must be within its device capabilities */ 1219*d30ea906Sjfb8856606 if ((dev_conf->rxmode.offloads & dev_info.rx_offload_capa) != 1220*d30ea906Sjfb8856606 dev_conf->rxmode.offloads) { 1221*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1222*d30ea906Sjfb8856606 "Ethdev port_id=%u requested Rx offloads 0x%"PRIx64" doesn't match Rx offloads " 1223*d30ea906Sjfb8856606 "capabilities 0x%"PRIx64" in %s()\n", 1224*d30ea906Sjfb8856606 port_id, dev_conf->rxmode.offloads, 1225*d30ea906Sjfb8856606 dev_info.rx_offload_capa, 1226*d30ea906Sjfb8856606 __func__); 1227*d30ea906Sjfb8856606 ret = -EINVAL; 1228*d30ea906Sjfb8856606 goto rollback; 1229*d30ea906Sjfb8856606 } 1230*d30ea906Sjfb8856606 if ((dev_conf->txmode.offloads & dev_info.tx_offload_capa) != 1231*d30ea906Sjfb8856606 dev_conf->txmode.offloads) { 1232*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1233*d30ea906Sjfb8856606 "Ethdev port_id=%u requested Tx offloads 0x%"PRIx64" doesn't match Tx offloads " 1234*d30ea906Sjfb8856606 "capabilities 0x%"PRIx64" in %s()\n", 1235*d30ea906Sjfb8856606 port_id, dev_conf->txmode.offloads, 1236*d30ea906Sjfb8856606 dev_info.tx_offload_capa, 1237*d30ea906Sjfb8856606 __func__); 1238*d30ea906Sjfb8856606 ret = -EINVAL; 1239*d30ea906Sjfb8856606 goto rollback; 1240*d30ea906Sjfb8856606 } 1241*d30ea906Sjfb8856606 1242*d30ea906Sjfb8856606 /* Check that device supports requested rss hash functions. */ 1243*d30ea906Sjfb8856606 if ((dev_info.flow_type_rss_offloads | 1244*d30ea906Sjfb8856606 dev_conf->rx_adv_conf.rss_conf.rss_hf) != 1245*d30ea906Sjfb8856606 dev_info.flow_type_rss_offloads) { 1246*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1247*d30ea906Sjfb8856606 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n", 1248*d30ea906Sjfb8856606 port_id, dev_conf->rx_adv_conf.rss_conf.rss_hf, 1249*d30ea906Sjfb8856606 dev_info.flow_type_rss_offloads); 1250*d30ea906Sjfb8856606 ret = -EINVAL; 1251*d30ea906Sjfb8856606 goto rollback; 1252*d30ea906Sjfb8856606 } 1253*d30ea906Sjfb8856606 1254*d30ea906Sjfb8856606 /* 1255*d30ea906Sjfb8856606 * Setup new number of RX/TX queues and reconfigure device. 1256*d30ea906Sjfb8856606 */ 1257*d30ea906Sjfb8856606 diag = rte_eth_dev_rx_queue_config(dev, nb_rx_q); 1258*d30ea906Sjfb8856606 if (diag != 0) { 1259*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1260*d30ea906Sjfb8856606 "Port%u rte_eth_dev_rx_queue_config = %d\n", 1261*d30ea906Sjfb8856606 port_id, diag); 1262*d30ea906Sjfb8856606 ret = diag; 1263*d30ea906Sjfb8856606 goto rollback; 1264*d30ea906Sjfb8856606 } 1265*d30ea906Sjfb8856606 1266*d30ea906Sjfb8856606 diag = rte_eth_dev_tx_queue_config(dev, nb_tx_q); 1267*d30ea906Sjfb8856606 if (diag != 0) { 1268*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1269*d30ea906Sjfb8856606 "Port%u rte_eth_dev_tx_queue_config = %d\n", 1270*d30ea906Sjfb8856606 port_id, diag); 1271*d30ea906Sjfb8856606 rte_eth_dev_rx_queue_config(dev, 0); 1272*d30ea906Sjfb8856606 ret = diag; 1273*d30ea906Sjfb8856606 goto rollback; 1274*d30ea906Sjfb8856606 } 1275*d30ea906Sjfb8856606 1276*d30ea906Sjfb8856606 diag = (*dev->dev_ops->dev_configure)(dev); 1277*d30ea906Sjfb8856606 if (diag != 0) { 1278*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port%u dev_configure = %d\n", 1279*d30ea906Sjfb8856606 port_id, diag); 1280*d30ea906Sjfb8856606 rte_eth_dev_rx_queue_config(dev, 0); 1281*d30ea906Sjfb8856606 rte_eth_dev_tx_queue_config(dev, 0); 1282*d30ea906Sjfb8856606 ret = eth_err(port_id, diag); 1283*d30ea906Sjfb8856606 goto rollback; 1284*d30ea906Sjfb8856606 } 1285*d30ea906Sjfb8856606 1286*d30ea906Sjfb8856606 /* Initialize Rx profiling if enabled at compilation time. */ 1287*d30ea906Sjfb8856606 diag = __rte_eth_dev_profile_init(port_id, dev); 1288*d30ea906Sjfb8856606 if (diag != 0) { 1289*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port%u __rte_eth_dev_profile_init = %d\n", 1290*d30ea906Sjfb8856606 port_id, diag); 1291*d30ea906Sjfb8856606 rte_eth_dev_rx_queue_config(dev, 0); 1292*d30ea906Sjfb8856606 rte_eth_dev_tx_queue_config(dev, 0); 1293*d30ea906Sjfb8856606 ret = eth_err(port_id, diag); 1294*d30ea906Sjfb8856606 goto rollback; 1295*d30ea906Sjfb8856606 } 1296*d30ea906Sjfb8856606 1297*d30ea906Sjfb8856606 return 0; 1298*d30ea906Sjfb8856606 1299*d30ea906Sjfb8856606 rollback: 1300*d30ea906Sjfb8856606 memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf)); 1301*d30ea906Sjfb8856606 1302*d30ea906Sjfb8856606 return ret; 1303*d30ea906Sjfb8856606 } 1304*d30ea906Sjfb8856606 1305*d30ea906Sjfb8856606 void 1306*d30ea906Sjfb8856606 _rte_eth_dev_reset(struct rte_eth_dev *dev) 1307*d30ea906Sjfb8856606 { 1308*d30ea906Sjfb8856606 if (dev->data->dev_started) { 1309*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port %u must be stopped to allow reset\n", 1310*d30ea906Sjfb8856606 dev->data->port_id); 1311*d30ea906Sjfb8856606 return; 1312*d30ea906Sjfb8856606 } 1313*d30ea906Sjfb8856606 1314*d30ea906Sjfb8856606 rte_eth_dev_rx_queue_config(dev, 0); 1315*d30ea906Sjfb8856606 rte_eth_dev_tx_queue_config(dev, 0); 1316*d30ea906Sjfb8856606 1317*d30ea906Sjfb8856606 memset(&dev->data->dev_conf, 0, sizeof(dev->data->dev_conf)); 1318*d30ea906Sjfb8856606 } 1319*d30ea906Sjfb8856606 1320*d30ea906Sjfb8856606 static void 1321*d30ea906Sjfb8856606 rte_eth_dev_mac_restore(struct rte_eth_dev *dev, 1322*d30ea906Sjfb8856606 struct rte_eth_dev_info *dev_info) 1323*d30ea906Sjfb8856606 { 1324*d30ea906Sjfb8856606 struct ether_addr *addr; 1325*d30ea906Sjfb8856606 uint16_t i; 1326*d30ea906Sjfb8856606 uint32_t pool = 0; 1327*d30ea906Sjfb8856606 uint64_t pool_mask; 1328*d30ea906Sjfb8856606 1329*d30ea906Sjfb8856606 /* replay MAC address configuration including default MAC */ 1330*d30ea906Sjfb8856606 addr = &dev->data->mac_addrs[0]; 1331*d30ea906Sjfb8856606 if (*dev->dev_ops->mac_addr_set != NULL) 1332*d30ea906Sjfb8856606 (*dev->dev_ops->mac_addr_set)(dev, addr); 1333*d30ea906Sjfb8856606 else if (*dev->dev_ops->mac_addr_add != NULL) 1334*d30ea906Sjfb8856606 (*dev->dev_ops->mac_addr_add)(dev, addr, 0, pool); 1335*d30ea906Sjfb8856606 1336*d30ea906Sjfb8856606 if (*dev->dev_ops->mac_addr_add != NULL) { 1337*d30ea906Sjfb8856606 for (i = 1; i < dev_info->max_mac_addrs; i++) { 1338*d30ea906Sjfb8856606 addr = &dev->data->mac_addrs[i]; 1339*d30ea906Sjfb8856606 1340*d30ea906Sjfb8856606 /* skip zero address */ 1341*d30ea906Sjfb8856606 if (is_zero_ether_addr(addr)) 1342*d30ea906Sjfb8856606 continue; 1343*d30ea906Sjfb8856606 1344*d30ea906Sjfb8856606 pool = 0; 1345*d30ea906Sjfb8856606 pool_mask = dev->data->mac_pool_sel[i]; 1346*d30ea906Sjfb8856606 1347*d30ea906Sjfb8856606 do { 1348*d30ea906Sjfb8856606 if (pool_mask & 1ULL) 1349*d30ea906Sjfb8856606 (*dev->dev_ops->mac_addr_add)(dev, 1350*d30ea906Sjfb8856606 addr, i, pool); 1351*d30ea906Sjfb8856606 pool_mask >>= 1; 1352*d30ea906Sjfb8856606 pool++; 1353*d30ea906Sjfb8856606 } while (pool_mask); 1354*d30ea906Sjfb8856606 } 1355*d30ea906Sjfb8856606 } 1356*d30ea906Sjfb8856606 } 1357*d30ea906Sjfb8856606 1358*d30ea906Sjfb8856606 static void 1359*d30ea906Sjfb8856606 rte_eth_dev_config_restore(struct rte_eth_dev *dev, 1360*d30ea906Sjfb8856606 struct rte_eth_dev_info *dev_info, uint16_t port_id) 1361*d30ea906Sjfb8856606 { 1362*d30ea906Sjfb8856606 if (!(*dev_info->dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR)) 1363*d30ea906Sjfb8856606 rte_eth_dev_mac_restore(dev, dev_info); 1364*d30ea906Sjfb8856606 1365*d30ea906Sjfb8856606 /* replay promiscuous configuration */ 1366*d30ea906Sjfb8856606 if (rte_eth_promiscuous_get(port_id) == 1) 1367*d30ea906Sjfb8856606 rte_eth_promiscuous_enable(port_id); 1368*d30ea906Sjfb8856606 else if (rte_eth_promiscuous_get(port_id) == 0) 1369*d30ea906Sjfb8856606 rte_eth_promiscuous_disable(port_id); 1370*d30ea906Sjfb8856606 1371*d30ea906Sjfb8856606 /* replay all multicast configuration */ 1372*d30ea906Sjfb8856606 if (rte_eth_allmulticast_get(port_id) == 1) 1373*d30ea906Sjfb8856606 rte_eth_allmulticast_enable(port_id); 1374*d30ea906Sjfb8856606 else if (rte_eth_allmulticast_get(port_id) == 0) 1375*d30ea906Sjfb8856606 rte_eth_allmulticast_disable(port_id); 1376*d30ea906Sjfb8856606 } 1377*d30ea906Sjfb8856606 1378*d30ea906Sjfb8856606 int 1379*d30ea906Sjfb8856606 rte_eth_dev_start(uint16_t port_id) 1380*d30ea906Sjfb8856606 { 1381*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1382*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info; 1383*d30ea906Sjfb8856606 int diag; 1384*d30ea906Sjfb8856606 1385*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1386*d30ea906Sjfb8856606 1387*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1388*d30ea906Sjfb8856606 1389*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP); 1390*d30ea906Sjfb8856606 1391*d30ea906Sjfb8856606 if (dev->data->dev_started != 0) { 1392*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(INFO, 1393*d30ea906Sjfb8856606 "Device with port_id=%"PRIu16" already started\n", 1394*d30ea906Sjfb8856606 port_id); 1395*d30ea906Sjfb8856606 return 0; 1396*d30ea906Sjfb8856606 } 1397*d30ea906Sjfb8856606 1398*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 1399*d30ea906Sjfb8856606 1400*d30ea906Sjfb8856606 /* Lets restore MAC now if device does not support live change */ 1401*d30ea906Sjfb8856606 if (*dev_info.dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR) 1402*d30ea906Sjfb8856606 rte_eth_dev_mac_restore(dev, &dev_info); 1403*d30ea906Sjfb8856606 1404*d30ea906Sjfb8856606 diag = (*dev->dev_ops->dev_start)(dev); 1405*d30ea906Sjfb8856606 if (diag == 0) 1406*d30ea906Sjfb8856606 dev->data->dev_started = 1; 1407*d30ea906Sjfb8856606 else 1408*d30ea906Sjfb8856606 return eth_err(port_id, diag); 1409*d30ea906Sjfb8856606 1410*d30ea906Sjfb8856606 rte_eth_dev_config_restore(dev, &dev_info, port_id); 1411*d30ea906Sjfb8856606 1412*d30ea906Sjfb8856606 if (dev->data->dev_conf.intr_conf.lsc == 0) { 1413*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP); 1414*d30ea906Sjfb8856606 (*dev->dev_ops->link_update)(dev, 0); 1415*d30ea906Sjfb8856606 } 1416*d30ea906Sjfb8856606 return 0; 1417*d30ea906Sjfb8856606 } 1418*d30ea906Sjfb8856606 1419*d30ea906Sjfb8856606 void 1420*d30ea906Sjfb8856606 rte_eth_dev_stop(uint16_t port_id) 1421*d30ea906Sjfb8856606 { 1422*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1423*d30ea906Sjfb8856606 1424*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1425*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1426*d30ea906Sjfb8856606 1427*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_stop); 1428*d30ea906Sjfb8856606 1429*d30ea906Sjfb8856606 if (dev->data->dev_started == 0) { 1430*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(INFO, 1431*d30ea906Sjfb8856606 "Device with port_id=%"PRIu16" already stopped\n", 1432*d30ea906Sjfb8856606 port_id); 1433*d30ea906Sjfb8856606 return; 1434*d30ea906Sjfb8856606 } 1435*d30ea906Sjfb8856606 1436*d30ea906Sjfb8856606 dev->data->dev_started = 0; 1437*d30ea906Sjfb8856606 (*dev->dev_ops->dev_stop)(dev); 1438*d30ea906Sjfb8856606 } 1439*d30ea906Sjfb8856606 1440*d30ea906Sjfb8856606 int 1441*d30ea906Sjfb8856606 rte_eth_dev_set_link_up(uint16_t port_id) 1442*d30ea906Sjfb8856606 { 1443*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1444*d30ea906Sjfb8856606 1445*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1446*d30ea906Sjfb8856606 1447*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1448*d30ea906Sjfb8856606 1449*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_up, -ENOTSUP); 1450*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->dev_set_link_up)(dev)); 1451*d30ea906Sjfb8856606 } 1452*d30ea906Sjfb8856606 1453*d30ea906Sjfb8856606 int 1454*d30ea906Sjfb8856606 rte_eth_dev_set_link_down(uint16_t port_id) 1455*d30ea906Sjfb8856606 { 1456*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1457*d30ea906Sjfb8856606 1458*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1459*d30ea906Sjfb8856606 1460*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1461*d30ea906Sjfb8856606 1462*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_down, -ENOTSUP); 1463*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->dev_set_link_down)(dev)); 1464*d30ea906Sjfb8856606 } 1465*d30ea906Sjfb8856606 1466*d30ea906Sjfb8856606 void 1467*d30ea906Sjfb8856606 rte_eth_dev_close(uint16_t port_id) 1468*d30ea906Sjfb8856606 { 1469*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1470*d30ea906Sjfb8856606 1471*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1472*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1473*d30ea906Sjfb8856606 1474*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_close); 1475*d30ea906Sjfb8856606 dev->data->dev_started = 0; 1476*d30ea906Sjfb8856606 (*dev->dev_ops->dev_close)(dev); 1477*d30ea906Sjfb8856606 1478*d30ea906Sjfb8856606 /* check behaviour flag - temporary for PMD migration */ 1479*d30ea906Sjfb8856606 if ((dev->data->dev_flags & RTE_ETH_DEV_CLOSE_REMOVE) != 0) { 1480*d30ea906Sjfb8856606 /* new behaviour: send event + reset state + free all data */ 1481*d30ea906Sjfb8856606 rte_eth_dev_release_port(dev); 1482*d30ea906Sjfb8856606 return; 1483*d30ea906Sjfb8856606 } 1484*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(DEBUG, "Port closing is using an old behaviour.\n" 1485*d30ea906Sjfb8856606 "The driver %s should migrate to the new behaviour.\n", 1486*d30ea906Sjfb8856606 dev->device->driver->name); 1487*d30ea906Sjfb8856606 /* old behaviour: only free queue arrays */ 1488*d30ea906Sjfb8856606 dev->data->nb_rx_queues = 0; 1489*d30ea906Sjfb8856606 rte_free(dev->data->rx_queues); 1490*d30ea906Sjfb8856606 dev->data->rx_queues = NULL; 1491*d30ea906Sjfb8856606 dev->data->nb_tx_queues = 0; 1492*d30ea906Sjfb8856606 rte_free(dev->data->tx_queues); 1493*d30ea906Sjfb8856606 dev->data->tx_queues = NULL; 1494*d30ea906Sjfb8856606 } 1495*d30ea906Sjfb8856606 1496*d30ea906Sjfb8856606 int 1497*d30ea906Sjfb8856606 rte_eth_dev_reset(uint16_t port_id) 1498*d30ea906Sjfb8856606 { 1499*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1500*d30ea906Sjfb8856606 int ret; 1501*d30ea906Sjfb8856606 1502*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1503*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1504*d30ea906Sjfb8856606 1505*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_reset, -ENOTSUP); 1506*d30ea906Sjfb8856606 1507*d30ea906Sjfb8856606 rte_eth_dev_stop(port_id); 1508*d30ea906Sjfb8856606 ret = dev->dev_ops->dev_reset(dev); 1509*d30ea906Sjfb8856606 1510*d30ea906Sjfb8856606 return eth_err(port_id, ret); 1511*d30ea906Sjfb8856606 } 1512*d30ea906Sjfb8856606 1513*d30ea906Sjfb8856606 int __rte_experimental 1514*d30ea906Sjfb8856606 rte_eth_dev_is_removed(uint16_t port_id) 1515*d30ea906Sjfb8856606 { 1516*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1517*d30ea906Sjfb8856606 int ret; 1518*d30ea906Sjfb8856606 1519*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0); 1520*d30ea906Sjfb8856606 1521*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1522*d30ea906Sjfb8856606 1523*d30ea906Sjfb8856606 if (dev->state == RTE_ETH_DEV_REMOVED) 1524*d30ea906Sjfb8856606 return 1; 1525*d30ea906Sjfb8856606 1526*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->is_removed, 0); 1527*d30ea906Sjfb8856606 1528*d30ea906Sjfb8856606 ret = dev->dev_ops->is_removed(dev); 1529*d30ea906Sjfb8856606 if (ret != 0) 1530*d30ea906Sjfb8856606 /* Device is physically removed. */ 1531*d30ea906Sjfb8856606 dev->state = RTE_ETH_DEV_REMOVED; 1532*d30ea906Sjfb8856606 1533*d30ea906Sjfb8856606 return ret; 1534*d30ea906Sjfb8856606 } 1535*d30ea906Sjfb8856606 1536*d30ea906Sjfb8856606 int 1537*d30ea906Sjfb8856606 rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id, 1538*d30ea906Sjfb8856606 uint16_t nb_rx_desc, unsigned int socket_id, 1539*d30ea906Sjfb8856606 const struct rte_eth_rxconf *rx_conf, 1540*d30ea906Sjfb8856606 struct rte_mempool *mp) 1541*d30ea906Sjfb8856606 { 1542*d30ea906Sjfb8856606 int ret; 1543*d30ea906Sjfb8856606 uint32_t mbp_buf_size; 1544*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1545*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info; 1546*d30ea906Sjfb8856606 struct rte_eth_rxconf local_conf; 1547*d30ea906Sjfb8856606 void **rxq; 1548*d30ea906Sjfb8856606 1549*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1550*d30ea906Sjfb8856606 1551*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1552*d30ea906Sjfb8856606 if (rx_queue_id >= dev->data->nb_rx_queues) { 1553*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id); 1554*d30ea906Sjfb8856606 return -EINVAL; 1555*d30ea906Sjfb8856606 } 1556*d30ea906Sjfb8856606 1557*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP); 1558*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_setup, -ENOTSUP); 1559*d30ea906Sjfb8856606 1560*d30ea906Sjfb8856606 /* 1561*d30ea906Sjfb8856606 * Check the size of the mbuf data buffer. 1562*d30ea906Sjfb8856606 * This value must be provided in the private data of the memory pool. 1563*d30ea906Sjfb8856606 * First check that the memory pool has a valid private data. 1564*d30ea906Sjfb8856606 */ 1565*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 1566*d30ea906Sjfb8856606 if (mp->private_data_size < sizeof(struct rte_pktmbuf_pool_private)) { 1567*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "%s private_data_size %d < %d\n", 1568*d30ea906Sjfb8856606 mp->name, (int)mp->private_data_size, 1569*d30ea906Sjfb8856606 (int)sizeof(struct rte_pktmbuf_pool_private)); 1570*d30ea906Sjfb8856606 return -ENOSPC; 1571*d30ea906Sjfb8856606 } 1572*d30ea906Sjfb8856606 mbp_buf_size = rte_pktmbuf_data_room_size(mp); 1573*d30ea906Sjfb8856606 1574*d30ea906Sjfb8856606 if ((mbp_buf_size - RTE_PKTMBUF_HEADROOM) < dev_info.min_rx_bufsize) { 1575*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1576*d30ea906Sjfb8856606 "%s mbuf_data_room_size %d < %d (RTE_PKTMBUF_HEADROOM=%d + min_rx_bufsize(dev)=%d)\n", 1577*d30ea906Sjfb8856606 mp->name, (int)mbp_buf_size, 1578*d30ea906Sjfb8856606 (int)(RTE_PKTMBUF_HEADROOM + dev_info.min_rx_bufsize), 1579*d30ea906Sjfb8856606 (int)RTE_PKTMBUF_HEADROOM, 1580*d30ea906Sjfb8856606 (int)dev_info.min_rx_bufsize); 1581*d30ea906Sjfb8856606 return -EINVAL; 1582*d30ea906Sjfb8856606 } 1583*d30ea906Sjfb8856606 1584*d30ea906Sjfb8856606 /* Use default specified by driver, if nb_rx_desc is zero */ 1585*d30ea906Sjfb8856606 if (nb_rx_desc == 0) { 1586*d30ea906Sjfb8856606 nb_rx_desc = dev_info.default_rxportconf.ring_size; 1587*d30ea906Sjfb8856606 /* If driver default is also zero, fall back on EAL default */ 1588*d30ea906Sjfb8856606 if (nb_rx_desc == 0) 1589*d30ea906Sjfb8856606 nb_rx_desc = RTE_ETH_DEV_FALLBACK_RX_RINGSIZE; 1590*d30ea906Sjfb8856606 } 1591*d30ea906Sjfb8856606 1592*d30ea906Sjfb8856606 if (nb_rx_desc > dev_info.rx_desc_lim.nb_max || 1593*d30ea906Sjfb8856606 nb_rx_desc < dev_info.rx_desc_lim.nb_min || 1594*d30ea906Sjfb8856606 nb_rx_desc % dev_info.rx_desc_lim.nb_align != 0) { 1595*d30ea906Sjfb8856606 1596*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1597*d30ea906Sjfb8856606 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu, = %hu, and a product of %hu\n", 1598*d30ea906Sjfb8856606 nb_rx_desc, dev_info.rx_desc_lim.nb_max, 1599*d30ea906Sjfb8856606 dev_info.rx_desc_lim.nb_min, 1600*d30ea906Sjfb8856606 dev_info.rx_desc_lim.nb_align); 1601*d30ea906Sjfb8856606 return -EINVAL; 1602*d30ea906Sjfb8856606 } 1603*d30ea906Sjfb8856606 1604*d30ea906Sjfb8856606 if (dev->data->dev_started && 1605*d30ea906Sjfb8856606 !(dev_info.dev_capa & 1606*d30ea906Sjfb8856606 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP)) 1607*d30ea906Sjfb8856606 return -EBUSY; 1608*d30ea906Sjfb8856606 1609*d30ea906Sjfb8856606 if (dev->data->dev_started && 1610*d30ea906Sjfb8856606 (dev->data->rx_queue_state[rx_queue_id] != 1611*d30ea906Sjfb8856606 RTE_ETH_QUEUE_STATE_STOPPED)) 1612*d30ea906Sjfb8856606 return -EBUSY; 1613*d30ea906Sjfb8856606 1614*d30ea906Sjfb8856606 rxq = dev->data->rx_queues; 1615*d30ea906Sjfb8856606 if (rxq[rx_queue_id]) { 1616*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, 1617*d30ea906Sjfb8856606 -ENOTSUP); 1618*d30ea906Sjfb8856606 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]); 1619*d30ea906Sjfb8856606 rxq[rx_queue_id] = NULL; 1620*d30ea906Sjfb8856606 } 1621*d30ea906Sjfb8856606 1622*d30ea906Sjfb8856606 if (rx_conf == NULL) 1623*d30ea906Sjfb8856606 rx_conf = &dev_info.default_rxconf; 1624*d30ea906Sjfb8856606 1625*d30ea906Sjfb8856606 local_conf = *rx_conf; 1626*d30ea906Sjfb8856606 1627*d30ea906Sjfb8856606 /* 1628*d30ea906Sjfb8856606 * If an offloading has already been enabled in 1629*d30ea906Sjfb8856606 * rte_eth_dev_configure(), it has been enabled on all queues, 1630*d30ea906Sjfb8856606 * so there is no need to enable it in this queue again. 1631*d30ea906Sjfb8856606 * The local_conf.offloads input to underlying PMD only carries 1632*d30ea906Sjfb8856606 * those offloadings which are only enabled on this queue and 1633*d30ea906Sjfb8856606 * not enabled on all queues. 1634*d30ea906Sjfb8856606 */ 1635*d30ea906Sjfb8856606 local_conf.offloads &= ~dev->data->dev_conf.rxmode.offloads; 1636*d30ea906Sjfb8856606 1637*d30ea906Sjfb8856606 /* 1638*d30ea906Sjfb8856606 * New added offloadings for this queue are those not enabled in 1639*d30ea906Sjfb8856606 * rte_eth_dev_configure() and they must be per-queue type. 1640*d30ea906Sjfb8856606 * A pure per-port offloading can't be enabled on a queue while 1641*d30ea906Sjfb8856606 * disabled on another queue. A pure per-port offloading can't 1642*d30ea906Sjfb8856606 * be enabled for any queue as new added one if it hasn't been 1643*d30ea906Sjfb8856606 * enabled in rte_eth_dev_configure(). 1644*d30ea906Sjfb8856606 */ 1645*d30ea906Sjfb8856606 if ((local_conf.offloads & dev_info.rx_queue_offload_capa) != 1646*d30ea906Sjfb8856606 local_conf.offloads) { 1647*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1648*d30ea906Sjfb8856606 "Ethdev port_id=%d rx_queue_id=%d, new added offloads 0x%"PRIx64" must be " 1649*d30ea906Sjfb8856606 "within pre-queue offload capabilities 0x%"PRIx64" in %s()\n", 1650*d30ea906Sjfb8856606 port_id, rx_queue_id, local_conf.offloads, 1651*d30ea906Sjfb8856606 dev_info.rx_queue_offload_capa, 1652*d30ea906Sjfb8856606 __func__); 1653*d30ea906Sjfb8856606 return -EINVAL; 1654*d30ea906Sjfb8856606 } 1655*d30ea906Sjfb8856606 1656*d30ea906Sjfb8856606 ret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc, 1657*d30ea906Sjfb8856606 socket_id, &local_conf, mp); 1658*d30ea906Sjfb8856606 if (!ret) { 1659*d30ea906Sjfb8856606 if (!dev->data->min_rx_buf_size || 1660*d30ea906Sjfb8856606 dev->data->min_rx_buf_size > mbp_buf_size) 1661*d30ea906Sjfb8856606 dev->data->min_rx_buf_size = mbp_buf_size; 1662*d30ea906Sjfb8856606 } 1663*d30ea906Sjfb8856606 1664*d30ea906Sjfb8856606 return eth_err(port_id, ret); 1665*d30ea906Sjfb8856606 } 1666*d30ea906Sjfb8856606 1667*d30ea906Sjfb8856606 int 1668*d30ea906Sjfb8856606 rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id, 1669*d30ea906Sjfb8856606 uint16_t nb_tx_desc, unsigned int socket_id, 1670*d30ea906Sjfb8856606 const struct rte_eth_txconf *tx_conf) 1671*d30ea906Sjfb8856606 { 1672*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1673*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info; 1674*d30ea906Sjfb8856606 struct rte_eth_txconf local_conf; 1675*d30ea906Sjfb8856606 void **txq; 1676*d30ea906Sjfb8856606 1677*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1678*d30ea906Sjfb8856606 1679*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1680*d30ea906Sjfb8856606 if (tx_queue_id >= dev->data->nb_tx_queues) { 1681*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id); 1682*d30ea906Sjfb8856606 return -EINVAL; 1683*d30ea906Sjfb8856606 } 1684*d30ea906Sjfb8856606 1685*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP); 1686*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_setup, -ENOTSUP); 1687*d30ea906Sjfb8856606 1688*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 1689*d30ea906Sjfb8856606 1690*d30ea906Sjfb8856606 /* Use default specified by driver, if nb_tx_desc is zero */ 1691*d30ea906Sjfb8856606 if (nb_tx_desc == 0) { 1692*d30ea906Sjfb8856606 nb_tx_desc = dev_info.default_txportconf.ring_size; 1693*d30ea906Sjfb8856606 /* If driver default is zero, fall back on EAL default */ 1694*d30ea906Sjfb8856606 if (nb_tx_desc == 0) 1695*d30ea906Sjfb8856606 nb_tx_desc = RTE_ETH_DEV_FALLBACK_TX_RINGSIZE; 1696*d30ea906Sjfb8856606 } 1697*d30ea906Sjfb8856606 if (nb_tx_desc > dev_info.tx_desc_lim.nb_max || 1698*d30ea906Sjfb8856606 nb_tx_desc < dev_info.tx_desc_lim.nb_min || 1699*d30ea906Sjfb8856606 nb_tx_desc % dev_info.tx_desc_lim.nb_align != 0) { 1700*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1701*d30ea906Sjfb8856606 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu, = %hu, and a product of %hu\n", 1702*d30ea906Sjfb8856606 nb_tx_desc, dev_info.tx_desc_lim.nb_max, 1703*d30ea906Sjfb8856606 dev_info.tx_desc_lim.nb_min, 1704*d30ea906Sjfb8856606 dev_info.tx_desc_lim.nb_align); 1705*d30ea906Sjfb8856606 return -EINVAL; 1706*d30ea906Sjfb8856606 } 1707*d30ea906Sjfb8856606 1708*d30ea906Sjfb8856606 if (dev->data->dev_started && 1709*d30ea906Sjfb8856606 !(dev_info.dev_capa & 1710*d30ea906Sjfb8856606 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP)) 1711*d30ea906Sjfb8856606 return -EBUSY; 1712*d30ea906Sjfb8856606 1713*d30ea906Sjfb8856606 if (dev->data->dev_started && 1714*d30ea906Sjfb8856606 (dev->data->tx_queue_state[tx_queue_id] != 1715*d30ea906Sjfb8856606 RTE_ETH_QUEUE_STATE_STOPPED)) 1716*d30ea906Sjfb8856606 return -EBUSY; 1717*d30ea906Sjfb8856606 1718*d30ea906Sjfb8856606 txq = dev->data->tx_queues; 1719*d30ea906Sjfb8856606 if (txq[tx_queue_id]) { 1720*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, 1721*d30ea906Sjfb8856606 -ENOTSUP); 1722*d30ea906Sjfb8856606 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]); 1723*d30ea906Sjfb8856606 txq[tx_queue_id] = NULL; 1724*d30ea906Sjfb8856606 } 1725*d30ea906Sjfb8856606 1726*d30ea906Sjfb8856606 if (tx_conf == NULL) 1727*d30ea906Sjfb8856606 tx_conf = &dev_info.default_txconf; 1728*d30ea906Sjfb8856606 1729*d30ea906Sjfb8856606 local_conf = *tx_conf; 1730*d30ea906Sjfb8856606 1731*d30ea906Sjfb8856606 /* 1732*d30ea906Sjfb8856606 * If an offloading has already been enabled in 1733*d30ea906Sjfb8856606 * rte_eth_dev_configure(), it has been enabled on all queues, 1734*d30ea906Sjfb8856606 * so there is no need to enable it in this queue again. 1735*d30ea906Sjfb8856606 * The local_conf.offloads input to underlying PMD only carries 1736*d30ea906Sjfb8856606 * those offloadings which are only enabled on this queue and 1737*d30ea906Sjfb8856606 * not enabled on all queues. 1738*d30ea906Sjfb8856606 */ 1739*d30ea906Sjfb8856606 local_conf.offloads &= ~dev->data->dev_conf.txmode.offloads; 1740*d30ea906Sjfb8856606 1741*d30ea906Sjfb8856606 /* 1742*d30ea906Sjfb8856606 * New added offloadings for this queue are those not enabled in 1743*d30ea906Sjfb8856606 * rte_eth_dev_configure() and they must be per-queue type. 1744*d30ea906Sjfb8856606 * A pure per-port offloading can't be enabled on a queue while 1745*d30ea906Sjfb8856606 * disabled on another queue. A pure per-port offloading can't 1746*d30ea906Sjfb8856606 * be enabled for any queue as new added one if it hasn't been 1747*d30ea906Sjfb8856606 * enabled in rte_eth_dev_configure(). 1748*d30ea906Sjfb8856606 */ 1749*d30ea906Sjfb8856606 if ((local_conf.offloads & dev_info.tx_queue_offload_capa) != 1750*d30ea906Sjfb8856606 local_conf.offloads) { 1751*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 1752*d30ea906Sjfb8856606 "Ethdev port_id=%d tx_queue_id=%d, new added offloads 0x%"PRIx64" must be " 1753*d30ea906Sjfb8856606 "within pre-queue offload capabilities 0x%"PRIx64" in %s()\n", 1754*d30ea906Sjfb8856606 port_id, tx_queue_id, local_conf.offloads, 1755*d30ea906Sjfb8856606 dev_info.tx_queue_offload_capa, 1756*d30ea906Sjfb8856606 __func__); 1757*d30ea906Sjfb8856606 return -EINVAL; 1758*d30ea906Sjfb8856606 } 1759*d30ea906Sjfb8856606 1760*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->tx_queue_setup)(dev, 1761*d30ea906Sjfb8856606 tx_queue_id, nb_tx_desc, socket_id, &local_conf)); 1762*d30ea906Sjfb8856606 } 1763*d30ea906Sjfb8856606 1764*d30ea906Sjfb8856606 void 1765*d30ea906Sjfb8856606 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent, 1766*d30ea906Sjfb8856606 void *userdata __rte_unused) 1767*d30ea906Sjfb8856606 { 1768*d30ea906Sjfb8856606 unsigned i; 1769*d30ea906Sjfb8856606 1770*d30ea906Sjfb8856606 for (i = 0; i < unsent; i++) 1771*d30ea906Sjfb8856606 rte_pktmbuf_free(pkts[i]); 1772*d30ea906Sjfb8856606 } 1773*d30ea906Sjfb8856606 1774*d30ea906Sjfb8856606 void 1775*d30ea906Sjfb8856606 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent, 1776*d30ea906Sjfb8856606 void *userdata) 1777*d30ea906Sjfb8856606 { 1778*d30ea906Sjfb8856606 uint64_t *count = userdata; 1779*d30ea906Sjfb8856606 unsigned i; 1780*d30ea906Sjfb8856606 1781*d30ea906Sjfb8856606 for (i = 0; i < unsent; i++) 1782*d30ea906Sjfb8856606 rte_pktmbuf_free(pkts[i]); 1783*d30ea906Sjfb8856606 1784*d30ea906Sjfb8856606 *count += unsent; 1785*d30ea906Sjfb8856606 } 1786*d30ea906Sjfb8856606 1787*d30ea906Sjfb8856606 int 1788*d30ea906Sjfb8856606 rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer, 1789*d30ea906Sjfb8856606 buffer_tx_error_fn cbfn, void *userdata) 1790*d30ea906Sjfb8856606 { 1791*d30ea906Sjfb8856606 buffer->error_callback = cbfn; 1792*d30ea906Sjfb8856606 buffer->error_userdata = userdata; 1793*d30ea906Sjfb8856606 return 0; 1794*d30ea906Sjfb8856606 } 1795*d30ea906Sjfb8856606 1796*d30ea906Sjfb8856606 int 1797*d30ea906Sjfb8856606 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size) 1798*d30ea906Sjfb8856606 { 1799*d30ea906Sjfb8856606 int ret = 0; 1800*d30ea906Sjfb8856606 1801*d30ea906Sjfb8856606 if (buffer == NULL) 1802*d30ea906Sjfb8856606 return -EINVAL; 1803*d30ea906Sjfb8856606 1804*d30ea906Sjfb8856606 buffer->size = size; 1805*d30ea906Sjfb8856606 if (buffer->error_callback == NULL) { 1806*d30ea906Sjfb8856606 ret = rte_eth_tx_buffer_set_err_callback( 1807*d30ea906Sjfb8856606 buffer, rte_eth_tx_buffer_drop_callback, NULL); 1808*d30ea906Sjfb8856606 } 1809*d30ea906Sjfb8856606 1810*d30ea906Sjfb8856606 return ret; 1811*d30ea906Sjfb8856606 } 1812*d30ea906Sjfb8856606 1813*d30ea906Sjfb8856606 int 1814*d30ea906Sjfb8856606 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt) 1815*d30ea906Sjfb8856606 { 1816*d30ea906Sjfb8856606 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 1817*d30ea906Sjfb8856606 int ret; 1818*d30ea906Sjfb8856606 1819*d30ea906Sjfb8856606 /* Validate Input Data. Bail if not valid or not supported. */ 1820*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1821*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_done_cleanup, -ENOTSUP); 1822*d30ea906Sjfb8856606 1823*d30ea906Sjfb8856606 /* Call driver to free pending mbufs. */ 1824*d30ea906Sjfb8856606 ret = (*dev->dev_ops->tx_done_cleanup)(dev->data->tx_queues[queue_id], 1825*d30ea906Sjfb8856606 free_cnt); 1826*d30ea906Sjfb8856606 return eth_err(port_id, ret); 1827*d30ea906Sjfb8856606 } 1828*d30ea906Sjfb8856606 1829*d30ea906Sjfb8856606 void 1830*d30ea906Sjfb8856606 rte_eth_promiscuous_enable(uint16_t port_id) 1831*d30ea906Sjfb8856606 { 1832*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1833*d30ea906Sjfb8856606 1834*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1835*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1836*d30ea906Sjfb8856606 1837*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->promiscuous_enable); 1838*d30ea906Sjfb8856606 (*dev->dev_ops->promiscuous_enable)(dev); 1839*d30ea906Sjfb8856606 dev->data->promiscuous = 1; 1840*d30ea906Sjfb8856606 } 1841*d30ea906Sjfb8856606 1842*d30ea906Sjfb8856606 void 1843*d30ea906Sjfb8856606 rte_eth_promiscuous_disable(uint16_t port_id) 1844*d30ea906Sjfb8856606 { 1845*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1846*d30ea906Sjfb8856606 1847*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1848*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1849*d30ea906Sjfb8856606 1850*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->promiscuous_disable); 1851*d30ea906Sjfb8856606 dev->data->promiscuous = 0; 1852*d30ea906Sjfb8856606 (*dev->dev_ops->promiscuous_disable)(dev); 1853*d30ea906Sjfb8856606 } 1854*d30ea906Sjfb8856606 1855*d30ea906Sjfb8856606 int 1856*d30ea906Sjfb8856606 rte_eth_promiscuous_get(uint16_t port_id) 1857*d30ea906Sjfb8856606 { 1858*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1859*d30ea906Sjfb8856606 1860*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1861*d30ea906Sjfb8856606 1862*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1863*d30ea906Sjfb8856606 return dev->data->promiscuous; 1864*d30ea906Sjfb8856606 } 1865*d30ea906Sjfb8856606 1866*d30ea906Sjfb8856606 void 1867*d30ea906Sjfb8856606 rte_eth_allmulticast_enable(uint16_t port_id) 1868*d30ea906Sjfb8856606 { 1869*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1870*d30ea906Sjfb8856606 1871*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1872*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1873*d30ea906Sjfb8856606 1874*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->allmulticast_enable); 1875*d30ea906Sjfb8856606 (*dev->dev_ops->allmulticast_enable)(dev); 1876*d30ea906Sjfb8856606 dev->data->all_multicast = 1; 1877*d30ea906Sjfb8856606 } 1878*d30ea906Sjfb8856606 1879*d30ea906Sjfb8856606 void 1880*d30ea906Sjfb8856606 rte_eth_allmulticast_disable(uint16_t port_id) 1881*d30ea906Sjfb8856606 { 1882*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1883*d30ea906Sjfb8856606 1884*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1885*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1886*d30ea906Sjfb8856606 1887*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->allmulticast_disable); 1888*d30ea906Sjfb8856606 dev->data->all_multicast = 0; 1889*d30ea906Sjfb8856606 (*dev->dev_ops->allmulticast_disable)(dev); 1890*d30ea906Sjfb8856606 } 1891*d30ea906Sjfb8856606 1892*d30ea906Sjfb8856606 int 1893*d30ea906Sjfb8856606 rte_eth_allmulticast_get(uint16_t port_id) 1894*d30ea906Sjfb8856606 { 1895*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1896*d30ea906Sjfb8856606 1897*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1898*d30ea906Sjfb8856606 1899*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1900*d30ea906Sjfb8856606 return dev->data->all_multicast; 1901*d30ea906Sjfb8856606 } 1902*d30ea906Sjfb8856606 1903*d30ea906Sjfb8856606 void 1904*d30ea906Sjfb8856606 rte_eth_link_get(uint16_t port_id, struct rte_eth_link *eth_link) 1905*d30ea906Sjfb8856606 { 1906*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1907*d30ea906Sjfb8856606 1908*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1909*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1910*d30ea906Sjfb8856606 1911*d30ea906Sjfb8856606 if (dev->data->dev_conf.intr_conf.lsc && 1912*d30ea906Sjfb8856606 dev->data->dev_started) 1913*d30ea906Sjfb8856606 rte_eth_linkstatus_get(dev, eth_link); 1914*d30ea906Sjfb8856606 else { 1915*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->link_update); 1916*d30ea906Sjfb8856606 (*dev->dev_ops->link_update)(dev, 1); 1917*d30ea906Sjfb8856606 *eth_link = dev->data->dev_link; 1918*d30ea906Sjfb8856606 } 1919*d30ea906Sjfb8856606 } 1920*d30ea906Sjfb8856606 1921*d30ea906Sjfb8856606 void 1922*d30ea906Sjfb8856606 rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *eth_link) 1923*d30ea906Sjfb8856606 { 1924*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1925*d30ea906Sjfb8856606 1926*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 1927*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1928*d30ea906Sjfb8856606 1929*d30ea906Sjfb8856606 if (dev->data->dev_conf.intr_conf.lsc && 1930*d30ea906Sjfb8856606 dev->data->dev_started) 1931*d30ea906Sjfb8856606 rte_eth_linkstatus_get(dev, eth_link); 1932*d30ea906Sjfb8856606 else { 1933*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->link_update); 1934*d30ea906Sjfb8856606 (*dev->dev_ops->link_update)(dev, 0); 1935*d30ea906Sjfb8856606 *eth_link = dev->data->dev_link; 1936*d30ea906Sjfb8856606 } 1937*d30ea906Sjfb8856606 } 1938*d30ea906Sjfb8856606 1939*d30ea906Sjfb8856606 int 1940*d30ea906Sjfb8856606 rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats) 1941*d30ea906Sjfb8856606 { 1942*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1943*d30ea906Sjfb8856606 1944*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1945*d30ea906Sjfb8856606 1946*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1947*d30ea906Sjfb8856606 memset(stats, 0, sizeof(*stats)); 1948*d30ea906Sjfb8856606 1949*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP); 1950*d30ea906Sjfb8856606 stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed; 1951*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats)); 1952*d30ea906Sjfb8856606 } 1953*d30ea906Sjfb8856606 1954*d30ea906Sjfb8856606 int 1955*d30ea906Sjfb8856606 rte_eth_stats_reset(uint16_t port_id) 1956*d30ea906Sjfb8856606 { 1957*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1958*d30ea906Sjfb8856606 1959*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 1960*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1961*d30ea906Sjfb8856606 1962*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_reset, -ENOTSUP); 1963*d30ea906Sjfb8856606 (*dev->dev_ops->stats_reset)(dev); 1964*d30ea906Sjfb8856606 dev->data->rx_mbuf_alloc_failed = 0; 1965*d30ea906Sjfb8856606 1966*d30ea906Sjfb8856606 return 0; 1967*d30ea906Sjfb8856606 } 1968*d30ea906Sjfb8856606 1969*d30ea906Sjfb8856606 static inline int 1970*d30ea906Sjfb8856606 get_xstats_basic_count(struct rte_eth_dev *dev) 1971*d30ea906Sjfb8856606 { 1972*d30ea906Sjfb8856606 uint16_t nb_rxqs, nb_txqs; 1973*d30ea906Sjfb8856606 int count; 1974*d30ea906Sjfb8856606 1975*d30ea906Sjfb8856606 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1976*d30ea906Sjfb8856606 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1977*d30ea906Sjfb8856606 1978*d30ea906Sjfb8856606 count = RTE_NB_STATS; 1979*d30ea906Sjfb8856606 count += nb_rxqs * RTE_NB_RXQ_STATS; 1980*d30ea906Sjfb8856606 count += nb_txqs * RTE_NB_TXQ_STATS; 1981*d30ea906Sjfb8856606 1982*d30ea906Sjfb8856606 return count; 1983*d30ea906Sjfb8856606 } 1984*d30ea906Sjfb8856606 1985*d30ea906Sjfb8856606 static int 1986*d30ea906Sjfb8856606 get_xstats_count(uint16_t port_id) 1987*d30ea906Sjfb8856606 { 1988*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 1989*d30ea906Sjfb8856606 int count; 1990*d30ea906Sjfb8856606 1991*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 1992*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 1993*d30ea906Sjfb8856606 if (dev->dev_ops->xstats_get_names_by_id != NULL) { 1994*d30ea906Sjfb8856606 count = (*dev->dev_ops->xstats_get_names_by_id)(dev, NULL, 1995*d30ea906Sjfb8856606 NULL, 0); 1996*d30ea906Sjfb8856606 if (count < 0) 1997*d30ea906Sjfb8856606 return eth_err(port_id, count); 1998*d30ea906Sjfb8856606 } 1999*d30ea906Sjfb8856606 if (dev->dev_ops->xstats_get_names != NULL) { 2000*d30ea906Sjfb8856606 count = (*dev->dev_ops->xstats_get_names)(dev, NULL, 0); 2001*d30ea906Sjfb8856606 if (count < 0) 2002*d30ea906Sjfb8856606 return eth_err(port_id, count); 2003*d30ea906Sjfb8856606 } else 2004*d30ea906Sjfb8856606 count = 0; 2005*d30ea906Sjfb8856606 2006*d30ea906Sjfb8856606 2007*d30ea906Sjfb8856606 count += get_xstats_basic_count(dev); 2008*d30ea906Sjfb8856606 2009*d30ea906Sjfb8856606 return count; 2010*d30ea906Sjfb8856606 } 2011*d30ea906Sjfb8856606 2012*d30ea906Sjfb8856606 int 2013*d30ea906Sjfb8856606 rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name, 2014*d30ea906Sjfb8856606 uint64_t *id) 2015*d30ea906Sjfb8856606 { 2016*d30ea906Sjfb8856606 int cnt_xstats, idx_xstat; 2017*d30ea906Sjfb8856606 2018*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2019*d30ea906Sjfb8856606 2020*d30ea906Sjfb8856606 if (!id) { 2021*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Id pointer is NULL\n"); 2022*d30ea906Sjfb8856606 return -ENOMEM; 2023*d30ea906Sjfb8856606 } 2024*d30ea906Sjfb8856606 2025*d30ea906Sjfb8856606 if (!xstat_name) { 2026*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "xstat_name pointer is NULL\n"); 2027*d30ea906Sjfb8856606 return -ENOMEM; 2028*d30ea906Sjfb8856606 } 2029*d30ea906Sjfb8856606 2030*d30ea906Sjfb8856606 /* Get count */ 2031*d30ea906Sjfb8856606 cnt_xstats = rte_eth_xstats_get_names_by_id(port_id, NULL, 0, NULL); 2032*d30ea906Sjfb8856606 if (cnt_xstats < 0) { 2033*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Cannot get count of xstats\n"); 2034*d30ea906Sjfb8856606 return -ENODEV; 2035*d30ea906Sjfb8856606 } 2036*d30ea906Sjfb8856606 2037*d30ea906Sjfb8856606 /* Get id-name lookup table */ 2038*d30ea906Sjfb8856606 struct rte_eth_xstat_name xstats_names[cnt_xstats]; 2039*d30ea906Sjfb8856606 2040*d30ea906Sjfb8856606 if (cnt_xstats != rte_eth_xstats_get_names_by_id( 2041*d30ea906Sjfb8856606 port_id, xstats_names, cnt_xstats, NULL)) { 2042*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Cannot get xstats lookup\n"); 2043*d30ea906Sjfb8856606 return -1; 2044*d30ea906Sjfb8856606 } 2045*d30ea906Sjfb8856606 2046*d30ea906Sjfb8856606 for (idx_xstat = 0; idx_xstat < cnt_xstats; idx_xstat++) { 2047*d30ea906Sjfb8856606 if (!strcmp(xstats_names[idx_xstat].name, xstat_name)) { 2048*d30ea906Sjfb8856606 *id = idx_xstat; 2049*d30ea906Sjfb8856606 return 0; 2050*d30ea906Sjfb8856606 }; 2051*d30ea906Sjfb8856606 } 2052*d30ea906Sjfb8856606 2053*d30ea906Sjfb8856606 return -EINVAL; 2054*d30ea906Sjfb8856606 } 2055*d30ea906Sjfb8856606 2056*d30ea906Sjfb8856606 /* retrieve basic stats names */ 2057*d30ea906Sjfb8856606 static int 2058*d30ea906Sjfb8856606 rte_eth_basic_stats_get_names(struct rte_eth_dev *dev, 2059*d30ea906Sjfb8856606 struct rte_eth_xstat_name *xstats_names) 2060*d30ea906Sjfb8856606 { 2061*d30ea906Sjfb8856606 int cnt_used_entries = 0; 2062*d30ea906Sjfb8856606 uint32_t idx, id_queue; 2063*d30ea906Sjfb8856606 uint16_t num_q; 2064*d30ea906Sjfb8856606 2065*d30ea906Sjfb8856606 for (idx = 0; idx < RTE_NB_STATS; idx++) { 2066*d30ea906Sjfb8856606 snprintf(xstats_names[cnt_used_entries].name, 2067*d30ea906Sjfb8856606 sizeof(xstats_names[0].name), 2068*d30ea906Sjfb8856606 "%s", rte_stats_strings[idx].name); 2069*d30ea906Sjfb8856606 cnt_used_entries++; 2070*d30ea906Sjfb8856606 } 2071*d30ea906Sjfb8856606 num_q = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2072*d30ea906Sjfb8856606 for (id_queue = 0; id_queue < num_q; id_queue++) { 2073*d30ea906Sjfb8856606 for (idx = 0; idx < RTE_NB_RXQ_STATS; idx++) { 2074*d30ea906Sjfb8856606 snprintf(xstats_names[cnt_used_entries].name, 2075*d30ea906Sjfb8856606 sizeof(xstats_names[0].name), 2076*d30ea906Sjfb8856606 "rx_q%u%s", 2077*d30ea906Sjfb8856606 id_queue, rte_rxq_stats_strings[idx].name); 2078*d30ea906Sjfb8856606 cnt_used_entries++; 2079*d30ea906Sjfb8856606 } 2080*d30ea906Sjfb8856606 2081*d30ea906Sjfb8856606 } 2082*d30ea906Sjfb8856606 num_q = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2083*d30ea906Sjfb8856606 for (id_queue = 0; id_queue < num_q; id_queue++) { 2084*d30ea906Sjfb8856606 for (idx = 0; idx < RTE_NB_TXQ_STATS; idx++) { 2085*d30ea906Sjfb8856606 snprintf(xstats_names[cnt_used_entries].name, 2086*d30ea906Sjfb8856606 sizeof(xstats_names[0].name), 2087*d30ea906Sjfb8856606 "tx_q%u%s", 2088*d30ea906Sjfb8856606 id_queue, rte_txq_stats_strings[idx].name); 2089*d30ea906Sjfb8856606 cnt_used_entries++; 2090*d30ea906Sjfb8856606 } 2091*d30ea906Sjfb8856606 } 2092*d30ea906Sjfb8856606 return cnt_used_entries; 2093*d30ea906Sjfb8856606 } 2094*d30ea906Sjfb8856606 2095*d30ea906Sjfb8856606 /* retrieve ethdev extended statistics names */ 2096*d30ea906Sjfb8856606 int 2097*d30ea906Sjfb8856606 rte_eth_xstats_get_names_by_id(uint16_t port_id, 2098*d30ea906Sjfb8856606 struct rte_eth_xstat_name *xstats_names, unsigned int size, 2099*d30ea906Sjfb8856606 uint64_t *ids) 2100*d30ea906Sjfb8856606 { 2101*d30ea906Sjfb8856606 struct rte_eth_xstat_name *xstats_names_copy; 2102*d30ea906Sjfb8856606 unsigned int no_basic_stat_requested = 1; 2103*d30ea906Sjfb8856606 unsigned int no_ext_stat_requested = 1; 2104*d30ea906Sjfb8856606 unsigned int expected_entries; 2105*d30ea906Sjfb8856606 unsigned int basic_count; 2106*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2107*d30ea906Sjfb8856606 unsigned int i; 2108*d30ea906Sjfb8856606 int ret; 2109*d30ea906Sjfb8856606 2110*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2111*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2112*d30ea906Sjfb8856606 2113*d30ea906Sjfb8856606 basic_count = get_xstats_basic_count(dev); 2114*d30ea906Sjfb8856606 ret = get_xstats_count(port_id); 2115*d30ea906Sjfb8856606 if (ret < 0) 2116*d30ea906Sjfb8856606 return ret; 2117*d30ea906Sjfb8856606 expected_entries = (unsigned int)ret; 2118*d30ea906Sjfb8856606 2119*d30ea906Sjfb8856606 /* Return max number of stats if no ids given */ 2120*d30ea906Sjfb8856606 if (!ids) { 2121*d30ea906Sjfb8856606 if (!xstats_names) 2122*d30ea906Sjfb8856606 return expected_entries; 2123*d30ea906Sjfb8856606 else if (xstats_names && size < expected_entries) 2124*d30ea906Sjfb8856606 return expected_entries; 2125*d30ea906Sjfb8856606 } 2126*d30ea906Sjfb8856606 2127*d30ea906Sjfb8856606 if (ids && !xstats_names) 2128*d30ea906Sjfb8856606 return -EINVAL; 2129*d30ea906Sjfb8856606 2130*d30ea906Sjfb8856606 if (ids && dev->dev_ops->xstats_get_names_by_id != NULL && size > 0) { 2131*d30ea906Sjfb8856606 uint64_t ids_copy[size]; 2132*d30ea906Sjfb8856606 2133*d30ea906Sjfb8856606 for (i = 0; i < size; i++) { 2134*d30ea906Sjfb8856606 if (ids[i] < basic_count) { 2135*d30ea906Sjfb8856606 no_basic_stat_requested = 0; 2136*d30ea906Sjfb8856606 break; 2137*d30ea906Sjfb8856606 } 2138*d30ea906Sjfb8856606 2139*d30ea906Sjfb8856606 /* 2140*d30ea906Sjfb8856606 * Convert ids to xstats ids that PMD knows. 2141*d30ea906Sjfb8856606 * ids known by user are basic + extended stats. 2142*d30ea906Sjfb8856606 */ 2143*d30ea906Sjfb8856606 ids_copy[i] = ids[i] - basic_count; 2144*d30ea906Sjfb8856606 } 2145*d30ea906Sjfb8856606 2146*d30ea906Sjfb8856606 if (no_basic_stat_requested) 2147*d30ea906Sjfb8856606 return (*dev->dev_ops->xstats_get_names_by_id)(dev, 2148*d30ea906Sjfb8856606 xstats_names, ids_copy, size); 2149*d30ea906Sjfb8856606 } 2150*d30ea906Sjfb8856606 2151*d30ea906Sjfb8856606 /* Retrieve all stats */ 2152*d30ea906Sjfb8856606 if (!ids) { 2153*d30ea906Sjfb8856606 int num_stats = rte_eth_xstats_get_names(port_id, xstats_names, 2154*d30ea906Sjfb8856606 expected_entries); 2155*d30ea906Sjfb8856606 if (num_stats < 0 || num_stats > (int)expected_entries) 2156*d30ea906Sjfb8856606 return num_stats; 2157*d30ea906Sjfb8856606 else 2158*d30ea906Sjfb8856606 return expected_entries; 2159*d30ea906Sjfb8856606 } 2160*d30ea906Sjfb8856606 2161*d30ea906Sjfb8856606 xstats_names_copy = calloc(expected_entries, 2162*d30ea906Sjfb8856606 sizeof(struct rte_eth_xstat_name)); 2163*d30ea906Sjfb8856606 2164*d30ea906Sjfb8856606 if (!xstats_names_copy) { 2165*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Can't allocate memory\n"); 2166*d30ea906Sjfb8856606 return -ENOMEM; 2167*d30ea906Sjfb8856606 } 2168*d30ea906Sjfb8856606 2169*d30ea906Sjfb8856606 if (ids) { 2170*d30ea906Sjfb8856606 for (i = 0; i < size; i++) { 2171*d30ea906Sjfb8856606 if (ids[i] >= basic_count) { 2172*d30ea906Sjfb8856606 no_ext_stat_requested = 0; 2173*d30ea906Sjfb8856606 break; 2174*d30ea906Sjfb8856606 } 2175*d30ea906Sjfb8856606 } 2176*d30ea906Sjfb8856606 } 2177*d30ea906Sjfb8856606 2178*d30ea906Sjfb8856606 /* Fill xstats_names_copy structure */ 2179*d30ea906Sjfb8856606 if (ids && no_ext_stat_requested) { 2180*d30ea906Sjfb8856606 rte_eth_basic_stats_get_names(dev, xstats_names_copy); 2181*d30ea906Sjfb8856606 } else { 2182*d30ea906Sjfb8856606 ret = rte_eth_xstats_get_names(port_id, xstats_names_copy, 2183*d30ea906Sjfb8856606 expected_entries); 2184*d30ea906Sjfb8856606 if (ret < 0) { 2185*d30ea906Sjfb8856606 free(xstats_names_copy); 2186*d30ea906Sjfb8856606 return ret; 2187*d30ea906Sjfb8856606 } 2188*d30ea906Sjfb8856606 } 2189*d30ea906Sjfb8856606 2190*d30ea906Sjfb8856606 /* Filter stats */ 2191*d30ea906Sjfb8856606 for (i = 0; i < size; i++) { 2192*d30ea906Sjfb8856606 if (ids[i] >= expected_entries) { 2193*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n"); 2194*d30ea906Sjfb8856606 free(xstats_names_copy); 2195*d30ea906Sjfb8856606 return -1; 2196*d30ea906Sjfb8856606 } 2197*d30ea906Sjfb8856606 xstats_names[i] = xstats_names_copy[ids[i]]; 2198*d30ea906Sjfb8856606 } 2199*d30ea906Sjfb8856606 2200*d30ea906Sjfb8856606 free(xstats_names_copy); 2201*d30ea906Sjfb8856606 return size; 2202*d30ea906Sjfb8856606 } 2203*d30ea906Sjfb8856606 2204*d30ea906Sjfb8856606 int 2205*d30ea906Sjfb8856606 rte_eth_xstats_get_names(uint16_t port_id, 2206*d30ea906Sjfb8856606 struct rte_eth_xstat_name *xstats_names, 2207*d30ea906Sjfb8856606 unsigned int size) 2208*d30ea906Sjfb8856606 { 2209*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2210*d30ea906Sjfb8856606 int cnt_used_entries; 2211*d30ea906Sjfb8856606 int cnt_expected_entries; 2212*d30ea906Sjfb8856606 int cnt_driver_entries; 2213*d30ea906Sjfb8856606 2214*d30ea906Sjfb8856606 cnt_expected_entries = get_xstats_count(port_id); 2215*d30ea906Sjfb8856606 if (xstats_names == NULL || cnt_expected_entries < 0 || 2216*d30ea906Sjfb8856606 (int)size < cnt_expected_entries) 2217*d30ea906Sjfb8856606 return cnt_expected_entries; 2218*d30ea906Sjfb8856606 2219*d30ea906Sjfb8856606 /* port_id checked in get_xstats_count() */ 2220*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2221*d30ea906Sjfb8856606 2222*d30ea906Sjfb8856606 cnt_used_entries = rte_eth_basic_stats_get_names( 2223*d30ea906Sjfb8856606 dev, xstats_names); 2224*d30ea906Sjfb8856606 2225*d30ea906Sjfb8856606 if (dev->dev_ops->xstats_get_names != NULL) { 2226*d30ea906Sjfb8856606 /* If there are any driver-specific xstats, append them 2227*d30ea906Sjfb8856606 * to end of list. 2228*d30ea906Sjfb8856606 */ 2229*d30ea906Sjfb8856606 cnt_driver_entries = (*dev->dev_ops->xstats_get_names)( 2230*d30ea906Sjfb8856606 dev, 2231*d30ea906Sjfb8856606 xstats_names + cnt_used_entries, 2232*d30ea906Sjfb8856606 size - cnt_used_entries); 2233*d30ea906Sjfb8856606 if (cnt_driver_entries < 0) 2234*d30ea906Sjfb8856606 return eth_err(port_id, cnt_driver_entries); 2235*d30ea906Sjfb8856606 cnt_used_entries += cnt_driver_entries; 2236*d30ea906Sjfb8856606 } 2237*d30ea906Sjfb8856606 2238*d30ea906Sjfb8856606 return cnt_used_entries; 2239*d30ea906Sjfb8856606 } 2240*d30ea906Sjfb8856606 2241*d30ea906Sjfb8856606 2242*d30ea906Sjfb8856606 static int 2243*d30ea906Sjfb8856606 rte_eth_basic_stats_get(uint16_t port_id, struct rte_eth_xstat *xstats) 2244*d30ea906Sjfb8856606 { 2245*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2246*d30ea906Sjfb8856606 struct rte_eth_stats eth_stats; 2247*d30ea906Sjfb8856606 unsigned int count = 0, i, q; 2248*d30ea906Sjfb8856606 uint64_t val, *stats_ptr; 2249*d30ea906Sjfb8856606 uint16_t nb_rxqs, nb_txqs; 2250*d30ea906Sjfb8856606 int ret; 2251*d30ea906Sjfb8856606 2252*d30ea906Sjfb8856606 ret = rte_eth_stats_get(port_id, ð_stats); 2253*d30ea906Sjfb8856606 if (ret < 0) 2254*d30ea906Sjfb8856606 return ret; 2255*d30ea906Sjfb8856606 2256*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2257*d30ea906Sjfb8856606 2258*d30ea906Sjfb8856606 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2259*d30ea906Sjfb8856606 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2260*d30ea906Sjfb8856606 2261*d30ea906Sjfb8856606 /* global stats */ 2262*d30ea906Sjfb8856606 for (i = 0; i < RTE_NB_STATS; i++) { 2263*d30ea906Sjfb8856606 stats_ptr = RTE_PTR_ADD(ð_stats, 2264*d30ea906Sjfb8856606 rte_stats_strings[i].offset); 2265*d30ea906Sjfb8856606 val = *stats_ptr; 2266*d30ea906Sjfb8856606 xstats[count++].value = val; 2267*d30ea906Sjfb8856606 } 2268*d30ea906Sjfb8856606 2269*d30ea906Sjfb8856606 /* per-rxq stats */ 2270*d30ea906Sjfb8856606 for (q = 0; q < nb_rxqs; q++) { 2271*d30ea906Sjfb8856606 for (i = 0; i < RTE_NB_RXQ_STATS; i++) { 2272*d30ea906Sjfb8856606 stats_ptr = RTE_PTR_ADD(ð_stats, 2273*d30ea906Sjfb8856606 rte_rxq_stats_strings[i].offset + 2274*d30ea906Sjfb8856606 q * sizeof(uint64_t)); 2275*d30ea906Sjfb8856606 val = *stats_ptr; 2276*d30ea906Sjfb8856606 xstats[count++].value = val; 2277*d30ea906Sjfb8856606 } 2278*d30ea906Sjfb8856606 } 2279*d30ea906Sjfb8856606 2280*d30ea906Sjfb8856606 /* per-txq stats */ 2281*d30ea906Sjfb8856606 for (q = 0; q < nb_txqs; q++) { 2282*d30ea906Sjfb8856606 for (i = 0; i < RTE_NB_TXQ_STATS; i++) { 2283*d30ea906Sjfb8856606 stats_ptr = RTE_PTR_ADD(ð_stats, 2284*d30ea906Sjfb8856606 rte_txq_stats_strings[i].offset + 2285*d30ea906Sjfb8856606 q * sizeof(uint64_t)); 2286*d30ea906Sjfb8856606 val = *stats_ptr; 2287*d30ea906Sjfb8856606 xstats[count++].value = val; 2288*d30ea906Sjfb8856606 } 2289*d30ea906Sjfb8856606 } 2290*d30ea906Sjfb8856606 return count; 2291*d30ea906Sjfb8856606 } 2292*d30ea906Sjfb8856606 2293*d30ea906Sjfb8856606 /* retrieve ethdev extended statistics */ 2294*d30ea906Sjfb8856606 int 2295*d30ea906Sjfb8856606 rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids, 2296*d30ea906Sjfb8856606 uint64_t *values, unsigned int size) 2297*d30ea906Sjfb8856606 { 2298*d30ea906Sjfb8856606 unsigned int no_basic_stat_requested = 1; 2299*d30ea906Sjfb8856606 unsigned int no_ext_stat_requested = 1; 2300*d30ea906Sjfb8856606 unsigned int num_xstats_filled; 2301*d30ea906Sjfb8856606 unsigned int basic_count; 2302*d30ea906Sjfb8856606 uint16_t expected_entries; 2303*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2304*d30ea906Sjfb8856606 unsigned int i; 2305*d30ea906Sjfb8856606 int ret; 2306*d30ea906Sjfb8856606 2307*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2308*d30ea906Sjfb8856606 ret = get_xstats_count(port_id); 2309*d30ea906Sjfb8856606 if (ret < 0) 2310*d30ea906Sjfb8856606 return ret; 2311*d30ea906Sjfb8856606 expected_entries = (uint16_t)ret; 2312*d30ea906Sjfb8856606 struct rte_eth_xstat xstats[expected_entries]; 2313*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2314*d30ea906Sjfb8856606 basic_count = get_xstats_basic_count(dev); 2315*d30ea906Sjfb8856606 2316*d30ea906Sjfb8856606 /* Return max number of stats if no ids given */ 2317*d30ea906Sjfb8856606 if (!ids) { 2318*d30ea906Sjfb8856606 if (!values) 2319*d30ea906Sjfb8856606 return expected_entries; 2320*d30ea906Sjfb8856606 else if (values && size < expected_entries) 2321*d30ea906Sjfb8856606 return expected_entries; 2322*d30ea906Sjfb8856606 } 2323*d30ea906Sjfb8856606 2324*d30ea906Sjfb8856606 if (ids && !values) 2325*d30ea906Sjfb8856606 return -EINVAL; 2326*d30ea906Sjfb8856606 2327*d30ea906Sjfb8856606 if (ids && dev->dev_ops->xstats_get_by_id != NULL && size) { 2328*d30ea906Sjfb8856606 unsigned int basic_count = get_xstats_basic_count(dev); 2329*d30ea906Sjfb8856606 uint64_t ids_copy[size]; 2330*d30ea906Sjfb8856606 2331*d30ea906Sjfb8856606 for (i = 0; i < size; i++) { 2332*d30ea906Sjfb8856606 if (ids[i] < basic_count) { 2333*d30ea906Sjfb8856606 no_basic_stat_requested = 0; 2334*d30ea906Sjfb8856606 break; 2335*d30ea906Sjfb8856606 } 2336*d30ea906Sjfb8856606 2337*d30ea906Sjfb8856606 /* 2338*d30ea906Sjfb8856606 * Convert ids to xstats ids that PMD knows. 2339*d30ea906Sjfb8856606 * ids known by user are basic + extended stats. 2340*d30ea906Sjfb8856606 */ 2341*d30ea906Sjfb8856606 ids_copy[i] = ids[i] - basic_count; 2342*d30ea906Sjfb8856606 } 2343*d30ea906Sjfb8856606 2344*d30ea906Sjfb8856606 if (no_basic_stat_requested) 2345*d30ea906Sjfb8856606 return (*dev->dev_ops->xstats_get_by_id)(dev, ids_copy, 2346*d30ea906Sjfb8856606 values, size); 2347*d30ea906Sjfb8856606 } 2348*d30ea906Sjfb8856606 2349*d30ea906Sjfb8856606 if (ids) { 2350*d30ea906Sjfb8856606 for (i = 0; i < size; i++) { 2351*d30ea906Sjfb8856606 if (ids[i] >= basic_count) { 2352*d30ea906Sjfb8856606 no_ext_stat_requested = 0; 2353*d30ea906Sjfb8856606 break; 2354*d30ea906Sjfb8856606 } 2355*d30ea906Sjfb8856606 } 2356*d30ea906Sjfb8856606 } 2357*d30ea906Sjfb8856606 2358*d30ea906Sjfb8856606 /* Fill the xstats structure */ 2359*d30ea906Sjfb8856606 if (ids && no_ext_stat_requested) 2360*d30ea906Sjfb8856606 ret = rte_eth_basic_stats_get(port_id, xstats); 2361*d30ea906Sjfb8856606 else 2362*d30ea906Sjfb8856606 ret = rte_eth_xstats_get(port_id, xstats, expected_entries); 2363*d30ea906Sjfb8856606 2364*d30ea906Sjfb8856606 if (ret < 0) 2365*d30ea906Sjfb8856606 return ret; 2366*d30ea906Sjfb8856606 num_xstats_filled = (unsigned int)ret; 2367*d30ea906Sjfb8856606 2368*d30ea906Sjfb8856606 /* Return all stats */ 2369*d30ea906Sjfb8856606 if (!ids) { 2370*d30ea906Sjfb8856606 for (i = 0; i < num_xstats_filled; i++) 2371*d30ea906Sjfb8856606 values[i] = xstats[i].value; 2372*d30ea906Sjfb8856606 return expected_entries; 2373*d30ea906Sjfb8856606 } 2374*d30ea906Sjfb8856606 2375*d30ea906Sjfb8856606 /* Filter stats */ 2376*d30ea906Sjfb8856606 for (i = 0; i < size; i++) { 2377*d30ea906Sjfb8856606 if (ids[i] >= expected_entries) { 2378*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n"); 2379*d30ea906Sjfb8856606 return -1; 2380*d30ea906Sjfb8856606 } 2381*d30ea906Sjfb8856606 values[i] = xstats[ids[i]].value; 2382*d30ea906Sjfb8856606 } 2383*d30ea906Sjfb8856606 return size; 2384*d30ea906Sjfb8856606 } 2385*d30ea906Sjfb8856606 2386*d30ea906Sjfb8856606 int 2387*d30ea906Sjfb8856606 rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats, 2388*d30ea906Sjfb8856606 unsigned int n) 2389*d30ea906Sjfb8856606 { 2390*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2391*d30ea906Sjfb8856606 unsigned int count = 0, i; 2392*d30ea906Sjfb8856606 signed int xcount = 0; 2393*d30ea906Sjfb8856606 uint16_t nb_rxqs, nb_txqs; 2394*d30ea906Sjfb8856606 int ret; 2395*d30ea906Sjfb8856606 2396*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 2397*d30ea906Sjfb8856606 2398*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2399*d30ea906Sjfb8856606 2400*d30ea906Sjfb8856606 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2401*d30ea906Sjfb8856606 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS); 2402*d30ea906Sjfb8856606 2403*d30ea906Sjfb8856606 /* Return generic statistics */ 2404*d30ea906Sjfb8856606 count = RTE_NB_STATS + (nb_rxqs * RTE_NB_RXQ_STATS) + 2405*d30ea906Sjfb8856606 (nb_txqs * RTE_NB_TXQ_STATS); 2406*d30ea906Sjfb8856606 2407*d30ea906Sjfb8856606 /* implemented by the driver */ 2408*d30ea906Sjfb8856606 if (dev->dev_ops->xstats_get != NULL) { 2409*d30ea906Sjfb8856606 /* Retrieve the xstats from the driver at the end of the 2410*d30ea906Sjfb8856606 * xstats struct. 2411*d30ea906Sjfb8856606 */ 2412*d30ea906Sjfb8856606 xcount = (*dev->dev_ops->xstats_get)(dev, 2413*d30ea906Sjfb8856606 xstats ? xstats + count : NULL, 2414*d30ea906Sjfb8856606 (n > count) ? n - count : 0); 2415*d30ea906Sjfb8856606 2416*d30ea906Sjfb8856606 if (xcount < 0) 2417*d30ea906Sjfb8856606 return eth_err(port_id, xcount); 2418*d30ea906Sjfb8856606 } 2419*d30ea906Sjfb8856606 2420*d30ea906Sjfb8856606 if (n < count + xcount || xstats == NULL) 2421*d30ea906Sjfb8856606 return count + xcount; 2422*d30ea906Sjfb8856606 2423*d30ea906Sjfb8856606 /* now fill the xstats structure */ 2424*d30ea906Sjfb8856606 ret = rte_eth_basic_stats_get(port_id, xstats); 2425*d30ea906Sjfb8856606 if (ret < 0) 2426*d30ea906Sjfb8856606 return ret; 2427*d30ea906Sjfb8856606 count = ret; 2428*d30ea906Sjfb8856606 2429*d30ea906Sjfb8856606 for (i = 0; i < count; i++) 2430*d30ea906Sjfb8856606 xstats[i].id = i; 2431*d30ea906Sjfb8856606 /* add an offset to driver-specific stats */ 2432*d30ea906Sjfb8856606 for ( ; i < count + xcount; i++) 2433*d30ea906Sjfb8856606 xstats[i].id += count; 2434*d30ea906Sjfb8856606 2435*d30ea906Sjfb8856606 return count + xcount; 2436*d30ea906Sjfb8856606 } 2437*d30ea906Sjfb8856606 2438*d30ea906Sjfb8856606 /* reset ethdev extended statistics */ 2439*d30ea906Sjfb8856606 void 2440*d30ea906Sjfb8856606 rte_eth_xstats_reset(uint16_t port_id) 2441*d30ea906Sjfb8856606 { 2442*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2443*d30ea906Sjfb8856606 2444*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 2445*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2446*d30ea906Sjfb8856606 2447*d30ea906Sjfb8856606 /* implemented by the driver */ 2448*d30ea906Sjfb8856606 if (dev->dev_ops->xstats_reset != NULL) { 2449*d30ea906Sjfb8856606 (*dev->dev_ops->xstats_reset)(dev); 2450*d30ea906Sjfb8856606 return; 2451*d30ea906Sjfb8856606 } 2452*d30ea906Sjfb8856606 2453*d30ea906Sjfb8856606 /* fallback to default */ 2454*d30ea906Sjfb8856606 rte_eth_stats_reset(port_id); 2455*d30ea906Sjfb8856606 } 2456*d30ea906Sjfb8856606 2457*d30ea906Sjfb8856606 static int 2458*d30ea906Sjfb8856606 set_queue_stats_mapping(uint16_t port_id, uint16_t queue_id, uint8_t stat_idx, 2459*d30ea906Sjfb8856606 uint8_t is_rx) 2460*d30ea906Sjfb8856606 { 2461*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2462*d30ea906Sjfb8856606 2463*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2464*d30ea906Sjfb8856606 2465*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2466*d30ea906Sjfb8856606 2467*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->queue_stats_mapping_set, -ENOTSUP); 2468*d30ea906Sjfb8856606 2469*d30ea906Sjfb8856606 if (is_rx && (queue_id >= dev->data->nb_rx_queues)) 2470*d30ea906Sjfb8856606 return -EINVAL; 2471*d30ea906Sjfb8856606 2472*d30ea906Sjfb8856606 if (!is_rx && (queue_id >= dev->data->nb_tx_queues)) 2473*d30ea906Sjfb8856606 return -EINVAL; 2474*d30ea906Sjfb8856606 2475*d30ea906Sjfb8856606 if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) 2476*d30ea906Sjfb8856606 return -EINVAL; 2477*d30ea906Sjfb8856606 2478*d30ea906Sjfb8856606 return (*dev->dev_ops->queue_stats_mapping_set) 2479*d30ea906Sjfb8856606 (dev, queue_id, stat_idx, is_rx); 2480*d30ea906Sjfb8856606 } 2481*d30ea906Sjfb8856606 2482*d30ea906Sjfb8856606 2483*d30ea906Sjfb8856606 int 2484*d30ea906Sjfb8856606 rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id, 2485*d30ea906Sjfb8856606 uint8_t stat_idx) 2486*d30ea906Sjfb8856606 { 2487*d30ea906Sjfb8856606 return eth_err(port_id, set_queue_stats_mapping(port_id, tx_queue_id, 2488*d30ea906Sjfb8856606 stat_idx, STAT_QMAP_TX)); 2489*d30ea906Sjfb8856606 } 2490*d30ea906Sjfb8856606 2491*d30ea906Sjfb8856606 2492*d30ea906Sjfb8856606 int 2493*d30ea906Sjfb8856606 rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id, 2494*d30ea906Sjfb8856606 uint8_t stat_idx) 2495*d30ea906Sjfb8856606 { 2496*d30ea906Sjfb8856606 return eth_err(port_id, set_queue_stats_mapping(port_id, rx_queue_id, 2497*d30ea906Sjfb8856606 stat_idx, STAT_QMAP_RX)); 2498*d30ea906Sjfb8856606 } 2499*d30ea906Sjfb8856606 2500*d30ea906Sjfb8856606 int 2501*d30ea906Sjfb8856606 rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size) 2502*d30ea906Sjfb8856606 { 2503*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2504*d30ea906Sjfb8856606 2505*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2506*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2507*d30ea906Sjfb8856606 2508*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fw_version_get, -ENOTSUP); 2509*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->fw_version_get)(dev, 2510*d30ea906Sjfb8856606 fw_version, fw_size)); 2511*d30ea906Sjfb8856606 } 2512*d30ea906Sjfb8856606 2513*d30ea906Sjfb8856606 void 2514*d30ea906Sjfb8856606 rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info) 2515*d30ea906Sjfb8856606 { 2516*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2517*d30ea906Sjfb8856606 const struct rte_eth_desc_lim lim = { 2518*d30ea906Sjfb8856606 .nb_max = UINT16_MAX, 2519*d30ea906Sjfb8856606 .nb_min = 0, 2520*d30ea906Sjfb8856606 .nb_align = 1, 2521*d30ea906Sjfb8856606 }; 2522*d30ea906Sjfb8856606 2523*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 2524*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2525*d30ea906Sjfb8856606 2526*d30ea906Sjfb8856606 memset(dev_info, 0, sizeof(struct rte_eth_dev_info)); 2527*d30ea906Sjfb8856606 dev_info->rx_desc_lim = lim; 2528*d30ea906Sjfb8856606 dev_info->tx_desc_lim = lim; 2529*d30ea906Sjfb8856606 dev_info->device = dev->device; 2530*d30ea906Sjfb8856606 2531*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_infos_get); 2532*d30ea906Sjfb8856606 (*dev->dev_ops->dev_infos_get)(dev, dev_info); 2533*d30ea906Sjfb8856606 dev_info->driver_name = dev->device->driver->name; 2534*d30ea906Sjfb8856606 dev_info->nb_rx_queues = dev->data->nb_rx_queues; 2535*d30ea906Sjfb8856606 dev_info->nb_tx_queues = dev->data->nb_tx_queues; 2536*d30ea906Sjfb8856606 2537*d30ea906Sjfb8856606 dev_info->dev_flags = &dev->data->dev_flags; 2538*d30ea906Sjfb8856606 } 2539*d30ea906Sjfb8856606 2540*d30ea906Sjfb8856606 int 2541*d30ea906Sjfb8856606 rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask, 2542*d30ea906Sjfb8856606 uint32_t *ptypes, int num) 2543*d30ea906Sjfb8856606 { 2544*d30ea906Sjfb8856606 int i, j; 2545*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2546*d30ea906Sjfb8856606 const uint32_t *all_ptypes; 2547*d30ea906Sjfb8856606 2548*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2549*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2550*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_supported_ptypes_get, 0); 2551*d30ea906Sjfb8856606 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev); 2552*d30ea906Sjfb8856606 2553*d30ea906Sjfb8856606 if (!all_ptypes) 2554*d30ea906Sjfb8856606 return 0; 2555*d30ea906Sjfb8856606 2556*d30ea906Sjfb8856606 for (i = 0, j = 0; all_ptypes[i] != RTE_PTYPE_UNKNOWN; ++i) 2557*d30ea906Sjfb8856606 if (all_ptypes[i] & ptype_mask) { 2558*d30ea906Sjfb8856606 if (j < num) 2559*d30ea906Sjfb8856606 ptypes[j] = all_ptypes[i]; 2560*d30ea906Sjfb8856606 j++; 2561*d30ea906Sjfb8856606 } 2562*d30ea906Sjfb8856606 2563*d30ea906Sjfb8856606 return j; 2564*d30ea906Sjfb8856606 } 2565*d30ea906Sjfb8856606 2566*d30ea906Sjfb8856606 void 2567*d30ea906Sjfb8856606 rte_eth_macaddr_get(uint16_t port_id, struct ether_addr *mac_addr) 2568*d30ea906Sjfb8856606 { 2569*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2570*d30ea906Sjfb8856606 2571*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_RET(port_id); 2572*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2573*d30ea906Sjfb8856606 ether_addr_copy(&dev->data->mac_addrs[0], mac_addr); 2574*d30ea906Sjfb8856606 } 2575*d30ea906Sjfb8856606 2576*d30ea906Sjfb8856606 2577*d30ea906Sjfb8856606 int 2578*d30ea906Sjfb8856606 rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu) 2579*d30ea906Sjfb8856606 { 2580*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2581*d30ea906Sjfb8856606 2582*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2583*d30ea906Sjfb8856606 2584*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2585*d30ea906Sjfb8856606 *mtu = dev->data->mtu; 2586*d30ea906Sjfb8856606 return 0; 2587*d30ea906Sjfb8856606 } 2588*d30ea906Sjfb8856606 2589*d30ea906Sjfb8856606 int 2590*d30ea906Sjfb8856606 rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu) 2591*d30ea906Sjfb8856606 { 2592*d30ea906Sjfb8856606 int ret; 2593*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2594*d30ea906Sjfb8856606 2595*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2596*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2597*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mtu_set, -ENOTSUP); 2598*d30ea906Sjfb8856606 2599*d30ea906Sjfb8856606 ret = (*dev->dev_ops->mtu_set)(dev, mtu); 2600*d30ea906Sjfb8856606 if (!ret) 2601*d30ea906Sjfb8856606 dev->data->mtu = mtu; 2602*d30ea906Sjfb8856606 2603*d30ea906Sjfb8856606 return eth_err(port_id, ret); 2604*d30ea906Sjfb8856606 } 2605*d30ea906Sjfb8856606 2606*d30ea906Sjfb8856606 int 2607*d30ea906Sjfb8856606 rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on) 2608*d30ea906Sjfb8856606 { 2609*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2610*d30ea906Sjfb8856606 int ret; 2611*d30ea906Sjfb8856606 2612*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2613*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2614*d30ea906Sjfb8856606 if (!(dev->data->dev_conf.rxmode.offloads & 2615*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_FILTER)) { 2616*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port %u: vlan-filtering disabled\n", 2617*d30ea906Sjfb8856606 port_id); 2618*d30ea906Sjfb8856606 return -ENOSYS; 2619*d30ea906Sjfb8856606 } 2620*d30ea906Sjfb8856606 2621*d30ea906Sjfb8856606 if (vlan_id > 4095) { 2622*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port_id=%u invalid vlan_id=%u > 4095\n", 2623*d30ea906Sjfb8856606 port_id, vlan_id); 2624*d30ea906Sjfb8856606 return -EINVAL; 2625*d30ea906Sjfb8856606 } 2626*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_filter_set, -ENOTSUP); 2627*d30ea906Sjfb8856606 2628*d30ea906Sjfb8856606 ret = (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on); 2629*d30ea906Sjfb8856606 if (ret == 0) { 2630*d30ea906Sjfb8856606 struct rte_vlan_filter_conf *vfc; 2631*d30ea906Sjfb8856606 int vidx; 2632*d30ea906Sjfb8856606 int vbit; 2633*d30ea906Sjfb8856606 2634*d30ea906Sjfb8856606 vfc = &dev->data->vlan_filter_conf; 2635*d30ea906Sjfb8856606 vidx = vlan_id / 64; 2636*d30ea906Sjfb8856606 vbit = vlan_id % 64; 2637*d30ea906Sjfb8856606 2638*d30ea906Sjfb8856606 if (on) 2639*d30ea906Sjfb8856606 vfc->ids[vidx] |= UINT64_C(1) << vbit; 2640*d30ea906Sjfb8856606 else 2641*d30ea906Sjfb8856606 vfc->ids[vidx] &= ~(UINT64_C(1) << vbit); 2642*d30ea906Sjfb8856606 } 2643*d30ea906Sjfb8856606 2644*d30ea906Sjfb8856606 return eth_err(port_id, ret); 2645*d30ea906Sjfb8856606 } 2646*d30ea906Sjfb8856606 2647*d30ea906Sjfb8856606 int 2648*d30ea906Sjfb8856606 rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id, 2649*d30ea906Sjfb8856606 int on) 2650*d30ea906Sjfb8856606 { 2651*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2652*d30ea906Sjfb8856606 2653*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2654*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2655*d30ea906Sjfb8856606 if (rx_queue_id >= dev->data->nb_rx_queues) { 2656*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid rx_queue_id=%u\n", rx_queue_id); 2657*d30ea906Sjfb8856606 return -EINVAL; 2658*d30ea906Sjfb8856606 } 2659*d30ea906Sjfb8856606 2660*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP); 2661*d30ea906Sjfb8856606 (*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on); 2662*d30ea906Sjfb8856606 2663*d30ea906Sjfb8856606 return 0; 2664*d30ea906Sjfb8856606 } 2665*d30ea906Sjfb8856606 2666*d30ea906Sjfb8856606 int 2667*d30ea906Sjfb8856606 rte_eth_dev_set_vlan_ether_type(uint16_t port_id, 2668*d30ea906Sjfb8856606 enum rte_vlan_type vlan_type, 2669*d30ea906Sjfb8856606 uint16_t tpid) 2670*d30ea906Sjfb8856606 { 2671*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2672*d30ea906Sjfb8856606 2673*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2674*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2675*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_tpid_set, -ENOTSUP); 2676*d30ea906Sjfb8856606 2677*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type, 2678*d30ea906Sjfb8856606 tpid)); 2679*d30ea906Sjfb8856606 } 2680*d30ea906Sjfb8856606 2681*d30ea906Sjfb8856606 int 2682*d30ea906Sjfb8856606 rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask) 2683*d30ea906Sjfb8856606 { 2684*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2685*d30ea906Sjfb8856606 int ret = 0; 2686*d30ea906Sjfb8856606 int mask = 0; 2687*d30ea906Sjfb8856606 int cur, org = 0; 2688*d30ea906Sjfb8856606 uint64_t orig_offloads; 2689*d30ea906Sjfb8856606 2690*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2691*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2692*d30ea906Sjfb8856606 2693*d30ea906Sjfb8856606 /* save original values in case of failure */ 2694*d30ea906Sjfb8856606 orig_offloads = dev->data->dev_conf.rxmode.offloads; 2695*d30ea906Sjfb8856606 2696*d30ea906Sjfb8856606 /*check which option changed by application*/ 2697*d30ea906Sjfb8856606 cur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD); 2698*d30ea906Sjfb8856606 org = !!(dev->data->dev_conf.rxmode.offloads & 2699*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_STRIP); 2700*d30ea906Sjfb8856606 if (cur != org) { 2701*d30ea906Sjfb8856606 if (cur) 2702*d30ea906Sjfb8856606 dev->data->dev_conf.rxmode.offloads |= 2703*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_STRIP; 2704*d30ea906Sjfb8856606 else 2705*d30ea906Sjfb8856606 dev->data->dev_conf.rxmode.offloads &= 2706*d30ea906Sjfb8856606 ~DEV_RX_OFFLOAD_VLAN_STRIP; 2707*d30ea906Sjfb8856606 mask |= ETH_VLAN_STRIP_MASK; 2708*d30ea906Sjfb8856606 } 2709*d30ea906Sjfb8856606 2710*d30ea906Sjfb8856606 cur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD); 2711*d30ea906Sjfb8856606 org = !!(dev->data->dev_conf.rxmode.offloads & 2712*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_FILTER); 2713*d30ea906Sjfb8856606 if (cur != org) { 2714*d30ea906Sjfb8856606 if (cur) 2715*d30ea906Sjfb8856606 dev->data->dev_conf.rxmode.offloads |= 2716*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_FILTER; 2717*d30ea906Sjfb8856606 else 2718*d30ea906Sjfb8856606 dev->data->dev_conf.rxmode.offloads &= 2719*d30ea906Sjfb8856606 ~DEV_RX_OFFLOAD_VLAN_FILTER; 2720*d30ea906Sjfb8856606 mask |= ETH_VLAN_FILTER_MASK; 2721*d30ea906Sjfb8856606 } 2722*d30ea906Sjfb8856606 2723*d30ea906Sjfb8856606 cur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD); 2724*d30ea906Sjfb8856606 org = !!(dev->data->dev_conf.rxmode.offloads & 2725*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_EXTEND); 2726*d30ea906Sjfb8856606 if (cur != org) { 2727*d30ea906Sjfb8856606 if (cur) 2728*d30ea906Sjfb8856606 dev->data->dev_conf.rxmode.offloads |= 2729*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_EXTEND; 2730*d30ea906Sjfb8856606 else 2731*d30ea906Sjfb8856606 dev->data->dev_conf.rxmode.offloads &= 2732*d30ea906Sjfb8856606 ~DEV_RX_OFFLOAD_VLAN_EXTEND; 2733*d30ea906Sjfb8856606 mask |= ETH_VLAN_EXTEND_MASK; 2734*d30ea906Sjfb8856606 } 2735*d30ea906Sjfb8856606 2736*d30ea906Sjfb8856606 /*no change*/ 2737*d30ea906Sjfb8856606 if (mask == 0) 2738*d30ea906Sjfb8856606 return ret; 2739*d30ea906Sjfb8856606 2740*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_offload_set, -ENOTSUP); 2741*d30ea906Sjfb8856606 ret = (*dev->dev_ops->vlan_offload_set)(dev, mask); 2742*d30ea906Sjfb8856606 if (ret) { 2743*d30ea906Sjfb8856606 /* hit an error restore original values */ 2744*d30ea906Sjfb8856606 dev->data->dev_conf.rxmode.offloads = orig_offloads; 2745*d30ea906Sjfb8856606 } 2746*d30ea906Sjfb8856606 2747*d30ea906Sjfb8856606 return eth_err(port_id, ret); 2748*d30ea906Sjfb8856606 } 2749*d30ea906Sjfb8856606 2750*d30ea906Sjfb8856606 int 2751*d30ea906Sjfb8856606 rte_eth_dev_get_vlan_offload(uint16_t port_id) 2752*d30ea906Sjfb8856606 { 2753*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2754*d30ea906Sjfb8856606 int ret = 0; 2755*d30ea906Sjfb8856606 2756*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2757*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2758*d30ea906Sjfb8856606 2759*d30ea906Sjfb8856606 if (dev->data->dev_conf.rxmode.offloads & 2760*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_STRIP) 2761*d30ea906Sjfb8856606 ret |= ETH_VLAN_STRIP_OFFLOAD; 2762*d30ea906Sjfb8856606 2763*d30ea906Sjfb8856606 if (dev->data->dev_conf.rxmode.offloads & 2764*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_FILTER) 2765*d30ea906Sjfb8856606 ret |= ETH_VLAN_FILTER_OFFLOAD; 2766*d30ea906Sjfb8856606 2767*d30ea906Sjfb8856606 if (dev->data->dev_conf.rxmode.offloads & 2768*d30ea906Sjfb8856606 DEV_RX_OFFLOAD_VLAN_EXTEND) 2769*d30ea906Sjfb8856606 ret |= ETH_VLAN_EXTEND_OFFLOAD; 2770*d30ea906Sjfb8856606 2771*d30ea906Sjfb8856606 return ret; 2772*d30ea906Sjfb8856606 } 2773*d30ea906Sjfb8856606 2774*d30ea906Sjfb8856606 int 2775*d30ea906Sjfb8856606 rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on) 2776*d30ea906Sjfb8856606 { 2777*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2778*d30ea906Sjfb8856606 2779*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2780*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2781*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP); 2782*d30ea906Sjfb8856606 2783*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on)); 2784*d30ea906Sjfb8856606 } 2785*d30ea906Sjfb8856606 2786*d30ea906Sjfb8856606 int 2787*d30ea906Sjfb8856606 rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf) 2788*d30ea906Sjfb8856606 { 2789*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2790*d30ea906Sjfb8856606 2791*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2792*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2793*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_get, -ENOTSUP); 2794*d30ea906Sjfb8856606 memset(fc_conf, 0, sizeof(*fc_conf)); 2795*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf)); 2796*d30ea906Sjfb8856606 } 2797*d30ea906Sjfb8856606 2798*d30ea906Sjfb8856606 int 2799*d30ea906Sjfb8856606 rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf) 2800*d30ea906Sjfb8856606 { 2801*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2802*d30ea906Sjfb8856606 2803*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2804*d30ea906Sjfb8856606 if ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) { 2805*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid send_xon, only 0/1 allowed\n"); 2806*d30ea906Sjfb8856606 return -EINVAL; 2807*d30ea906Sjfb8856606 } 2808*d30ea906Sjfb8856606 2809*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2810*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_set, -ENOTSUP); 2811*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf)); 2812*d30ea906Sjfb8856606 } 2813*d30ea906Sjfb8856606 2814*d30ea906Sjfb8856606 int 2815*d30ea906Sjfb8856606 rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id, 2816*d30ea906Sjfb8856606 struct rte_eth_pfc_conf *pfc_conf) 2817*d30ea906Sjfb8856606 { 2818*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2819*d30ea906Sjfb8856606 2820*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2821*d30ea906Sjfb8856606 if (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) { 2822*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid priority, only 0-7 allowed\n"); 2823*d30ea906Sjfb8856606 return -EINVAL; 2824*d30ea906Sjfb8856606 } 2825*d30ea906Sjfb8856606 2826*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2827*d30ea906Sjfb8856606 /* High water, low water validation are device specific */ 2828*d30ea906Sjfb8856606 if (*dev->dev_ops->priority_flow_ctrl_set) 2829*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set) 2830*d30ea906Sjfb8856606 (dev, pfc_conf)); 2831*d30ea906Sjfb8856606 return -ENOTSUP; 2832*d30ea906Sjfb8856606 } 2833*d30ea906Sjfb8856606 2834*d30ea906Sjfb8856606 static int 2835*d30ea906Sjfb8856606 rte_eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf, 2836*d30ea906Sjfb8856606 uint16_t reta_size) 2837*d30ea906Sjfb8856606 { 2838*d30ea906Sjfb8856606 uint16_t i, num; 2839*d30ea906Sjfb8856606 2840*d30ea906Sjfb8856606 if (!reta_conf) 2841*d30ea906Sjfb8856606 return -EINVAL; 2842*d30ea906Sjfb8856606 2843*d30ea906Sjfb8856606 num = (reta_size + RTE_RETA_GROUP_SIZE - 1) / RTE_RETA_GROUP_SIZE; 2844*d30ea906Sjfb8856606 for (i = 0; i < num; i++) { 2845*d30ea906Sjfb8856606 if (reta_conf[i].mask) 2846*d30ea906Sjfb8856606 return 0; 2847*d30ea906Sjfb8856606 } 2848*d30ea906Sjfb8856606 2849*d30ea906Sjfb8856606 return -EINVAL; 2850*d30ea906Sjfb8856606 } 2851*d30ea906Sjfb8856606 2852*d30ea906Sjfb8856606 static int 2853*d30ea906Sjfb8856606 rte_eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf, 2854*d30ea906Sjfb8856606 uint16_t reta_size, 2855*d30ea906Sjfb8856606 uint16_t max_rxq) 2856*d30ea906Sjfb8856606 { 2857*d30ea906Sjfb8856606 uint16_t i, idx, shift; 2858*d30ea906Sjfb8856606 2859*d30ea906Sjfb8856606 if (!reta_conf) 2860*d30ea906Sjfb8856606 return -EINVAL; 2861*d30ea906Sjfb8856606 2862*d30ea906Sjfb8856606 if (max_rxq == 0) { 2863*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "No receive queue is available\n"); 2864*d30ea906Sjfb8856606 return -EINVAL; 2865*d30ea906Sjfb8856606 } 2866*d30ea906Sjfb8856606 2867*d30ea906Sjfb8856606 for (i = 0; i < reta_size; i++) { 2868*d30ea906Sjfb8856606 idx = i / RTE_RETA_GROUP_SIZE; 2869*d30ea906Sjfb8856606 shift = i % RTE_RETA_GROUP_SIZE; 2870*d30ea906Sjfb8856606 if ((reta_conf[idx].mask & (1ULL << shift)) && 2871*d30ea906Sjfb8856606 (reta_conf[idx].reta[shift] >= max_rxq)) { 2872*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 2873*d30ea906Sjfb8856606 "reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u\n", 2874*d30ea906Sjfb8856606 idx, shift, 2875*d30ea906Sjfb8856606 reta_conf[idx].reta[shift], max_rxq); 2876*d30ea906Sjfb8856606 return -EINVAL; 2877*d30ea906Sjfb8856606 } 2878*d30ea906Sjfb8856606 } 2879*d30ea906Sjfb8856606 2880*d30ea906Sjfb8856606 return 0; 2881*d30ea906Sjfb8856606 } 2882*d30ea906Sjfb8856606 2883*d30ea906Sjfb8856606 int 2884*d30ea906Sjfb8856606 rte_eth_dev_rss_reta_update(uint16_t port_id, 2885*d30ea906Sjfb8856606 struct rte_eth_rss_reta_entry64 *reta_conf, 2886*d30ea906Sjfb8856606 uint16_t reta_size) 2887*d30ea906Sjfb8856606 { 2888*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2889*d30ea906Sjfb8856606 int ret; 2890*d30ea906Sjfb8856606 2891*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2892*d30ea906Sjfb8856606 /* Check mask bits */ 2893*d30ea906Sjfb8856606 ret = rte_eth_check_reta_mask(reta_conf, reta_size); 2894*d30ea906Sjfb8856606 if (ret < 0) 2895*d30ea906Sjfb8856606 return ret; 2896*d30ea906Sjfb8856606 2897*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2898*d30ea906Sjfb8856606 2899*d30ea906Sjfb8856606 /* Check entry value */ 2900*d30ea906Sjfb8856606 ret = rte_eth_check_reta_entry(reta_conf, reta_size, 2901*d30ea906Sjfb8856606 dev->data->nb_rx_queues); 2902*d30ea906Sjfb8856606 if (ret < 0) 2903*d30ea906Sjfb8856606 return ret; 2904*d30ea906Sjfb8856606 2905*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP); 2906*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf, 2907*d30ea906Sjfb8856606 reta_size)); 2908*d30ea906Sjfb8856606 } 2909*d30ea906Sjfb8856606 2910*d30ea906Sjfb8856606 int 2911*d30ea906Sjfb8856606 rte_eth_dev_rss_reta_query(uint16_t port_id, 2912*d30ea906Sjfb8856606 struct rte_eth_rss_reta_entry64 *reta_conf, 2913*d30ea906Sjfb8856606 uint16_t reta_size) 2914*d30ea906Sjfb8856606 { 2915*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2916*d30ea906Sjfb8856606 int ret; 2917*d30ea906Sjfb8856606 2918*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2919*d30ea906Sjfb8856606 2920*d30ea906Sjfb8856606 /* Check mask bits */ 2921*d30ea906Sjfb8856606 ret = rte_eth_check_reta_mask(reta_conf, reta_size); 2922*d30ea906Sjfb8856606 if (ret < 0) 2923*d30ea906Sjfb8856606 return ret; 2924*d30ea906Sjfb8856606 2925*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2926*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP); 2927*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf, 2928*d30ea906Sjfb8856606 reta_size)); 2929*d30ea906Sjfb8856606 } 2930*d30ea906Sjfb8856606 2931*d30ea906Sjfb8856606 int 2932*d30ea906Sjfb8856606 rte_eth_dev_rss_hash_update(uint16_t port_id, 2933*d30ea906Sjfb8856606 struct rte_eth_rss_conf *rss_conf) 2934*d30ea906Sjfb8856606 { 2935*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2936*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, }; 2937*d30ea906Sjfb8856606 2938*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2939*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2940*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 2941*d30ea906Sjfb8856606 if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) != 2942*d30ea906Sjfb8856606 dev_info.flow_type_rss_offloads) { 2943*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 2944*d30ea906Sjfb8856606 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n", 2945*d30ea906Sjfb8856606 port_id, rss_conf->rss_hf, 2946*d30ea906Sjfb8856606 dev_info.flow_type_rss_offloads); 2947*d30ea906Sjfb8856606 return -EINVAL; 2948*d30ea906Sjfb8856606 } 2949*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_update, -ENOTSUP); 2950*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev, 2951*d30ea906Sjfb8856606 rss_conf)); 2952*d30ea906Sjfb8856606 } 2953*d30ea906Sjfb8856606 2954*d30ea906Sjfb8856606 int 2955*d30ea906Sjfb8856606 rte_eth_dev_rss_hash_conf_get(uint16_t port_id, 2956*d30ea906Sjfb8856606 struct rte_eth_rss_conf *rss_conf) 2957*d30ea906Sjfb8856606 { 2958*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2959*d30ea906Sjfb8856606 2960*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2961*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2962*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_conf_get, -ENOTSUP); 2963*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev, 2964*d30ea906Sjfb8856606 rss_conf)); 2965*d30ea906Sjfb8856606 } 2966*d30ea906Sjfb8856606 2967*d30ea906Sjfb8856606 int 2968*d30ea906Sjfb8856606 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id, 2969*d30ea906Sjfb8856606 struct rte_eth_udp_tunnel *udp_tunnel) 2970*d30ea906Sjfb8856606 { 2971*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2972*d30ea906Sjfb8856606 2973*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2974*d30ea906Sjfb8856606 if (udp_tunnel == NULL) { 2975*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n"); 2976*d30ea906Sjfb8856606 return -EINVAL; 2977*d30ea906Sjfb8856606 } 2978*d30ea906Sjfb8856606 2979*d30ea906Sjfb8856606 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) { 2980*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 2981*d30ea906Sjfb8856606 return -EINVAL; 2982*d30ea906Sjfb8856606 } 2983*d30ea906Sjfb8856606 2984*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2985*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_add, -ENOTSUP); 2986*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev, 2987*d30ea906Sjfb8856606 udp_tunnel)); 2988*d30ea906Sjfb8856606 } 2989*d30ea906Sjfb8856606 2990*d30ea906Sjfb8856606 int 2991*d30ea906Sjfb8856606 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id, 2992*d30ea906Sjfb8856606 struct rte_eth_udp_tunnel *udp_tunnel) 2993*d30ea906Sjfb8856606 { 2994*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 2995*d30ea906Sjfb8856606 2996*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 2997*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 2998*d30ea906Sjfb8856606 2999*d30ea906Sjfb8856606 if (udp_tunnel == NULL) { 3000*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n"); 3001*d30ea906Sjfb8856606 return -EINVAL; 3002*d30ea906Sjfb8856606 } 3003*d30ea906Sjfb8856606 3004*d30ea906Sjfb8856606 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) { 3005*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 3006*d30ea906Sjfb8856606 return -EINVAL; 3007*d30ea906Sjfb8856606 } 3008*d30ea906Sjfb8856606 3009*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_del, -ENOTSUP); 3010*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev, 3011*d30ea906Sjfb8856606 udp_tunnel)); 3012*d30ea906Sjfb8856606 } 3013*d30ea906Sjfb8856606 3014*d30ea906Sjfb8856606 int 3015*d30ea906Sjfb8856606 rte_eth_led_on(uint16_t port_id) 3016*d30ea906Sjfb8856606 { 3017*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3018*d30ea906Sjfb8856606 3019*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3020*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3021*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_on, -ENOTSUP); 3022*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev)); 3023*d30ea906Sjfb8856606 } 3024*d30ea906Sjfb8856606 3025*d30ea906Sjfb8856606 int 3026*d30ea906Sjfb8856606 rte_eth_led_off(uint16_t port_id) 3027*d30ea906Sjfb8856606 { 3028*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3029*d30ea906Sjfb8856606 3030*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3031*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3032*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_off, -ENOTSUP); 3033*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev)); 3034*d30ea906Sjfb8856606 } 3035*d30ea906Sjfb8856606 3036*d30ea906Sjfb8856606 /* 3037*d30ea906Sjfb8856606 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find 3038*d30ea906Sjfb8856606 * an empty spot. 3039*d30ea906Sjfb8856606 */ 3040*d30ea906Sjfb8856606 static int 3041*d30ea906Sjfb8856606 get_mac_addr_index(uint16_t port_id, const struct ether_addr *addr) 3042*d30ea906Sjfb8856606 { 3043*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info; 3044*d30ea906Sjfb8856606 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3045*d30ea906Sjfb8856606 unsigned i; 3046*d30ea906Sjfb8856606 3047*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3048*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 3049*d30ea906Sjfb8856606 3050*d30ea906Sjfb8856606 for (i = 0; i < dev_info.max_mac_addrs; i++) 3051*d30ea906Sjfb8856606 if (memcmp(addr, &dev->data->mac_addrs[i], ETHER_ADDR_LEN) == 0) 3052*d30ea906Sjfb8856606 return i; 3053*d30ea906Sjfb8856606 3054*d30ea906Sjfb8856606 return -1; 3055*d30ea906Sjfb8856606 } 3056*d30ea906Sjfb8856606 3057*d30ea906Sjfb8856606 static const struct ether_addr null_mac_addr; 3058*d30ea906Sjfb8856606 3059*d30ea906Sjfb8856606 int 3060*d30ea906Sjfb8856606 rte_eth_dev_mac_addr_add(uint16_t port_id, struct ether_addr *addr, 3061*d30ea906Sjfb8856606 uint32_t pool) 3062*d30ea906Sjfb8856606 { 3063*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3064*d30ea906Sjfb8856606 int index; 3065*d30ea906Sjfb8856606 uint64_t pool_mask; 3066*d30ea906Sjfb8856606 int ret; 3067*d30ea906Sjfb8856606 3068*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3069*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3070*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_add, -ENOTSUP); 3071*d30ea906Sjfb8856606 3072*d30ea906Sjfb8856606 if (is_zero_ether_addr(addr)) { 3073*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n", 3074*d30ea906Sjfb8856606 port_id); 3075*d30ea906Sjfb8856606 return -EINVAL; 3076*d30ea906Sjfb8856606 } 3077*d30ea906Sjfb8856606 if (pool >= ETH_64_POOLS) { 3078*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Pool id must be 0-%d\n", ETH_64_POOLS - 1); 3079*d30ea906Sjfb8856606 return -EINVAL; 3080*d30ea906Sjfb8856606 } 3081*d30ea906Sjfb8856606 3082*d30ea906Sjfb8856606 index = get_mac_addr_index(port_id, addr); 3083*d30ea906Sjfb8856606 if (index < 0) { 3084*d30ea906Sjfb8856606 index = get_mac_addr_index(port_id, &null_mac_addr); 3085*d30ea906Sjfb8856606 if (index < 0) { 3086*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n", 3087*d30ea906Sjfb8856606 port_id); 3088*d30ea906Sjfb8856606 return -ENOSPC; 3089*d30ea906Sjfb8856606 } 3090*d30ea906Sjfb8856606 } else { 3091*d30ea906Sjfb8856606 pool_mask = dev->data->mac_pool_sel[index]; 3092*d30ea906Sjfb8856606 3093*d30ea906Sjfb8856606 /* Check if both MAC address and pool is already there, and do nothing */ 3094*d30ea906Sjfb8856606 if (pool_mask & (1ULL << pool)) 3095*d30ea906Sjfb8856606 return 0; 3096*d30ea906Sjfb8856606 } 3097*d30ea906Sjfb8856606 3098*d30ea906Sjfb8856606 /* Update NIC */ 3099*d30ea906Sjfb8856606 ret = (*dev->dev_ops->mac_addr_add)(dev, addr, index, pool); 3100*d30ea906Sjfb8856606 3101*d30ea906Sjfb8856606 if (ret == 0) { 3102*d30ea906Sjfb8856606 /* Update address in NIC data structure */ 3103*d30ea906Sjfb8856606 ether_addr_copy(addr, &dev->data->mac_addrs[index]); 3104*d30ea906Sjfb8856606 3105*d30ea906Sjfb8856606 /* Update pool bitmap in NIC data structure */ 3106*d30ea906Sjfb8856606 dev->data->mac_pool_sel[index] |= (1ULL << pool); 3107*d30ea906Sjfb8856606 } 3108*d30ea906Sjfb8856606 3109*d30ea906Sjfb8856606 return eth_err(port_id, ret); 3110*d30ea906Sjfb8856606 } 3111*d30ea906Sjfb8856606 3112*d30ea906Sjfb8856606 int 3113*d30ea906Sjfb8856606 rte_eth_dev_mac_addr_remove(uint16_t port_id, struct ether_addr *addr) 3114*d30ea906Sjfb8856606 { 3115*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3116*d30ea906Sjfb8856606 int index; 3117*d30ea906Sjfb8856606 3118*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3119*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3120*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_remove, -ENOTSUP); 3121*d30ea906Sjfb8856606 3122*d30ea906Sjfb8856606 index = get_mac_addr_index(port_id, addr); 3123*d30ea906Sjfb8856606 if (index == 0) { 3124*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 3125*d30ea906Sjfb8856606 "Port %u: Cannot remove default MAC address\n", 3126*d30ea906Sjfb8856606 port_id); 3127*d30ea906Sjfb8856606 return -EADDRINUSE; 3128*d30ea906Sjfb8856606 } else if (index < 0) 3129*d30ea906Sjfb8856606 return 0; /* Do nothing if address wasn't found */ 3130*d30ea906Sjfb8856606 3131*d30ea906Sjfb8856606 /* Update NIC */ 3132*d30ea906Sjfb8856606 (*dev->dev_ops->mac_addr_remove)(dev, index); 3133*d30ea906Sjfb8856606 3134*d30ea906Sjfb8856606 /* Update address in NIC data structure */ 3135*d30ea906Sjfb8856606 ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]); 3136*d30ea906Sjfb8856606 3137*d30ea906Sjfb8856606 /* reset pool bitmap */ 3138*d30ea906Sjfb8856606 dev->data->mac_pool_sel[index] = 0; 3139*d30ea906Sjfb8856606 3140*d30ea906Sjfb8856606 return 0; 3141*d30ea906Sjfb8856606 } 3142*d30ea906Sjfb8856606 3143*d30ea906Sjfb8856606 int 3144*d30ea906Sjfb8856606 rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct ether_addr *addr) 3145*d30ea906Sjfb8856606 { 3146*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3147*d30ea906Sjfb8856606 int ret; 3148*d30ea906Sjfb8856606 3149*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3150*d30ea906Sjfb8856606 3151*d30ea906Sjfb8856606 if (!is_valid_assigned_ether_addr(addr)) 3152*d30ea906Sjfb8856606 return -EINVAL; 3153*d30ea906Sjfb8856606 3154*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3155*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_set, -ENOTSUP); 3156*d30ea906Sjfb8856606 3157*d30ea906Sjfb8856606 ret = (*dev->dev_ops->mac_addr_set)(dev, addr); 3158*d30ea906Sjfb8856606 if (ret < 0) 3159*d30ea906Sjfb8856606 return ret; 3160*d30ea906Sjfb8856606 3161*d30ea906Sjfb8856606 /* Update default address in NIC data structure */ 3162*d30ea906Sjfb8856606 ether_addr_copy(addr, &dev->data->mac_addrs[0]); 3163*d30ea906Sjfb8856606 3164*d30ea906Sjfb8856606 return 0; 3165*d30ea906Sjfb8856606 } 3166*d30ea906Sjfb8856606 3167*d30ea906Sjfb8856606 3168*d30ea906Sjfb8856606 /* 3169*d30ea906Sjfb8856606 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find 3170*d30ea906Sjfb8856606 * an empty spot. 3171*d30ea906Sjfb8856606 */ 3172*d30ea906Sjfb8856606 static int 3173*d30ea906Sjfb8856606 get_hash_mac_addr_index(uint16_t port_id, const struct ether_addr *addr) 3174*d30ea906Sjfb8856606 { 3175*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info; 3176*d30ea906Sjfb8856606 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3177*d30ea906Sjfb8856606 unsigned i; 3178*d30ea906Sjfb8856606 3179*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 3180*d30ea906Sjfb8856606 if (!dev->data->hash_mac_addrs) 3181*d30ea906Sjfb8856606 return -1; 3182*d30ea906Sjfb8856606 3183*d30ea906Sjfb8856606 for (i = 0; i < dev_info.max_hash_mac_addrs; i++) 3184*d30ea906Sjfb8856606 if (memcmp(addr, &dev->data->hash_mac_addrs[i], 3185*d30ea906Sjfb8856606 ETHER_ADDR_LEN) == 0) 3186*d30ea906Sjfb8856606 return i; 3187*d30ea906Sjfb8856606 3188*d30ea906Sjfb8856606 return -1; 3189*d30ea906Sjfb8856606 } 3190*d30ea906Sjfb8856606 3191*d30ea906Sjfb8856606 int 3192*d30ea906Sjfb8856606 rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct ether_addr *addr, 3193*d30ea906Sjfb8856606 uint8_t on) 3194*d30ea906Sjfb8856606 { 3195*d30ea906Sjfb8856606 int index; 3196*d30ea906Sjfb8856606 int ret; 3197*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3198*d30ea906Sjfb8856606 3199*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3200*d30ea906Sjfb8856606 3201*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3202*d30ea906Sjfb8856606 if (is_zero_ether_addr(addr)) { 3203*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n", 3204*d30ea906Sjfb8856606 port_id); 3205*d30ea906Sjfb8856606 return -EINVAL; 3206*d30ea906Sjfb8856606 } 3207*d30ea906Sjfb8856606 3208*d30ea906Sjfb8856606 index = get_hash_mac_addr_index(port_id, addr); 3209*d30ea906Sjfb8856606 /* Check if it's already there, and do nothing */ 3210*d30ea906Sjfb8856606 if ((index >= 0) && on) 3211*d30ea906Sjfb8856606 return 0; 3212*d30ea906Sjfb8856606 3213*d30ea906Sjfb8856606 if (index < 0) { 3214*d30ea906Sjfb8856606 if (!on) { 3215*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 3216*d30ea906Sjfb8856606 "Port %u: the MAC address was not set in UTA\n", 3217*d30ea906Sjfb8856606 port_id); 3218*d30ea906Sjfb8856606 return -EINVAL; 3219*d30ea906Sjfb8856606 } 3220*d30ea906Sjfb8856606 3221*d30ea906Sjfb8856606 index = get_hash_mac_addr_index(port_id, &null_mac_addr); 3222*d30ea906Sjfb8856606 if (index < 0) { 3223*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n", 3224*d30ea906Sjfb8856606 port_id); 3225*d30ea906Sjfb8856606 return -ENOSPC; 3226*d30ea906Sjfb8856606 } 3227*d30ea906Sjfb8856606 } 3228*d30ea906Sjfb8856606 3229*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_hash_table_set, -ENOTSUP); 3230*d30ea906Sjfb8856606 ret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on); 3231*d30ea906Sjfb8856606 if (ret == 0) { 3232*d30ea906Sjfb8856606 /* Update address in NIC data structure */ 3233*d30ea906Sjfb8856606 if (on) 3234*d30ea906Sjfb8856606 ether_addr_copy(addr, 3235*d30ea906Sjfb8856606 &dev->data->hash_mac_addrs[index]); 3236*d30ea906Sjfb8856606 else 3237*d30ea906Sjfb8856606 ether_addr_copy(&null_mac_addr, 3238*d30ea906Sjfb8856606 &dev->data->hash_mac_addrs[index]); 3239*d30ea906Sjfb8856606 } 3240*d30ea906Sjfb8856606 3241*d30ea906Sjfb8856606 return eth_err(port_id, ret); 3242*d30ea906Sjfb8856606 } 3243*d30ea906Sjfb8856606 3244*d30ea906Sjfb8856606 int 3245*d30ea906Sjfb8856606 rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on) 3246*d30ea906Sjfb8856606 { 3247*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3248*d30ea906Sjfb8856606 3249*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3250*d30ea906Sjfb8856606 3251*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3252*d30ea906Sjfb8856606 3253*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_all_hash_table_set, -ENOTSUP); 3254*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev, 3255*d30ea906Sjfb8856606 on)); 3256*d30ea906Sjfb8856606 } 3257*d30ea906Sjfb8856606 3258*d30ea906Sjfb8856606 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx, 3259*d30ea906Sjfb8856606 uint16_t tx_rate) 3260*d30ea906Sjfb8856606 { 3261*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3262*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info; 3263*d30ea906Sjfb8856606 struct rte_eth_link link; 3264*d30ea906Sjfb8856606 3265*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3266*d30ea906Sjfb8856606 3267*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3268*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 3269*d30ea906Sjfb8856606 link = dev->data->dev_link; 3270*d30ea906Sjfb8856606 3271*d30ea906Sjfb8856606 if (queue_idx > dev_info.max_tx_queues) { 3272*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 3273*d30ea906Sjfb8856606 "Set queue rate limit:port %u: invalid queue id=%u\n", 3274*d30ea906Sjfb8856606 port_id, queue_idx); 3275*d30ea906Sjfb8856606 return -EINVAL; 3276*d30ea906Sjfb8856606 } 3277*d30ea906Sjfb8856606 3278*d30ea906Sjfb8856606 if (tx_rate > link.link_speed) { 3279*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 3280*d30ea906Sjfb8856606 "Set queue rate limit:invalid tx_rate=%u, bigger than link speed= %d\n", 3281*d30ea906Sjfb8856606 tx_rate, link.link_speed); 3282*d30ea906Sjfb8856606 return -EINVAL; 3283*d30ea906Sjfb8856606 } 3284*d30ea906Sjfb8856606 3285*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_queue_rate_limit, -ENOTSUP); 3286*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev, 3287*d30ea906Sjfb8856606 queue_idx, tx_rate)); 3288*d30ea906Sjfb8856606 } 3289*d30ea906Sjfb8856606 3290*d30ea906Sjfb8856606 int 3291*d30ea906Sjfb8856606 rte_eth_mirror_rule_set(uint16_t port_id, 3292*d30ea906Sjfb8856606 struct rte_eth_mirror_conf *mirror_conf, 3293*d30ea906Sjfb8856606 uint8_t rule_id, uint8_t on) 3294*d30ea906Sjfb8856606 { 3295*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3296*d30ea906Sjfb8856606 3297*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3298*d30ea906Sjfb8856606 if (mirror_conf->rule_type == 0) { 3299*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Mirror rule type can not be 0\n"); 3300*d30ea906Sjfb8856606 return -EINVAL; 3301*d30ea906Sjfb8856606 } 3302*d30ea906Sjfb8856606 3303*d30ea906Sjfb8856606 if (mirror_conf->dst_pool >= ETH_64_POOLS) { 3304*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid dst pool, pool id must be 0-%d\n", 3305*d30ea906Sjfb8856606 ETH_64_POOLS - 1); 3306*d30ea906Sjfb8856606 return -EINVAL; 3307*d30ea906Sjfb8856606 } 3308*d30ea906Sjfb8856606 3309*d30ea906Sjfb8856606 if ((mirror_conf->rule_type & (ETH_MIRROR_VIRTUAL_POOL_UP | 3310*d30ea906Sjfb8856606 ETH_MIRROR_VIRTUAL_POOL_DOWN)) && 3311*d30ea906Sjfb8856606 (mirror_conf->pool_mask == 0)) { 3312*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 3313*d30ea906Sjfb8856606 "Invalid mirror pool, pool mask can not be 0\n"); 3314*d30ea906Sjfb8856606 return -EINVAL; 3315*d30ea906Sjfb8856606 } 3316*d30ea906Sjfb8856606 3317*d30ea906Sjfb8856606 if ((mirror_conf->rule_type & ETH_MIRROR_VLAN) && 3318*d30ea906Sjfb8856606 mirror_conf->vlan.vlan_mask == 0) { 3319*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 3320*d30ea906Sjfb8856606 "Invalid vlan mask, vlan mask can not be 0\n"); 3321*d30ea906Sjfb8856606 return -EINVAL; 3322*d30ea906Sjfb8856606 } 3323*d30ea906Sjfb8856606 3324*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3325*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_set, -ENOTSUP); 3326*d30ea906Sjfb8856606 3327*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->mirror_rule_set)(dev, 3328*d30ea906Sjfb8856606 mirror_conf, rule_id, on)); 3329*d30ea906Sjfb8856606 } 3330*d30ea906Sjfb8856606 3331*d30ea906Sjfb8856606 int 3332*d30ea906Sjfb8856606 rte_eth_mirror_rule_reset(uint16_t port_id, uint8_t rule_id) 3333*d30ea906Sjfb8856606 { 3334*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3335*d30ea906Sjfb8856606 3336*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3337*d30ea906Sjfb8856606 3338*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3339*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_reset, -ENOTSUP); 3340*d30ea906Sjfb8856606 3341*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->mirror_rule_reset)(dev, 3342*d30ea906Sjfb8856606 rule_id)); 3343*d30ea906Sjfb8856606 } 3344*d30ea906Sjfb8856606 3345*d30ea906Sjfb8856606 RTE_INIT(eth_dev_init_cb_lists) 3346*d30ea906Sjfb8856606 { 3347*d30ea906Sjfb8856606 int i; 3348*d30ea906Sjfb8856606 3349*d30ea906Sjfb8856606 for (i = 0; i < RTE_MAX_ETHPORTS; i++) 3350*d30ea906Sjfb8856606 TAILQ_INIT(&rte_eth_devices[i].link_intr_cbs); 3351*d30ea906Sjfb8856606 } 3352*d30ea906Sjfb8856606 3353*d30ea906Sjfb8856606 int 3354*d30ea906Sjfb8856606 rte_eth_dev_callback_register(uint16_t port_id, 3355*d30ea906Sjfb8856606 enum rte_eth_event_type event, 3356*d30ea906Sjfb8856606 rte_eth_dev_cb_fn cb_fn, void *cb_arg) 3357*d30ea906Sjfb8856606 { 3358*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3359*d30ea906Sjfb8856606 struct rte_eth_dev_callback *user_cb; 3360*d30ea906Sjfb8856606 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */ 3361*d30ea906Sjfb8856606 uint16_t last_port; 3362*d30ea906Sjfb8856606 3363*d30ea906Sjfb8856606 if (!cb_fn) 3364*d30ea906Sjfb8856606 return -EINVAL; 3365*d30ea906Sjfb8856606 3366*d30ea906Sjfb8856606 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) { 3367*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id); 3368*d30ea906Sjfb8856606 return -EINVAL; 3369*d30ea906Sjfb8856606 } 3370*d30ea906Sjfb8856606 3371*d30ea906Sjfb8856606 if (port_id == RTE_ETH_ALL) { 3372*d30ea906Sjfb8856606 next_port = 0; 3373*d30ea906Sjfb8856606 last_port = RTE_MAX_ETHPORTS - 1; 3374*d30ea906Sjfb8856606 } else { 3375*d30ea906Sjfb8856606 next_port = last_port = port_id; 3376*d30ea906Sjfb8856606 } 3377*d30ea906Sjfb8856606 3378*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_cb_lock); 3379*d30ea906Sjfb8856606 3380*d30ea906Sjfb8856606 do { 3381*d30ea906Sjfb8856606 dev = &rte_eth_devices[next_port]; 3382*d30ea906Sjfb8856606 3383*d30ea906Sjfb8856606 TAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) { 3384*d30ea906Sjfb8856606 if (user_cb->cb_fn == cb_fn && 3385*d30ea906Sjfb8856606 user_cb->cb_arg == cb_arg && 3386*d30ea906Sjfb8856606 user_cb->event == event) { 3387*d30ea906Sjfb8856606 break; 3388*d30ea906Sjfb8856606 } 3389*d30ea906Sjfb8856606 } 3390*d30ea906Sjfb8856606 3391*d30ea906Sjfb8856606 /* create a new callback. */ 3392*d30ea906Sjfb8856606 if (user_cb == NULL) { 3393*d30ea906Sjfb8856606 user_cb = rte_zmalloc("INTR_USER_CALLBACK", 3394*d30ea906Sjfb8856606 sizeof(struct rte_eth_dev_callback), 0); 3395*d30ea906Sjfb8856606 if (user_cb != NULL) { 3396*d30ea906Sjfb8856606 user_cb->cb_fn = cb_fn; 3397*d30ea906Sjfb8856606 user_cb->cb_arg = cb_arg; 3398*d30ea906Sjfb8856606 user_cb->event = event; 3399*d30ea906Sjfb8856606 TAILQ_INSERT_TAIL(&(dev->link_intr_cbs), 3400*d30ea906Sjfb8856606 user_cb, next); 3401*d30ea906Sjfb8856606 } else { 3402*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 3403*d30ea906Sjfb8856606 rte_eth_dev_callback_unregister(port_id, event, 3404*d30ea906Sjfb8856606 cb_fn, cb_arg); 3405*d30ea906Sjfb8856606 return -ENOMEM; 3406*d30ea906Sjfb8856606 } 3407*d30ea906Sjfb8856606 3408*d30ea906Sjfb8856606 } 3409*d30ea906Sjfb8856606 } while (++next_port <= last_port); 3410*d30ea906Sjfb8856606 3411*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 3412*d30ea906Sjfb8856606 return 0; 3413*d30ea906Sjfb8856606 } 3414*d30ea906Sjfb8856606 3415*d30ea906Sjfb8856606 int 3416*d30ea906Sjfb8856606 rte_eth_dev_callback_unregister(uint16_t port_id, 3417*d30ea906Sjfb8856606 enum rte_eth_event_type event, 3418*d30ea906Sjfb8856606 rte_eth_dev_cb_fn cb_fn, void *cb_arg) 3419*d30ea906Sjfb8856606 { 3420*d30ea906Sjfb8856606 int ret; 3421*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3422*d30ea906Sjfb8856606 struct rte_eth_dev_callback *cb, *next; 3423*d30ea906Sjfb8856606 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */ 3424*d30ea906Sjfb8856606 uint16_t last_port; 3425*d30ea906Sjfb8856606 3426*d30ea906Sjfb8856606 if (!cb_fn) 3427*d30ea906Sjfb8856606 return -EINVAL; 3428*d30ea906Sjfb8856606 3429*d30ea906Sjfb8856606 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) { 3430*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id); 3431*d30ea906Sjfb8856606 return -EINVAL; 3432*d30ea906Sjfb8856606 } 3433*d30ea906Sjfb8856606 3434*d30ea906Sjfb8856606 if (port_id == RTE_ETH_ALL) { 3435*d30ea906Sjfb8856606 next_port = 0; 3436*d30ea906Sjfb8856606 last_port = RTE_MAX_ETHPORTS - 1; 3437*d30ea906Sjfb8856606 } else { 3438*d30ea906Sjfb8856606 next_port = last_port = port_id; 3439*d30ea906Sjfb8856606 } 3440*d30ea906Sjfb8856606 3441*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_cb_lock); 3442*d30ea906Sjfb8856606 3443*d30ea906Sjfb8856606 do { 3444*d30ea906Sjfb8856606 dev = &rte_eth_devices[next_port]; 3445*d30ea906Sjfb8856606 ret = 0; 3446*d30ea906Sjfb8856606 for (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL; 3447*d30ea906Sjfb8856606 cb = next) { 3448*d30ea906Sjfb8856606 3449*d30ea906Sjfb8856606 next = TAILQ_NEXT(cb, next); 3450*d30ea906Sjfb8856606 3451*d30ea906Sjfb8856606 if (cb->cb_fn != cb_fn || cb->event != event || 3452*d30ea906Sjfb8856606 (cb->cb_arg != (void *)-1 && cb->cb_arg != cb_arg)) 3453*d30ea906Sjfb8856606 continue; 3454*d30ea906Sjfb8856606 3455*d30ea906Sjfb8856606 /* 3456*d30ea906Sjfb8856606 * if this callback is not executing right now, 3457*d30ea906Sjfb8856606 * then remove it. 3458*d30ea906Sjfb8856606 */ 3459*d30ea906Sjfb8856606 if (cb->active == 0) { 3460*d30ea906Sjfb8856606 TAILQ_REMOVE(&(dev->link_intr_cbs), cb, next); 3461*d30ea906Sjfb8856606 rte_free(cb); 3462*d30ea906Sjfb8856606 } else { 3463*d30ea906Sjfb8856606 ret = -EAGAIN; 3464*d30ea906Sjfb8856606 } 3465*d30ea906Sjfb8856606 } 3466*d30ea906Sjfb8856606 } while (++next_port <= last_port); 3467*d30ea906Sjfb8856606 3468*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 3469*d30ea906Sjfb8856606 return ret; 3470*d30ea906Sjfb8856606 } 3471*d30ea906Sjfb8856606 3472*d30ea906Sjfb8856606 int 3473*d30ea906Sjfb8856606 _rte_eth_dev_callback_process(struct rte_eth_dev *dev, 3474*d30ea906Sjfb8856606 enum rte_eth_event_type event, void *ret_param) 3475*d30ea906Sjfb8856606 { 3476*d30ea906Sjfb8856606 struct rte_eth_dev_callback *cb_lst; 3477*d30ea906Sjfb8856606 struct rte_eth_dev_callback dev_cb; 3478*d30ea906Sjfb8856606 int rc = 0; 3479*d30ea906Sjfb8856606 3480*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_cb_lock); 3481*d30ea906Sjfb8856606 TAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) { 3482*d30ea906Sjfb8856606 if (cb_lst->cb_fn == NULL || cb_lst->event != event) 3483*d30ea906Sjfb8856606 continue; 3484*d30ea906Sjfb8856606 dev_cb = *cb_lst; 3485*d30ea906Sjfb8856606 cb_lst->active = 1; 3486*d30ea906Sjfb8856606 if (ret_param != NULL) 3487*d30ea906Sjfb8856606 dev_cb.ret_param = ret_param; 3488*d30ea906Sjfb8856606 3489*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 3490*d30ea906Sjfb8856606 rc = dev_cb.cb_fn(dev->data->port_id, dev_cb.event, 3491*d30ea906Sjfb8856606 dev_cb.cb_arg, dev_cb.ret_param); 3492*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_dev_cb_lock); 3493*d30ea906Sjfb8856606 cb_lst->active = 0; 3494*d30ea906Sjfb8856606 } 3495*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_dev_cb_lock); 3496*d30ea906Sjfb8856606 return rc; 3497*d30ea906Sjfb8856606 } 3498*d30ea906Sjfb8856606 3499*d30ea906Sjfb8856606 void 3500*d30ea906Sjfb8856606 rte_eth_dev_probing_finish(struct rte_eth_dev *dev) 3501*d30ea906Sjfb8856606 { 3502*d30ea906Sjfb8856606 if (dev == NULL) 3503*d30ea906Sjfb8856606 return; 3504*d30ea906Sjfb8856606 3505*d30ea906Sjfb8856606 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_NEW, NULL); 3506*d30ea906Sjfb8856606 3507*d30ea906Sjfb8856606 dev->state = RTE_ETH_DEV_ATTACHED; 3508*d30ea906Sjfb8856606 } 3509*d30ea906Sjfb8856606 3510*d30ea906Sjfb8856606 int 3511*d30ea906Sjfb8856606 rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data) 3512*d30ea906Sjfb8856606 { 3513*d30ea906Sjfb8856606 uint32_t vec; 3514*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3515*d30ea906Sjfb8856606 struct rte_intr_handle *intr_handle; 3516*d30ea906Sjfb8856606 uint16_t qid; 3517*d30ea906Sjfb8856606 int rc; 3518*d30ea906Sjfb8856606 3519*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3520*d30ea906Sjfb8856606 3521*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3522*d30ea906Sjfb8856606 3523*d30ea906Sjfb8856606 if (!dev->intr_handle) { 3524*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 3525*d30ea906Sjfb8856606 return -ENOTSUP; 3526*d30ea906Sjfb8856606 } 3527*d30ea906Sjfb8856606 3528*d30ea906Sjfb8856606 intr_handle = dev->intr_handle; 3529*d30ea906Sjfb8856606 if (!intr_handle->intr_vec) { 3530*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 3531*d30ea906Sjfb8856606 return -EPERM; 3532*d30ea906Sjfb8856606 } 3533*d30ea906Sjfb8856606 3534*d30ea906Sjfb8856606 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) { 3535*d30ea906Sjfb8856606 vec = intr_handle->intr_vec[qid]; 3536*d30ea906Sjfb8856606 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); 3537*d30ea906Sjfb8856606 if (rc && rc != -EEXIST) { 3538*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 3539*d30ea906Sjfb8856606 "p %u q %u rx ctl error op %d epfd %d vec %u\n", 3540*d30ea906Sjfb8856606 port_id, qid, op, epfd, vec); 3541*d30ea906Sjfb8856606 } 3542*d30ea906Sjfb8856606 } 3543*d30ea906Sjfb8856606 3544*d30ea906Sjfb8856606 return 0; 3545*d30ea906Sjfb8856606 } 3546*d30ea906Sjfb8856606 3547*d30ea906Sjfb8856606 int __rte_experimental 3548*d30ea906Sjfb8856606 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id) 3549*d30ea906Sjfb8856606 { 3550*d30ea906Sjfb8856606 struct rte_intr_handle *intr_handle; 3551*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3552*d30ea906Sjfb8856606 unsigned int efd_idx; 3553*d30ea906Sjfb8856606 uint32_t vec; 3554*d30ea906Sjfb8856606 int fd; 3555*d30ea906Sjfb8856606 3556*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1); 3557*d30ea906Sjfb8856606 3558*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3559*d30ea906Sjfb8856606 3560*d30ea906Sjfb8856606 if (queue_id >= dev->data->nb_rx_queues) { 3561*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 3562*d30ea906Sjfb8856606 return -1; 3563*d30ea906Sjfb8856606 } 3564*d30ea906Sjfb8856606 3565*d30ea906Sjfb8856606 if (!dev->intr_handle) { 3566*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 3567*d30ea906Sjfb8856606 return -1; 3568*d30ea906Sjfb8856606 } 3569*d30ea906Sjfb8856606 3570*d30ea906Sjfb8856606 intr_handle = dev->intr_handle; 3571*d30ea906Sjfb8856606 if (!intr_handle->intr_vec) { 3572*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 3573*d30ea906Sjfb8856606 return -1; 3574*d30ea906Sjfb8856606 } 3575*d30ea906Sjfb8856606 3576*d30ea906Sjfb8856606 vec = intr_handle->intr_vec[queue_id]; 3577*d30ea906Sjfb8856606 efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ? 3578*d30ea906Sjfb8856606 (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec; 3579*d30ea906Sjfb8856606 fd = intr_handle->efds[efd_idx]; 3580*d30ea906Sjfb8856606 3581*d30ea906Sjfb8856606 return fd; 3582*d30ea906Sjfb8856606 } 3583*d30ea906Sjfb8856606 3584*d30ea906Sjfb8856606 const struct rte_memzone * 3585*d30ea906Sjfb8856606 rte_eth_dma_zone_reserve(const struct rte_eth_dev *dev, const char *ring_name, 3586*d30ea906Sjfb8856606 uint16_t queue_id, size_t size, unsigned align, 3587*d30ea906Sjfb8856606 int socket_id) 3588*d30ea906Sjfb8856606 { 3589*d30ea906Sjfb8856606 char z_name[RTE_MEMZONE_NAMESIZE]; 3590*d30ea906Sjfb8856606 const struct rte_memzone *mz; 3591*d30ea906Sjfb8856606 3592*d30ea906Sjfb8856606 snprintf(z_name, sizeof(z_name), "eth_p%d_q%d_%s", 3593*d30ea906Sjfb8856606 dev->data->port_id, queue_id, ring_name); 3594*d30ea906Sjfb8856606 3595*d30ea906Sjfb8856606 mz = rte_memzone_lookup(z_name); 3596*d30ea906Sjfb8856606 if (mz) 3597*d30ea906Sjfb8856606 return mz; 3598*d30ea906Sjfb8856606 3599*d30ea906Sjfb8856606 return rte_memzone_reserve_aligned(z_name, size, socket_id, 3600*d30ea906Sjfb8856606 RTE_MEMZONE_IOVA_CONTIG, align); 3601*d30ea906Sjfb8856606 } 3602*d30ea906Sjfb8856606 3603*d30ea906Sjfb8856606 int __rte_experimental 3604*d30ea906Sjfb8856606 rte_eth_dev_create(struct rte_device *device, const char *name, 3605*d30ea906Sjfb8856606 size_t priv_data_size, 3606*d30ea906Sjfb8856606 ethdev_bus_specific_init ethdev_bus_specific_init, 3607*d30ea906Sjfb8856606 void *bus_init_params, 3608*d30ea906Sjfb8856606 ethdev_init_t ethdev_init, void *init_params) 3609*d30ea906Sjfb8856606 { 3610*d30ea906Sjfb8856606 struct rte_eth_dev *ethdev; 3611*d30ea906Sjfb8856606 int retval; 3612*d30ea906Sjfb8856606 3613*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_init, -EINVAL); 3614*d30ea906Sjfb8856606 3615*d30ea906Sjfb8856606 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 3616*d30ea906Sjfb8856606 ethdev = rte_eth_dev_allocate(name); 3617*d30ea906Sjfb8856606 if (!ethdev) 3618*d30ea906Sjfb8856606 return -ENODEV; 3619*d30ea906Sjfb8856606 3620*d30ea906Sjfb8856606 if (priv_data_size) { 3621*d30ea906Sjfb8856606 ethdev->data->dev_private = rte_zmalloc_socket( 3622*d30ea906Sjfb8856606 name, priv_data_size, RTE_CACHE_LINE_SIZE, 3623*d30ea906Sjfb8856606 device->numa_node); 3624*d30ea906Sjfb8856606 3625*d30ea906Sjfb8856606 if (!ethdev->data->dev_private) { 3626*d30ea906Sjfb8856606 RTE_LOG(ERR, EAL, "failed to allocate private data"); 3627*d30ea906Sjfb8856606 retval = -ENOMEM; 3628*d30ea906Sjfb8856606 goto probe_failed; 3629*d30ea906Sjfb8856606 } 3630*d30ea906Sjfb8856606 } 3631*d30ea906Sjfb8856606 } else { 3632*d30ea906Sjfb8856606 ethdev = rte_eth_dev_attach_secondary(name); 3633*d30ea906Sjfb8856606 if (!ethdev) { 3634*d30ea906Sjfb8856606 RTE_LOG(ERR, EAL, "secondary process attach failed, " 3635*d30ea906Sjfb8856606 "ethdev doesn't exist"); 3636*d30ea906Sjfb8856606 return -ENODEV; 3637*d30ea906Sjfb8856606 } 3638*d30ea906Sjfb8856606 } 3639*d30ea906Sjfb8856606 3640*d30ea906Sjfb8856606 ethdev->device = device; 3641*d30ea906Sjfb8856606 3642*d30ea906Sjfb8856606 if (ethdev_bus_specific_init) { 3643*d30ea906Sjfb8856606 retval = ethdev_bus_specific_init(ethdev, bus_init_params); 3644*d30ea906Sjfb8856606 if (retval) { 3645*d30ea906Sjfb8856606 RTE_LOG(ERR, EAL, 3646*d30ea906Sjfb8856606 "ethdev bus specific initialisation failed"); 3647*d30ea906Sjfb8856606 goto probe_failed; 3648*d30ea906Sjfb8856606 } 3649*d30ea906Sjfb8856606 } 3650*d30ea906Sjfb8856606 3651*d30ea906Sjfb8856606 retval = ethdev_init(ethdev, init_params); 3652*d30ea906Sjfb8856606 if (retval) { 3653*d30ea906Sjfb8856606 RTE_LOG(ERR, EAL, "ethdev initialisation failed"); 3654*d30ea906Sjfb8856606 goto probe_failed; 3655*d30ea906Sjfb8856606 } 3656*d30ea906Sjfb8856606 3657*d30ea906Sjfb8856606 rte_eth_dev_probing_finish(ethdev); 3658*d30ea906Sjfb8856606 3659*d30ea906Sjfb8856606 return retval; 3660*d30ea906Sjfb8856606 3661*d30ea906Sjfb8856606 probe_failed: 3662*d30ea906Sjfb8856606 rte_eth_dev_release_port(ethdev); 3663*d30ea906Sjfb8856606 return retval; 3664*d30ea906Sjfb8856606 } 3665*d30ea906Sjfb8856606 3666*d30ea906Sjfb8856606 int __rte_experimental 3667*d30ea906Sjfb8856606 rte_eth_dev_destroy(struct rte_eth_dev *ethdev, 3668*d30ea906Sjfb8856606 ethdev_uninit_t ethdev_uninit) 3669*d30ea906Sjfb8856606 { 3670*d30ea906Sjfb8856606 int ret; 3671*d30ea906Sjfb8856606 3672*d30ea906Sjfb8856606 ethdev = rte_eth_dev_allocated(ethdev->data->name); 3673*d30ea906Sjfb8856606 if (!ethdev) 3674*d30ea906Sjfb8856606 return -ENODEV; 3675*d30ea906Sjfb8856606 3676*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_uninit, -EINVAL); 3677*d30ea906Sjfb8856606 3678*d30ea906Sjfb8856606 ret = ethdev_uninit(ethdev); 3679*d30ea906Sjfb8856606 if (ret) 3680*d30ea906Sjfb8856606 return ret; 3681*d30ea906Sjfb8856606 3682*d30ea906Sjfb8856606 return rte_eth_dev_release_port(ethdev); 3683*d30ea906Sjfb8856606 } 3684*d30ea906Sjfb8856606 3685*d30ea906Sjfb8856606 int 3686*d30ea906Sjfb8856606 rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id, 3687*d30ea906Sjfb8856606 int epfd, int op, void *data) 3688*d30ea906Sjfb8856606 { 3689*d30ea906Sjfb8856606 uint32_t vec; 3690*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3691*d30ea906Sjfb8856606 struct rte_intr_handle *intr_handle; 3692*d30ea906Sjfb8856606 int rc; 3693*d30ea906Sjfb8856606 3694*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3695*d30ea906Sjfb8856606 3696*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3697*d30ea906Sjfb8856606 if (queue_id >= dev->data->nb_rx_queues) { 3698*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 3699*d30ea906Sjfb8856606 return -EINVAL; 3700*d30ea906Sjfb8856606 } 3701*d30ea906Sjfb8856606 3702*d30ea906Sjfb8856606 if (!dev->intr_handle) { 3703*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n"); 3704*d30ea906Sjfb8856606 return -ENOTSUP; 3705*d30ea906Sjfb8856606 } 3706*d30ea906Sjfb8856606 3707*d30ea906Sjfb8856606 intr_handle = dev->intr_handle; 3708*d30ea906Sjfb8856606 if (!intr_handle->intr_vec) { 3709*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n"); 3710*d30ea906Sjfb8856606 return -EPERM; 3711*d30ea906Sjfb8856606 } 3712*d30ea906Sjfb8856606 3713*d30ea906Sjfb8856606 vec = intr_handle->intr_vec[queue_id]; 3714*d30ea906Sjfb8856606 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data); 3715*d30ea906Sjfb8856606 if (rc && rc != -EEXIST) { 3716*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, 3717*d30ea906Sjfb8856606 "p %u q %u rx ctl error op %d epfd %d vec %u\n", 3718*d30ea906Sjfb8856606 port_id, queue_id, op, epfd, vec); 3719*d30ea906Sjfb8856606 return rc; 3720*d30ea906Sjfb8856606 } 3721*d30ea906Sjfb8856606 3722*d30ea906Sjfb8856606 return 0; 3723*d30ea906Sjfb8856606 } 3724*d30ea906Sjfb8856606 3725*d30ea906Sjfb8856606 int 3726*d30ea906Sjfb8856606 rte_eth_dev_rx_intr_enable(uint16_t port_id, 3727*d30ea906Sjfb8856606 uint16_t queue_id) 3728*d30ea906Sjfb8856606 { 3729*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3730*d30ea906Sjfb8856606 3731*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3732*d30ea906Sjfb8856606 3733*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3734*d30ea906Sjfb8856606 3735*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_enable, -ENOTSUP); 3736*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev, 3737*d30ea906Sjfb8856606 queue_id)); 3738*d30ea906Sjfb8856606 } 3739*d30ea906Sjfb8856606 3740*d30ea906Sjfb8856606 int 3741*d30ea906Sjfb8856606 rte_eth_dev_rx_intr_disable(uint16_t port_id, 3742*d30ea906Sjfb8856606 uint16_t queue_id) 3743*d30ea906Sjfb8856606 { 3744*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3745*d30ea906Sjfb8856606 3746*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3747*d30ea906Sjfb8856606 3748*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3749*d30ea906Sjfb8856606 3750*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_disable, -ENOTSUP); 3751*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev, 3752*d30ea906Sjfb8856606 queue_id)); 3753*d30ea906Sjfb8856606 } 3754*d30ea906Sjfb8856606 3755*d30ea906Sjfb8856606 3756*d30ea906Sjfb8856606 int 3757*d30ea906Sjfb8856606 rte_eth_dev_filter_supported(uint16_t port_id, 3758*d30ea906Sjfb8856606 enum rte_filter_type filter_type) 3759*d30ea906Sjfb8856606 { 3760*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3761*d30ea906Sjfb8856606 3762*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3763*d30ea906Sjfb8856606 3764*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3765*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP); 3766*d30ea906Sjfb8856606 return (*dev->dev_ops->filter_ctrl)(dev, filter_type, 3767*d30ea906Sjfb8856606 RTE_ETH_FILTER_NOP, NULL); 3768*d30ea906Sjfb8856606 } 3769*d30ea906Sjfb8856606 3770*d30ea906Sjfb8856606 int 3771*d30ea906Sjfb8856606 rte_eth_dev_filter_ctrl(uint16_t port_id, enum rte_filter_type filter_type, 3772*d30ea906Sjfb8856606 enum rte_filter_op filter_op, void *arg) 3773*d30ea906Sjfb8856606 { 3774*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3775*d30ea906Sjfb8856606 3776*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3777*d30ea906Sjfb8856606 3778*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3779*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP); 3780*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->filter_ctrl)(dev, filter_type, 3781*d30ea906Sjfb8856606 filter_op, arg)); 3782*d30ea906Sjfb8856606 } 3783*d30ea906Sjfb8856606 3784*d30ea906Sjfb8856606 const struct rte_eth_rxtx_callback * 3785*d30ea906Sjfb8856606 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id, 3786*d30ea906Sjfb8856606 rte_rx_callback_fn fn, void *user_param) 3787*d30ea906Sjfb8856606 { 3788*d30ea906Sjfb8856606 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 3789*d30ea906Sjfb8856606 rte_errno = ENOTSUP; 3790*d30ea906Sjfb8856606 return NULL; 3791*d30ea906Sjfb8856606 #endif 3792*d30ea906Sjfb8856606 /* check input parameters */ 3793*d30ea906Sjfb8856606 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 3794*d30ea906Sjfb8856606 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) { 3795*d30ea906Sjfb8856606 rte_errno = EINVAL; 3796*d30ea906Sjfb8856606 return NULL; 3797*d30ea906Sjfb8856606 } 3798*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 3799*d30ea906Sjfb8856606 3800*d30ea906Sjfb8856606 if (cb == NULL) { 3801*d30ea906Sjfb8856606 rte_errno = ENOMEM; 3802*d30ea906Sjfb8856606 return NULL; 3803*d30ea906Sjfb8856606 } 3804*d30ea906Sjfb8856606 3805*d30ea906Sjfb8856606 cb->fn.rx = fn; 3806*d30ea906Sjfb8856606 cb->param = user_param; 3807*d30ea906Sjfb8856606 3808*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_rx_cb_lock); 3809*d30ea906Sjfb8856606 /* Add the callbacks in fifo order. */ 3810*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback *tail = 3811*d30ea906Sjfb8856606 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; 3812*d30ea906Sjfb8856606 3813*d30ea906Sjfb8856606 if (!tail) { 3814*d30ea906Sjfb8856606 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id] = cb; 3815*d30ea906Sjfb8856606 3816*d30ea906Sjfb8856606 } else { 3817*d30ea906Sjfb8856606 while (tail->next) 3818*d30ea906Sjfb8856606 tail = tail->next; 3819*d30ea906Sjfb8856606 tail->next = cb; 3820*d30ea906Sjfb8856606 } 3821*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_rx_cb_lock); 3822*d30ea906Sjfb8856606 3823*d30ea906Sjfb8856606 return cb; 3824*d30ea906Sjfb8856606 } 3825*d30ea906Sjfb8856606 3826*d30ea906Sjfb8856606 const struct rte_eth_rxtx_callback * 3827*d30ea906Sjfb8856606 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id, 3828*d30ea906Sjfb8856606 rte_rx_callback_fn fn, void *user_param) 3829*d30ea906Sjfb8856606 { 3830*d30ea906Sjfb8856606 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 3831*d30ea906Sjfb8856606 rte_errno = ENOTSUP; 3832*d30ea906Sjfb8856606 return NULL; 3833*d30ea906Sjfb8856606 #endif 3834*d30ea906Sjfb8856606 /* check input parameters */ 3835*d30ea906Sjfb8856606 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 3836*d30ea906Sjfb8856606 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) { 3837*d30ea906Sjfb8856606 rte_errno = EINVAL; 3838*d30ea906Sjfb8856606 return NULL; 3839*d30ea906Sjfb8856606 } 3840*d30ea906Sjfb8856606 3841*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 3842*d30ea906Sjfb8856606 3843*d30ea906Sjfb8856606 if (cb == NULL) { 3844*d30ea906Sjfb8856606 rte_errno = ENOMEM; 3845*d30ea906Sjfb8856606 return NULL; 3846*d30ea906Sjfb8856606 } 3847*d30ea906Sjfb8856606 3848*d30ea906Sjfb8856606 cb->fn.rx = fn; 3849*d30ea906Sjfb8856606 cb->param = user_param; 3850*d30ea906Sjfb8856606 3851*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_rx_cb_lock); 3852*d30ea906Sjfb8856606 /* Add the callbacks at fisrt position*/ 3853*d30ea906Sjfb8856606 cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id]; 3854*d30ea906Sjfb8856606 rte_smp_wmb(); 3855*d30ea906Sjfb8856606 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id] = cb; 3856*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_rx_cb_lock); 3857*d30ea906Sjfb8856606 3858*d30ea906Sjfb8856606 return cb; 3859*d30ea906Sjfb8856606 } 3860*d30ea906Sjfb8856606 3861*d30ea906Sjfb8856606 const struct rte_eth_rxtx_callback * 3862*d30ea906Sjfb8856606 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id, 3863*d30ea906Sjfb8856606 rte_tx_callback_fn fn, void *user_param) 3864*d30ea906Sjfb8856606 { 3865*d30ea906Sjfb8856606 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 3866*d30ea906Sjfb8856606 rte_errno = ENOTSUP; 3867*d30ea906Sjfb8856606 return NULL; 3868*d30ea906Sjfb8856606 #endif 3869*d30ea906Sjfb8856606 /* check input parameters */ 3870*d30ea906Sjfb8856606 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL || 3871*d30ea906Sjfb8856606 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) { 3872*d30ea906Sjfb8856606 rte_errno = EINVAL; 3873*d30ea906Sjfb8856606 return NULL; 3874*d30ea906Sjfb8856606 } 3875*d30ea906Sjfb8856606 3876*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0); 3877*d30ea906Sjfb8856606 3878*d30ea906Sjfb8856606 if (cb == NULL) { 3879*d30ea906Sjfb8856606 rte_errno = ENOMEM; 3880*d30ea906Sjfb8856606 return NULL; 3881*d30ea906Sjfb8856606 } 3882*d30ea906Sjfb8856606 3883*d30ea906Sjfb8856606 cb->fn.tx = fn; 3884*d30ea906Sjfb8856606 cb->param = user_param; 3885*d30ea906Sjfb8856606 3886*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_tx_cb_lock); 3887*d30ea906Sjfb8856606 /* Add the callbacks in fifo order. */ 3888*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback *tail = 3889*d30ea906Sjfb8856606 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id]; 3890*d30ea906Sjfb8856606 3891*d30ea906Sjfb8856606 if (!tail) { 3892*d30ea906Sjfb8856606 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id] = cb; 3893*d30ea906Sjfb8856606 3894*d30ea906Sjfb8856606 } else { 3895*d30ea906Sjfb8856606 while (tail->next) 3896*d30ea906Sjfb8856606 tail = tail->next; 3897*d30ea906Sjfb8856606 tail->next = cb; 3898*d30ea906Sjfb8856606 } 3899*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_tx_cb_lock); 3900*d30ea906Sjfb8856606 3901*d30ea906Sjfb8856606 return cb; 3902*d30ea906Sjfb8856606 } 3903*d30ea906Sjfb8856606 3904*d30ea906Sjfb8856606 int 3905*d30ea906Sjfb8856606 rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id, 3906*d30ea906Sjfb8856606 const struct rte_eth_rxtx_callback *user_cb) 3907*d30ea906Sjfb8856606 { 3908*d30ea906Sjfb8856606 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 3909*d30ea906Sjfb8856606 return -ENOTSUP; 3910*d30ea906Sjfb8856606 #endif 3911*d30ea906Sjfb8856606 /* Check input parameters. */ 3912*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 3913*d30ea906Sjfb8856606 if (user_cb == NULL || 3914*d30ea906Sjfb8856606 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) 3915*d30ea906Sjfb8856606 return -EINVAL; 3916*d30ea906Sjfb8856606 3917*d30ea906Sjfb8856606 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3918*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback *cb; 3919*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback **prev_cb; 3920*d30ea906Sjfb8856606 int ret = -EINVAL; 3921*d30ea906Sjfb8856606 3922*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_rx_cb_lock); 3923*d30ea906Sjfb8856606 prev_cb = &dev->post_rx_burst_cbs[queue_id]; 3924*d30ea906Sjfb8856606 for (; *prev_cb != NULL; prev_cb = &cb->next) { 3925*d30ea906Sjfb8856606 cb = *prev_cb; 3926*d30ea906Sjfb8856606 if (cb == user_cb) { 3927*d30ea906Sjfb8856606 /* Remove the user cb from the callback list. */ 3928*d30ea906Sjfb8856606 *prev_cb = cb->next; 3929*d30ea906Sjfb8856606 ret = 0; 3930*d30ea906Sjfb8856606 break; 3931*d30ea906Sjfb8856606 } 3932*d30ea906Sjfb8856606 } 3933*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_rx_cb_lock); 3934*d30ea906Sjfb8856606 3935*d30ea906Sjfb8856606 return ret; 3936*d30ea906Sjfb8856606 } 3937*d30ea906Sjfb8856606 3938*d30ea906Sjfb8856606 int 3939*d30ea906Sjfb8856606 rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id, 3940*d30ea906Sjfb8856606 const struct rte_eth_rxtx_callback *user_cb) 3941*d30ea906Sjfb8856606 { 3942*d30ea906Sjfb8856606 #ifndef RTE_ETHDEV_RXTX_CALLBACKS 3943*d30ea906Sjfb8856606 return -ENOTSUP; 3944*d30ea906Sjfb8856606 #endif 3945*d30ea906Sjfb8856606 /* Check input parameters. */ 3946*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL); 3947*d30ea906Sjfb8856606 if (user_cb == NULL || 3948*d30ea906Sjfb8856606 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) 3949*d30ea906Sjfb8856606 return -EINVAL; 3950*d30ea906Sjfb8856606 3951*d30ea906Sjfb8856606 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3952*d30ea906Sjfb8856606 int ret = -EINVAL; 3953*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback *cb; 3954*d30ea906Sjfb8856606 struct rte_eth_rxtx_callback **prev_cb; 3955*d30ea906Sjfb8856606 3956*d30ea906Sjfb8856606 rte_spinlock_lock(&rte_eth_tx_cb_lock); 3957*d30ea906Sjfb8856606 prev_cb = &dev->pre_tx_burst_cbs[queue_id]; 3958*d30ea906Sjfb8856606 for (; *prev_cb != NULL; prev_cb = &cb->next) { 3959*d30ea906Sjfb8856606 cb = *prev_cb; 3960*d30ea906Sjfb8856606 if (cb == user_cb) { 3961*d30ea906Sjfb8856606 /* Remove the user cb from the callback list. */ 3962*d30ea906Sjfb8856606 *prev_cb = cb->next; 3963*d30ea906Sjfb8856606 ret = 0; 3964*d30ea906Sjfb8856606 break; 3965*d30ea906Sjfb8856606 } 3966*d30ea906Sjfb8856606 } 3967*d30ea906Sjfb8856606 rte_spinlock_unlock(&rte_eth_tx_cb_lock); 3968*d30ea906Sjfb8856606 3969*d30ea906Sjfb8856606 return ret; 3970*d30ea906Sjfb8856606 } 3971*d30ea906Sjfb8856606 3972*d30ea906Sjfb8856606 int 3973*d30ea906Sjfb8856606 rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id, 3974*d30ea906Sjfb8856606 struct rte_eth_rxq_info *qinfo) 3975*d30ea906Sjfb8856606 { 3976*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 3977*d30ea906Sjfb8856606 3978*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 3979*d30ea906Sjfb8856606 3980*d30ea906Sjfb8856606 if (qinfo == NULL) 3981*d30ea906Sjfb8856606 return -EINVAL; 3982*d30ea906Sjfb8856606 3983*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 3984*d30ea906Sjfb8856606 if (queue_id >= dev->data->nb_rx_queues) { 3985*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id); 3986*d30ea906Sjfb8856606 return -EINVAL; 3987*d30ea906Sjfb8856606 } 3988*d30ea906Sjfb8856606 3989*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rxq_info_get, -ENOTSUP); 3990*d30ea906Sjfb8856606 3991*d30ea906Sjfb8856606 memset(qinfo, 0, sizeof(*qinfo)); 3992*d30ea906Sjfb8856606 dev->dev_ops->rxq_info_get(dev, queue_id, qinfo); 3993*d30ea906Sjfb8856606 return 0; 3994*d30ea906Sjfb8856606 } 3995*d30ea906Sjfb8856606 3996*d30ea906Sjfb8856606 int 3997*d30ea906Sjfb8856606 rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id, 3998*d30ea906Sjfb8856606 struct rte_eth_txq_info *qinfo) 3999*d30ea906Sjfb8856606 { 4000*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4001*d30ea906Sjfb8856606 4002*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4003*d30ea906Sjfb8856606 4004*d30ea906Sjfb8856606 if (qinfo == NULL) 4005*d30ea906Sjfb8856606 return -EINVAL; 4006*d30ea906Sjfb8856606 4007*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4008*d30ea906Sjfb8856606 if (queue_id >= dev->data->nb_tx_queues) { 4009*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id); 4010*d30ea906Sjfb8856606 return -EINVAL; 4011*d30ea906Sjfb8856606 } 4012*d30ea906Sjfb8856606 4013*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->txq_info_get, -ENOTSUP); 4014*d30ea906Sjfb8856606 4015*d30ea906Sjfb8856606 memset(qinfo, 0, sizeof(*qinfo)); 4016*d30ea906Sjfb8856606 dev->dev_ops->txq_info_get(dev, queue_id, qinfo); 4017*d30ea906Sjfb8856606 4018*d30ea906Sjfb8856606 return 0; 4019*d30ea906Sjfb8856606 } 4020*d30ea906Sjfb8856606 4021*d30ea906Sjfb8856606 int 4022*d30ea906Sjfb8856606 rte_eth_dev_set_mc_addr_list(uint16_t port_id, 4023*d30ea906Sjfb8856606 struct ether_addr *mc_addr_set, 4024*d30ea906Sjfb8856606 uint32_t nb_mc_addr) 4025*d30ea906Sjfb8856606 { 4026*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4027*d30ea906Sjfb8856606 4028*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4029*d30ea906Sjfb8856606 4030*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4031*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP); 4032*d30ea906Sjfb8856606 return eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev, 4033*d30ea906Sjfb8856606 mc_addr_set, nb_mc_addr)); 4034*d30ea906Sjfb8856606 } 4035*d30ea906Sjfb8856606 4036*d30ea906Sjfb8856606 int 4037*d30ea906Sjfb8856606 rte_eth_timesync_enable(uint16_t port_id) 4038*d30ea906Sjfb8856606 { 4039*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4040*d30ea906Sjfb8856606 4041*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4042*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4043*d30ea906Sjfb8856606 4044*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP); 4045*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev)); 4046*d30ea906Sjfb8856606 } 4047*d30ea906Sjfb8856606 4048*d30ea906Sjfb8856606 int 4049*d30ea906Sjfb8856606 rte_eth_timesync_disable(uint16_t port_id) 4050*d30ea906Sjfb8856606 { 4051*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4052*d30ea906Sjfb8856606 4053*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4054*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4055*d30ea906Sjfb8856606 4056*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP); 4057*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev)); 4058*d30ea906Sjfb8856606 } 4059*d30ea906Sjfb8856606 4060*d30ea906Sjfb8856606 int 4061*d30ea906Sjfb8856606 rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp, 4062*d30ea906Sjfb8856606 uint32_t flags) 4063*d30ea906Sjfb8856606 { 4064*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4065*d30ea906Sjfb8856606 4066*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4067*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4068*d30ea906Sjfb8856606 4069*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp, -ENOTSUP); 4070*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp) 4071*d30ea906Sjfb8856606 (dev, timestamp, flags)); 4072*d30ea906Sjfb8856606 } 4073*d30ea906Sjfb8856606 4074*d30ea906Sjfb8856606 int 4075*d30ea906Sjfb8856606 rte_eth_timesync_read_tx_timestamp(uint16_t port_id, 4076*d30ea906Sjfb8856606 struct timespec *timestamp) 4077*d30ea906Sjfb8856606 { 4078*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4079*d30ea906Sjfb8856606 4080*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4081*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4082*d30ea906Sjfb8856606 4083*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp, -ENOTSUP); 4084*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp) 4085*d30ea906Sjfb8856606 (dev, timestamp)); 4086*d30ea906Sjfb8856606 } 4087*d30ea906Sjfb8856606 4088*d30ea906Sjfb8856606 int 4089*d30ea906Sjfb8856606 rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta) 4090*d30ea906Sjfb8856606 { 4091*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4092*d30ea906Sjfb8856606 4093*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4094*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4095*d30ea906Sjfb8856606 4096*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_adjust_time, -ENOTSUP); 4097*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev, 4098*d30ea906Sjfb8856606 delta)); 4099*d30ea906Sjfb8856606 } 4100*d30ea906Sjfb8856606 4101*d30ea906Sjfb8856606 int 4102*d30ea906Sjfb8856606 rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp) 4103*d30ea906Sjfb8856606 { 4104*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4105*d30ea906Sjfb8856606 4106*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4107*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4108*d30ea906Sjfb8856606 4109*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_time, -ENOTSUP); 4110*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev, 4111*d30ea906Sjfb8856606 timestamp)); 4112*d30ea906Sjfb8856606 } 4113*d30ea906Sjfb8856606 4114*d30ea906Sjfb8856606 int 4115*d30ea906Sjfb8856606 rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp) 4116*d30ea906Sjfb8856606 { 4117*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4118*d30ea906Sjfb8856606 4119*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4120*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4121*d30ea906Sjfb8856606 4122*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_write_time, -ENOTSUP); 4123*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev, 4124*d30ea906Sjfb8856606 timestamp)); 4125*d30ea906Sjfb8856606 } 4126*d30ea906Sjfb8856606 4127*d30ea906Sjfb8856606 int 4128*d30ea906Sjfb8856606 rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info) 4129*d30ea906Sjfb8856606 { 4130*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4131*d30ea906Sjfb8856606 4132*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4133*d30ea906Sjfb8856606 4134*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4135*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg, -ENOTSUP); 4136*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info)); 4137*d30ea906Sjfb8856606 } 4138*d30ea906Sjfb8856606 4139*d30ea906Sjfb8856606 int 4140*d30ea906Sjfb8856606 rte_eth_dev_get_eeprom_length(uint16_t port_id) 4141*d30ea906Sjfb8856606 { 4142*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4143*d30ea906Sjfb8856606 4144*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4145*d30ea906Sjfb8856606 4146*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4147*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom_length, -ENOTSUP); 4148*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev)); 4149*d30ea906Sjfb8856606 } 4150*d30ea906Sjfb8856606 4151*d30ea906Sjfb8856606 int 4152*d30ea906Sjfb8856606 rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info) 4153*d30ea906Sjfb8856606 { 4154*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4155*d30ea906Sjfb8856606 4156*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4157*d30ea906Sjfb8856606 4158*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4159*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom, -ENOTSUP); 4160*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info)); 4161*d30ea906Sjfb8856606 } 4162*d30ea906Sjfb8856606 4163*d30ea906Sjfb8856606 int 4164*d30ea906Sjfb8856606 rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info) 4165*d30ea906Sjfb8856606 { 4166*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4167*d30ea906Sjfb8856606 4168*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4169*d30ea906Sjfb8856606 4170*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4171*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_eeprom, -ENOTSUP); 4172*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info)); 4173*d30ea906Sjfb8856606 } 4174*d30ea906Sjfb8856606 4175*d30ea906Sjfb8856606 int __rte_experimental 4176*d30ea906Sjfb8856606 rte_eth_dev_get_module_info(uint16_t port_id, 4177*d30ea906Sjfb8856606 struct rte_eth_dev_module_info *modinfo) 4178*d30ea906Sjfb8856606 { 4179*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4180*d30ea906Sjfb8856606 4181*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4182*d30ea906Sjfb8856606 4183*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4184*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_info, -ENOTSUP); 4185*d30ea906Sjfb8856606 return (*dev->dev_ops->get_module_info)(dev, modinfo); 4186*d30ea906Sjfb8856606 } 4187*d30ea906Sjfb8856606 4188*d30ea906Sjfb8856606 int __rte_experimental 4189*d30ea906Sjfb8856606 rte_eth_dev_get_module_eeprom(uint16_t port_id, 4190*d30ea906Sjfb8856606 struct rte_dev_eeprom_info *info) 4191*d30ea906Sjfb8856606 { 4192*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4193*d30ea906Sjfb8856606 4194*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4195*d30ea906Sjfb8856606 4196*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4197*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_eeprom, -ENOTSUP); 4198*d30ea906Sjfb8856606 return (*dev->dev_ops->get_module_eeprom)(dev, info); 4199*d30ea906Sjfb8856606 } 4200*d30ea906Sjfb8856606 4201*d30ea906Sjfb8856606 int 4202*d30ea906Sjfb8856606 rte_eth_dev_get_dcb_info(uint16_t port_id, 4203*d30ea906Sjfb8856606 struct rte_eth_dcb_info *dcb_info) 4204*d30ea906Sjfb8856606 { 4205*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4206*d30ea906Sjfb8856606 4207*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4208*d30ea906Sjfb8856606 4209*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4210*d30ea906Sjfb8856606 memset(dcb_info, 0, sizeof(struct rte_eth_dcb_info)); 4211*d30ea906Sjfb8856606 4212*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_dcb_info, -ENOTSUP); 4213*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info)); 4214*d30ea906Sjfb8856606 } 4215*d30ea906Sjfb8856606 4216*d30ea906Sjfb8856606 int 4217*d30ea906Sjfb8856606 rte_eth_dev_l2_tunnel_eth_type_conf(uint16_t port_id, 4218*d30ea906Sjfb8856606 struct rte_eth_l2_tunnel_conf *l2_tunnel) 4219*d30ea906Sjfb8856606 { 4220*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4221*d30ea906Sjfb8856606 4222*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4223*d30ea906Sjfb8856606 if (l2_tunnel == NULL) { 4224*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n"); 4225*d30ea906Sjfb8856606 return -EINVAL; 4226*d30ea906Sjfb8856606 } 4227*d30ea906Sjfb8856606 4228*d30ea906Sjfb8856606 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) { 4229*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 4230*d30ea906Sjfb8856606 return -EINVAL; 4231*d30ea906Sjfb8856606 } 4232*d30ea906Sjfb8856606 4233*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4234*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_eth_type_conf, 4235*d30ea906Sjfb8856606 -ENOTSUP); 4236*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_eth_type_conf)(dev, 4237*d30ea906Sjfb8856606 l2_tunnel)); 4238*d30ea906Sjfb8856606 } 4239*d30ea906Sjfb8856606 4240*d30ea906Sjfb8856606 int 4241*d30ea906Sjfb8856606 rte_eth_dev_l2_tunnel_offload_set(uint16_t port_id, 4242*d30ea906Sjfb8856606 struct rte_eth_l2_tunnel_conf *l2_tunnel, 4243*d30ea906Sjfb8856606 uint32_t mask, 4244*d30ea906Sjfb8856606 uint8_t en) 4245*d30ea906Sjfb8856606 { 4246*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4247*d30ea906Sjfb8856606 4248*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4249*d30ea906Sjfb8856606 4250*d30ea906Sjfb8856606 if (l2_tunnel == NULL) { 4251*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n"); 4252*d30ea906Sjfb8856606 return -EINVAL; 4253*d30ea906Sjfb8856606 } 4254*d30ea906Sjfb8856606 4255*d30ea906Sjfb8856606 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) { 4256*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n"); 4257*d30ea906Sjfb8856606 return -EINVAL; 4258*d30ea906Sjfb8856606 } 4259*d30ea906Sjfb8856606 4260*d30ea906Sjfb8856606 if (mask == 0) { 4261*d30ea906Sjfb8856606 RTE_ETHDEV_LOG(ERR, "Mask should have a value\n"); 4262*d30ea906Sjfb8856606 return -EINVAL; 4263*d30ea906Sjfb8856606 } 4264*d30ea906Sjfb8856606 4265*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4266*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_offload_set, 4267*d30ea906Sjfb8856606 -ENOTSUP); 4268*d30ea906Sjfb8856606 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_offload_set)(dev, 4269*d30ea906Sjfb8856606 l2_tunnel, mask, en)); 4270*d30ea906Sjfb8856606 } 4271*d30ea906Sjfb8856606 4272*d30ea906Sjfb8856606 static void 4273*d30ea906Sjfb8856606 rte_eth_dev_adjust_nb_desc(uint16_t *nb_desc, 4274*d30ea906Sjfb8856606 const struct rte_eth_desc_lim *desc_lim) 4275*d30ea906Sjfb8856606 { 4276*d30ea906Sjfb8856606 if (desc_lim->nb_align != 0) 4277*d30ea906Sjfb8856606 *nb_desc = RTE_ALIGN_CEIL(*nb_desc, desc_lim->nb_align); 4278*d30ea906Sjfb8856606 4279*d30ea906Sjfb8856606 if (desc_lim->nb_max != 0) 4280*d30ea906Sjfb8856606 *nb_desc = RTE_MIN(*nb_desc, desc_lim->nb_max); 4281*d30ea906Sjfb8856606 4282*d30ea906Sjfb8856606 *nb_desc = RTE_MAX(*nb_desc, desc_lim->nb_min); 4283*d30ea906Sjfb8856606 } 4284*d30ea906Sjfb8856606 4285*d30ea906Sjfb8856606 int 4286*d30ea906Sjfb8856606 rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id, 4287*d30ea906Sjfb8856606 uint16_t *nb_rx_desc, 4288*d30ea906Sjfb8856606 uint16_t *nb_tx_desc) 4289*d30ea906Sjfb8856606 { 4290*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4291*d30ea906Sjfb8856606 struct rte_eth_dev_info dev_info; 4292*d30ea906Sjfb8856606 4293*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4294*d30ea906Sjfb8856606 4295*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4296*d30ea906Sjfb8856606 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP); 4297*d30ea906Sjfb8856606 4298*d30ea906Sjfb8856606 rte_eth_dev_info_get(port_id, &dev_info); 4299*d30ea906Sjfb8856606 4300*d30ea906Sjfb8856606 if (nb_rx_desc != NULL) 4301*d30ea906Sjfb8856606 rte_eth_dev_adjust_nb_desc(nb_rx_desc, &dev_info.rx_desc_lim); 4302*d30ea906Sjfb8856606 4303*d30ea906Sjfb8856606 if (nb_tx_desc != NULL) 4304*d30ea906Sjfb8856606 rte_eth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim); 4305*d30ea906Sjfb8856606 4306*d30ea906Sjfb8856606 return 0; 4307*d30ea906Sjfb8856606 } 4308*d30ea906Sjfb8856606 4309*d30ea906Sjfb8856606 int 4310*d30ea906Sjfb8856606 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool) 4311*d30ea906Sjfb8856606 { 4312*d30ea906Sjfb8856606 struct rte_eth_dev *dev; 4313*d30ea906Sjfb8856606 4314*d30ea906Sjfb8856606 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV); 4315*d30ea906Sjfb8856606 4316*d30ea906Sjfb8856606 if (pool == NULL) 4317*d30ea906Sjfb8856606 return -EINVAL; 4318*d30ea906Sjfb8856606 4319*d30ea906Sjfb8856606 dev = &rte_eth_devices[port_id]; 4320*d30ea906Sjfb8856606 4321*d30ea906Sjfb8856606 if (*dev->dev_ops->pool_ops_supported == NULL) 4322*d30ea906Sjfb8856606 return 1; /* all pools are supported */ 4323*d30ea906Sjfb8856606 4324*d30ea906Sjfb8856606 return (*dev->dev_ops->pool_ops_supported)(dev, pool); 4325*d30ea906Sjfb8856606 } 4326*d30ea906Sjfb8856606 4327*d30ea906Sjfb8856606 /** 4328*d30ea906Sjfb8856606 * A set of values to describe the possible states of a switch domain. 4329*d30ea906Sjfb8856606 */ 4330*d30ea906Sjfb8856606 enum rte_eth_switch_domain_state { 4331*d30ea906Sjfb8856606 RTE_ETH_SWITCH_DOMAIN_UNUSED = 0, 4332*d30ea906Sjfb8856606 RTE_ETH_SWITCH_DOMAIN_ALLOCATED 4333*d30ea906Sjfb8856606 }; 4334*d30ea906Sjfb8856606 4335*d30ea906Sjfb8856606 /** 4336*d30ea906Sjfb8856606 * Array of switch domains available for allocation. Array is sized to 4337*d30ea906Sjfb8856606 * RTE_MAX_ETHPORTS elements as there cannot be more active switch domains than 4338*d30ea906Sjfb8856606 * ethdev ports in a single process. 4339*d30ea906Sjfb8856606 */ 4340*d30ea906Sjfb8856606 static struct rte_eth_dev_switch { 4341*d30ea906Sjfb8856606 enum rte_eth_switch_domain_state state; 4342*d30ea906Sjfb8856606 } rte_eth_switch_domains[RTE_MAX_ETHPORTS]; 4343*d30ea906Sjfb8856606 4344*d30ea906Sjfb8856606 int __rte_experimental 4345*d30ea906Sjfb8856606 rte_eth_switch_domain_alloc(uint16_t *domain_id) 4346*d30ea906Sjfb8856606 { 4347*d30ea906Sjfb8856606 unsigned int i; 4348*d30ea906Sjfb8856606 4349*d30ea906Sjfb8856606 *domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 4350*d30ea906Sjfb8856606 4351*d30ea906Sjfb8856606 for (i = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID + 1; 4352*d30ea906Sjfb8856606 i < RTE_MAX_ETHPORTS; i++) { 4353*d30ea906Sjfb8856606 if (rte_eth_switch_domains[i].state == 4354*d30ea906Sjfb8856606 RTE_ETH_SWITCH_DOMAIN_UNUSED) { 4355*d30ea906Sjfb8856606 rte_eth_switch_domains[i].state = 4356*d30ea906Sjfb8856606 RTE_ETH_SWITCH_DOMAIN_ALLOCATED; 4357*d30ea906Sjfb8856606 *domain_id = i; 4358*d30ea906Sjfb8856606 return 0; 4359*d30ea906Sjfb8856606 } 4360*d30ea906Sjfb8856606 } 4361*d30ea906Sjfb8856606 4362*d30ea906Sjfb8856606 return -ENOSPC; 4363*d30ea906Sjfb8856606 } 4364*d30ea906Sjfb8856606 4365*d30ea906Sjfb8856606 int __rte_experimental 4366*d30ea906Sjfb8856606 rte_eth_switch_domain_free(uint16_t domain_id) 4367*d30ea906Sjfb8856606 { 4368*d30ea906Sjfb8856606 if (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID || 4369*d30ea906Sjfb8856606 domain_id >= RTE_MAX_ETHPORTS) 4370*d30ea906Sjfb8856606 return -EINVAL; 4371*d30ea906Sjfb8856606 4372*d30ea906Sjfb8856606 if (rte_eth_switch_domains[domain_id].state != 4373*d30ea906Sjfb8856606 RTE_ETH_SWITCH_DOMAIN_ALLOCATED) 4374*d30ea906Sjfb8856606 return -EINVAL; 4375*d30ea906Sjfb8856606 4376*d30ea906Sjfb8856606 rte_eth_switch_domains[domain_id].state = RTE_ETH_SWITCH_DOMAIN_UNUSED; 4377*d30ea906Sjfb8856606 4378*d30ea906Sjfb8856606 return 0; 4379*d30ea906Sjfb8856606 } 4380*d30ea906Sjfb8856606 4381*d30ea906Sjfb8856606 static int 4382*d30ea906Sjfb8856606 rte_eth_devargs_tokenise(struct rte_kvargs *arglist, const char *str_in) 4383*d30ea906Sjfb8856606 { 4384*d30ea906Sjfb8856606 int state; 4385*d30ea906Sjfb8856606 struct rte_kvargs_pair *pair; 4386*d30ea906Sjfb8856606 char *letter; 4387*d30ea906Sjfb8856606 4388*d30ea906Sjfb8856606 arglist->str = strdup(str_in); 4389*d30ea906Sjfb8856606 if (arglist->str == NULL) 4390*d30ea906Sjfb8856606 return -ENOMEM; 4391*d30ea906Sjfb8856606 4392*d30ea906Sjfb8856606 letter = arglist->str; 4393*d30ea906Sjfb8856606 state = 0; 4394*d30ea906Sjfb8856606 arglist->count = 0; 4395*d30ea906Sjfb8856606 pair = &arglist->pairs[0]; 4396*d30ea906Sjfb8856606 while (1) { 4397*d30ea906Sjfb8856606 switch (state) { 4398*d30ea906Sjfb8856606 case 0: /* Initial */ 4399*d30ea906Sjfb8856606 if (*letter == '=') 4400*d30ea906Sjfb8856606 return -EINVAL; 4401*d30ea906Sjfb8856606 else if (*letter == '\0') 4402*d30ea906Sjfb8856606 return 0; 4403*d30ea906Sjfb8856606 4404*d30ea906Sjfb8856606 state = 1; 4405*d30ea906Sjfb8856606 pair->key = letter; 4406*d30ea906Sjfb8856606 /* fall-thru */ 4407*d30ea906Sjfb8856606 4408*d30ea906Sjfb8856606 case 1: /* Parsing key */ 4409*d30ea906Sjfb8856606 if (*letter == '=') { 4410*d30ea906Sjfb8856606 *letter = '\0'; 4411*d30ea906Sjfb8856606 pair->value = letter + 1; 4412*d30ea906Sjfb8856606 state = 2; 4413*d30ea906Sjfb8856606 } else if (*letter == ',' || *letter == '\0') 4414*d30ea906Sjfb8856606 return -EINVAL; 4415*d30ea906Sjfb8856606 break; 4416*d30ea906Sjfb8856606 4417*d30ea906Sjfb8856606 4418*d30ea906Sjfb8856606 case 2: /* Parsing value */ 4419*d30ea906Sjfb8856606 if (*letter == '[') 4420*d30ea906Sjfb8856606 state = 3; 4421*d30ea906Sjfb8856606 else if (*letter == ',') { 4422*d30ea906Sjfb8856606 *letter = '\0'; 4423*d30ea906Sjfb8856606 arglist->count++; 4424*d30ea906Sjfb8856606 pair = &arglist->pairs[arglist->count]; 4425*d30ea906Sjfb8856606 state = 0; 4426*d30ea906Sjfb8856606 } else if (*letter == '\0') { 4427*d30ea906Sjfb8856606 letter--; 4428*d30ea906Sjfb8856606 arglist->count++; 4429*d30ea906Sjfb8856606 pair = &arglist->pairs[arglist->count]; 4430*d30ea906Sjfb8856606 state = 0; 4431*d30ea906Sjfb8856606 } 4432*d30ea906Sjfb8856606 break; 4433*d30ea906Sjfb8856606 4434*d30ea906Sjfb8856606 case 3: /* Parsing list */ 4435*d30ea906Sjfb8856606 if (*letter == ']') 4436*d30ea906Sjfb8856606 state = 2; 4437*d30ea906Sjfb8856606 else if (*letter == '\0') 4438*d30ea906Sjfb8856606 return -EINVAL; 4439*d30ea906Sjfb8856606 break; 4440*d30ea906Sjfb8856606 } 4441*d30ea906Sjfb8856606 letter++; 4442*d30ea906Sjfb8856606 } 4443*d30ea906Sjfb8856606 } 4444*d30ea906Sjfb8856606 4445*d30ea906Sjfb8856606 int __rte_experimental 4446*d30ea906Sjfb8856606 rte_eth_devargs_parse(const char *dargs, struct rte_eth_devargs *eth_da) 4447*d30ea906Sjfb8856606 { 4448*d30ea906Sjfb8856606 struct rte_kvargs args; 4449*d30ea906Sjfb8856606 struct rte_kvargs_pair *pair; 4450*d30ea906Sjfb8856606 unsigned int i; 4451*d30ea906Sjfb8856606 int result = 0; 4452*d30ea906Sjfb8856606 4453*d30ea906Sjfb8856606 memset(eth_da, 0, sizeof(*eth_da)); 4454*d30ea906Sjfb8856606 4455*d30ea906Sjfb8856606 result = rte_eth_devargs_tokenise(&args, dargs); 4456*d30ea906Sjfb8856606 if (result < 0) 4457*d30ea906Sjfb8856606 goto parse_cleanup; 4458*d30ea906Sjfb8856606 4459*d30ea906Sjfb8856606 for (i = 0; i < args.count; i++) { 4460*d30ea906Sjfb8856606 pair = &args.pairs[i]; 4461*d30ea906Sjfb8856606 if (strcmp("representor", pair->key) == 0) { 4462*d30ea906Sjfb8856606 result = rte_eth_devargs_parse_list(pair->value, 4463*d30ea906Sjfb8856606 rte_eth_devargs_parse_representor_ports, 4464*d30ea906Sjfb8856606 eth_da); 4465*d30ea906Sjfb8856606 if (result < 0) 4466*d30ea906Sjfb8856606 goto parse_cleanup; 4467*d30ea906Sjfb8856606 } 4468*d30ea906Sjfb8856606 } 4469*d30ea906Sjfb8856606 4470*d30ea906Sjfb8856606 parse_cleanup: 4471*d30ea906Sjfb8856606 if (args.str) 4472*d30ea906Sjfb8856606 free(args.str); 4473*d30ea906Sjfb8856606 4474*d30ea906Sjfb8856606 return result; 4475*d30ea906Sjfb8856606 } 4476*d30ea906Sjfb8856606 4477*d30ea906Sjfb8856606 RTE_INIT(ethdev_init_log) 4478*d30ea906Sjfb8856606 { 4479*d30ea906Sjfb8856606 rte_eth_dev_logtype = rte_log_register("lib.ethdev"); 4480*d30ea906Sjfb8856606 if (rte_eth_dev_logtype >= 0) 4481*d30ea906Sjfb8856606 rte_log_set_level(rte_eth_dev_logtype, RTE_LOG_INFO); 4482*d30ea906Sjfb8856606 } 4483