1d30ea906Sjfb8856606 /* SPDX-License-Identifier: BSD-3-Clause
2d30ea906Sjfb8856606  * Copyright(c) 2015 Intel Corporation
3d30ea906Sjfb8856606  */
4d30ea906Sjfb8856606 
5d30ea906Sjfb8856606 #ifndef _RTE_DEV_INFO_H_
6d30ea906Sjfb8856606 #define _RTE_DEV_INFO_H_
7d30ea906Sjfb8856606 
8d30ea906Sjfb8856606 #include <stdint.h>
9d30ea906Sjfb8856606 
10d30ea906Sjfb8856606 /*
11d30ea906Sjfb8856606  * Placeholder for accessing device registers
12d30ea906Sjfb8856606  */
13d30ea906Sjfb8856606 struct rte_dev_reg_info {
14d30ea906Sjfb8856606 	void *data; /**< Buffer for return registers */
15d30ea906Sjfb8856606 	uint32_t offset; /**< Start register table location for access */
16d30ea906Sjfb8856606 	uint32_t length; /**< Number of registers to fetch */
17d30ea906Sjfb8856606 	uint32_t width; /**< Size of device register */
18d30ea906Sjfb8856606 	uint32_t version; /**< Device version */
19d30ea906Sjfb8856606 };
20d30ea906Sjfb8856606 
21d30ea906Sjfb8856606 /*
22d30ea906Sjfb8856606  * Placeholder for accessing device eeprom
23d30ea906Sjfb8856606  */
24d30ea906Sjfb8856606 struct rte_dev_eeprom_info {
25d30ea906Sjfb8856606 	void *data; /**< Buffer for return eeprom */
26d30ea906Sjfb8856606 	uint32_t offset; /**< Start eeprom address for access*/
27d30ea906Sjfb8856606 	uint32_t length; /**< Length of eeprom region to access */
28d30ea906Sjfb8856606 	uint32_t magic; /**< Device-specific key, such as device-id */
29d30ea906Sjfb8856606 };
30d30ea906Sjfb8856606 
31d30ea906Sjfb8856606 /**
32d30ea906Sjfb8856606  * Placeholder for accessing plugin module eeprom
33d30ea906Sjfb8856606  */
34d30ea906Sjfb8856606 struct rte_eth_dev_module_info {
35d30ea906Sjfb8856606 	uint32_t type; /**< Type of plugin module eeprom */
36d30ea906Sjfb8856606 	uint32_t eeprom_len; /**< Length of plugin module eeprom */
37d30ea906Sjfb8856606 };
38d30ea906Sjfb8856606 
39d30ea906Sjfb8856606 /* EEPROM Standards for plug in modules */
40d30ea906Sjfb8856606 #define RTE_ETH_MODULE_SFF_8079             0x1
41d30ea906Sjfb8856606 #define RTE_ETH_MODULE_SFF_8079_LEN         256
42d30ea906Sjfb8856606 #define RTE_ETH_MODULE_SFF_8472             0x2
43d30ea906Sjfb8856606 #define RTE_ETH_MODULE_SFF_8472_LEN         512
44d30ea906Sjfb8856606 #define RTE_ETH_MODULE_SFF_8636             0x3
45d30ea906Sjfb8856606 #define RTE_ETH_MODULE_SFF_8636_LEN         256
46*4418919fSjohnjiang #define RTE_ETH_MODULE_SFF_8636_MAX_LEN     640
47d30ea906Sjfb8856606 #define RTE_ETH_MODULE_SFF_8436             0x4
48d30ea906Sjfb8856606 #define RTE_ETH_MODULE_SFF_8436_LEN         256
49*4418919fSjohnjiang #define RTE_ETH_MODULE_SFF_8436_MAX_LEN     640
50d30ea906Sjfb8856606 
51d30ea906Sjfb8856606 #endif /* _RTE_DEV_INFO_H_ */
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