1*2bfe3f2eSlogwang /*
2*2bfe3f2eSlogwang  *   BSD LICENSE
3*2bfe3f2eSlogwang  *
4*2bfe3f2eSlogwang  *   Copyright (C) Cavium, Inc. 2017.
5*2bfe3f2eSlogwang  *
6*2bfe3f2eSlogwang  *   Redistribution and use in source and binary forms, with or without
7*2bfe3f2eSlogwang  *   modification, are permitted provided that the following conditions
8*2bfe3f2eSlogwang  *   are met:
9*2bfe3f2eSlogwang  *
10*2bfe3f2eSlogwang  *     * Redistributions of source code must retain the above copyright
11*2bfe3f2eSlogwang  *       notice, this list of conditions and the following disclaimer.
12*2bfe3f2eSlogwang  *     * Redistributions in binary form must reproduce the above copyright
13*2bfe3f2eSlogwang  *       notice, this list of conditions and the following disclaimer in
14*2bfe3f2eSlogwang  *       the documentation and/or other materials provided with the
15*2bfe3f2eSlogwang  *       distribution.
16*2bfe3f2eSlogwang  *     * Neither the name of Cavium, Inc nor the names of its
17*2bfe3f2eSlogwang  *       contributors may be used to endorse or promote products derived
18*2bfe3f2eSlogwang  *       from this software without specific prior written permission.
19*2bfe3f2eSlogwang  *
20*2bfe3f2eSlogwang  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21*2bfe3f2eSlogwang  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22*2bfe3f2eSlogwang  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23*2bfe3f2eSlogwang  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24*2bfe3f2eSlogwang  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25*2bfe3f2eSlogwang  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26*2bfe3f2eSlogwang  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27*2bfe3f2eSlogwang  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28*2bfe3f2eSlogwang  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29*2bfe3f2eSlogwang  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30*2bfe3f2eSlogwang  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31*2bfe3f2eSlogwang  */
32*2bfe3f2eSlogwang 
33*2bfe3f2eSlogwang #ifndef STACK_H
34*2bfe3f2eSlogwang #define STACK_H
35*2bfe3f2eSlogwang 
36*2bfe3f2eSlogwang #ifdef __cplusplus
37*2bfe3f2eSlogwang extern "C" {
38*2bfe3f2eSlogwang #endif
39*2bfe3f2eSlogwang 
40*2bfe3f2eSlogwang #include "lthread_int.h"
41*2bfe3f2eSlogwang 
42*2bfe3f2eSlogwang /*
43*2bfe3f2eSlogwang  * Sets up the initial stack for the lthread.
44*2bfe3f2eSlogwang  */
45*2bfe3f2eSlogwang static inline void
46*2bfe3f2eSlogwang arch_set_stack(struct lthread *lt, void *func)
47*2bfe3f2eSlogwang {
48*2bfe3f2eSlogwang 	void **stack_top = (void *)((char *)(lt->stack) + lt->stack_size);
49*2bfe3f2eSlogwang 
50*2bfe3f2eSlogwang 	/*
51*2bfe3f2eSlogwang 	 * Align stack_top to 16 bytes. Arm64 has the constraint that the
52*2bfe3f2eSlogwang 	 * stack pointer must always be quad-word aligned.
53*2bfe3f2eSlogwang 	 */
54*2bfe3f2eSlogwang 	stack_top = (void **)(((unsigned long)(stack_top)) & ~0xfUL);
55*2bfe3f2eSlogwang 
56*2bfe3f2eSlogwang 	/*
57*2bfe3f2eSlogwang 	 * First Stack Frame
58*2bfe3f2eSlogwang 	 */
59*2bfe3f2eSlogwang 	stack_top[0] = NULL;
60*2bfe3f2eSlogwang 	stack_top[-1] = NULL;
61*2bfe3f2eSlogwang 
62*2bfe3f2eSlogwang 	/*
63*2bfe3f2eSlogwang 	 * Initialize the context
64*2bfe3f2eSlogwang 	 */
65*2bfe3f2eSlogwang 	lt->ctx.fp = &stack_top[-1];
66*2bfe3f2eSlogwang 	lt->ctx.sp = &stack_top[-2];
67*2bfe3f2eSlogwang 
68*2bfe3f2eSlogwang 	/*
69*2bfe3f2eSlogwang 	 * Here only the address of _lthread_exec is saved as the link
70*2bfe3f2eSlogwang 	 * register value. The argument to _lthread_exec i.e the address of
71*2bfe3f2eSlogwang 	 * the lthread struct is not saved. This is because the first
72*2bfe3f2eSlogwang 	 * argument to ctx_switch is the address of the new context,
73*2bfe3f2eSlogwang 	 * which also happens to be the address of required lthread struct.
74*2bfe3f2eSlogwang 	 * So while returning from ctx_switch into _thread_exec, parameter
75*2bfe3f2eSlogwang 	 * register x0 will always contain the required value.
76*2bfe3f2eSlogwang 	 */
77*2bfe3f2eSlogwang 	lt->ctx.lr = func;
78*2bfe3f2eSlogwang }
79*2bfe3f2eSlogwang 
80*2bfe3f2eSlogwang #ifdef __cplusplus
81*2bfe3f2eSlogwang }
82*2bfe3f2eSlogwang #endif
83*2bfe3f2eSlogwang 
84*2bfe3f2eSlogwang #endif /* STACK_H_ */
85