1*2bfe3f2eSlogwang /* 2*2bfe3f2eSlogwang * BSD LICENSE 3*2bfe3f2eSlogwang * 4*2bfe3f2eSlogwang * Copyright (C) Cavium, Inc. 2017. 5*2bfe3f2eSlogwang * 6*2bfe3f2eSlogwang * Redistribution and use in source and binary forms, with or without 7*2bfe3f2eSlogwang * modification, are permitted provided that the following conditions 8*2bfe3f2eSlogwang * are met: 9*2bfe3f2eSlogwang * 10*2bfe3f2eSlogwang * * Redistributions of source code must retain the above copyright 11*2bfe3f2eSlogwang * notice, this list of conditions and the following disclaimer. 12*2bfe3f2eSlogwang * * Redistributions in binary form must reproduce the above copyright 13*2bfe3f2eSlogwang * notice, this list of conditions and the following disclaimer in 14*2bfe3f2eSlogwang * the documentation and/or other materials provided with the 15*2bfe3f2eSlogwang * distribution. 16*2bfe3f2eSlogwang * * Neither the name of Cavium, Inc nor the names of its 17*2bfe3f2eSlogwang * contributors may be used to endorse or promote products derived 18*2bfe3f2eSlogwang * from this software without specific prior written permission. 19*2bfe3f2eSlogwang * 20*2bfe3f2eSlogwang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21*2bfe3f2eSlogwang * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22*2bfe3f2eSlogwang * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23*2bfe3f2eSlogwang * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24*2bfe3f2eSlogwang * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25*2bfe3f2eSlogwang * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26*2bfe3f2eSlogwang * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27*2bfe3f2eSlogwang * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28*2bfe3f2eSlogwang * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29*2bfe3f2eSlogwang * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30*2bfe3f2eSlogwang * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31*2bfe3f2eSlogwang */ 32*2bfe3f2eSlogwang 33*2bfe3f2eSlogwang #ifndef CTX_H 34*2bfe3f2eSlogwang #define CTX_H 35*2bfe3f2eSlogwang 36*2bfe3f2eSlogwang #ifdef __cplusplus 37*2bfe3f2eSlogwang extern "C" { 38*2bfe3f2eSlogwang #endif 39*2bfe3f2eSlogwang 40*2bfe3f2eSlogwang /* 41*2bfe3f2eSlogwang * CPU context registers 42*2bfe3f2eSlogwang */ 43*2bfe3f2eSlogwang struct ctx { 44*2bfe3f2eSlogwang void *sp; /* 0 */ 45*2bfe3f2eSlogwang void *fp; /* 8 */ 46*2bfe3f2eSlogwang void *lr; /* 16 */ 47*2bfe3f2eSlogwang 48*2bfe3f2eSlogwang /* Callee Saved Generic Registers */ 49*2bfe3f2eSlogwang void *r19; /* 24 */ 50*2bfe3f2eSlogwang void *r20; /* 32 */ 51*2bfe3f2eSlogwang void *r21; /* 40 */ 52*2bfe3f2eSlogwang void *r22; /* 48 */ 53*2bfe3f2eSlogwang void *r23; /* 56 */ 54*2bfe3f2eSlogwang void *r24; /* 64 */ 55*2bfe3f2eSlogwang void *r25; /* 72 */ 56*2bfe3f2eSlogwang void *r26; /* 80 */ 57*2bfe3f2eSlogwang void *r27; /* 88 */ 58*2bfe3f2eSlogwang void *r28; /* 96 */ 59*2bfe3f2eSlogwang 60*2bfe3f2eSlogwang /* 61*2bfe3f2eSlogwang * Callee Saved SIMD Registers. Only the bottom 64-bits 62*2bfe3f2eSlogwang * of these registers needs to be saved. 63*2bfe3f2eSlogwang */ 64*2bfe3f2eSlogwang void *v8; /* 104 */ 65*2bfe3f2eSlogwang void *v9; /* 112 */ 66*2bfe3f2eSlogwang void *v10; /* 120 */ 67*2bfe3f2eSlogwang void *v11; /* 128 */ 68*2bfe3f2eSlogwang void *v12; /* 136 */ 69*2bfe3f2eSlogwang void *v13; /* 144 */ 70*2bfe3f2eSlogwang void *v14; /* 152 */ 71*2bfe3f2eSlogwang void *v15; /* 160 */ 72*2bfe3f2eSlogwang }; 73*2bfe3f2eSlogwang 74*2bfe3f2eSlogwang 75*2bfe3f2eSlogwang void 76*2bfe3f2eSlogwang ctx_switch(struct ctx *new_ctx, struct ctx *curr_ctx); 77*2bfe3f2eSlogwang 78*2bfe3f2eSlogwang 79*2bfe3f2eSlogwang #ifdef __cplusplus 80*2bfe3f2eSlogwang } 81*2bfe3f2eSlogwang #endif 82*2bfe3f2eSlogwang 83*2bfe3f2eSlogwang #endif /* RTE_CTX_H_ */ 84