1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2015-2020 3 */ 4 5 #ifndef _TXGBE_ETHDEV_H_ 6 #define _TXGBE_ETHDEV_H_ 7 8 #include <stdint.h> 9 10 #include "base/txgbe.h" 11 #include "txgbe_ptypes.h" 12 #include <rte_time.h> 13 14 /* need update link, bit flag */ 15 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0) 16 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1) 17 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2) 18 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3) 19 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4) 20 21 /* 22 * Defines that were not part of txgbe_type.h as they are not used by the 23 * FreeBSD driver. 24 */ 25 #define TXGBE_VFTA_SIZE 128 26 #define TXGBE_VLAN_TAG_SIZE 4 27 #define TXGBE_HKEY_MAX_INDEX 10 28 /*Default value of Max Rx Queue*/ 29 #define TXGBE_MAX_RX_QUEUE_NUM 128 30 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM 31 32 #ifndef NBBY 33 #define NBBY 8 /* number of bits in a byte */ 34 #endif 35 #define TXGBE_HWSTRIP_BITMAP_SIZE \ 36 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY)) 37 38 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */ 39 40 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8 41 42 #define TXGBE_RSS_OFFLOAD_ALL ( \ 43 ETH_RSS_IPV4 | \ 44 ETH_RSS_NONFRAG_IPV4_TCP | \ 45 ETH_RSS_NONFRAG_IPV4_UDP | \ 46 ETH_RSS_IPV6 | \ 47 ETH_RSS_NONFRAG_IPV6_TCP | \ 48 ETH_RSS_NONFRAG_IPV6_UDP | \ 49 ETH_RSS_IPV6_EX | \ 50 ETH_RSS_IPV6_TCP_EX | \ 51 ETH_RSS_IPV6_UDP_EX) 52 53 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET 54 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET 55 56 /* structure for interrupt relative data */ 57 struct txgbe_interrupt { 58 uint32_t flags; 59 uint32_t mask_misc; 60 /* to save original mask during delayed handler */ 61 uint32_t mask_misc_orig; 62 uint32_t mask[2]; 63 }; 64 65 #define TXGBE_NB_STAT_MAPPING 32 66 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 67 #define NB_QMAP_FIELDS_PER_QSM_REG 4 68 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 69 struct txgbe_stat_mappings { 70 uint32_t tqsm[TXGBE_NB_STAT_MAPPING]; 71 uint32_t rqsm[TXGBE_NB_STAT_MAPPING]; 72 }; 73 74 struct txgbe_vfta { 75 uint32_t vfta[TXGBE_VFTA_SIZE]; 76 }; 77 78 struct txgbe_hwstrip { 79 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE]; 80 }; 81 82 /* 83 * VF data which used by PF host only 84 */ 85 #define TXGBE_MAX_VF_MC_ENTRIES 30 86 87 struct txgbe_uta_info { 88 uint8_t uc_filter_type; 89 uint16_t uta_in_use; 90 uint32_t uta_shadow[TXGBE_MAX_UTA]; 91 }; 92 93 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */ 94 95 struct txgbe_mirror_info { 96 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES]; 97 /* store PF mirror rules configuration */ 98 }; 99 100 struct txgbe_vf_info { 101 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN]; 102 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES]; 103 uint16_t num_vf_mc_hashes; 104 bool clear_to_send; 105 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF]; 106 uint16_t vlan_count; 107 uint8_t api_version; 108 uint16_t switch_domain_id; 109 uint16_t xcast_mode; 110 uint16_t mac_count; 111 }; 112 113 struct txgbe_ethertype_filter { 114 uint16_t ethertype; 115 uint32_t etqf; 116 uint32_t etqs; 117 /** 118 * If this filter is added by configuration, 119 * it should not be removed. 120 */ 121 bool conf; 122 }; 123 124 /* 125 * Structure to store filters' info. 126 */ 127 struct txgbe_filter_info { 128 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */ 129 /* store used ethertype filters*/ 130 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX]; 131 }; 132 133 /* The configuration of bandwidth */ 134 struct txgbe_bw_conf { 135 uint8_t tc_num; /* Number of TCs. */ 136 }; 137 138 /* 139 * Structure to store private data for each driver instance (for each port). 140 */ 141 struct txgbe_adapter { 142 struct txgbe_hw hw; 143 struct txgbe_hw_stats stats; 144 struct txgbe_interrupt intr; 145 struct txgbe_stat_mappings stat_mappings; 146 struct txgbe_vfta shadow_vfta; 147 struct txgbe_hwstrip hwstrip; 148 struct txgbe_dcb_config dcb_config; 149 struct txgbe_mirror_info mr_data; 150 struct txgbe_vf_info *vfdata; 151 struct txgbe_uta_info uta_info; 152 struct txgbe_filter_info filter; 153 struct txgbe_bw_conf bw_conf; 154 bool rx_bulk_alloc_allowed; 155 struct rte_timecounter systime_tc; 156 struct rte_timecounter rx_tstamp_tc; 157 struct rte_timecounter tx_tstamp_tc; 158 159 /* For RSS reta table update */ 160 uint8_t rss_reta_updated; 161 }; 162 163 #define TXGBE_DEV_ADAPTER(dev) \ 164 ((struct txgbe_adapter *)(dev)->data->dev_private) 165 166 #define TXGBE_DEV_HW(dev) \ 167 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw) 168 169 #define TXGBE_DEV_STATS(dev) \ 170 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats) 171 172 #define TXGBE_DEV_INTR(dev) \ 173 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr) 174 175 #define TXGBE_DEV_STAT_MAPPINGS(dev) \ 176 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings) 177 178 #define TXGBE_DEV_VFTA(dev) \ 179 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta) 180 181 #define TXGBE_DEV_HWSTRIP(dev) \ 182 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip) 183 184 #define TXGBE_DEV_DCB_CONFIG(dev) \ 185 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config) 186 187 #define TXGBE_DEV_VFDATA(dev) \ 188 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata) 189 190 #define TXGBE_DEV_MR_INFO(dev) \ 191 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data) 192 193 #define TXGBE_DEV_UTA_INFO(dev) \ 194 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info) 195 196 #define TXGBE_DEV_FILTER(dev) \ 197 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter) 198 #define TXGBE_DEV_BW_CONF(dev) \ 199 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf) 200 201 202 /* 203 * RX/TX function prototypes 204 */ 205 void txgbe_dev_clear_queues(struct rte_eth_dev *dev); 206 207 void txgbe_dev_free_queues(struct rte_eth_dev *dev); 208 209 void txgbe_dev_rx_queue_release(void *rxq); 210 211 void txgbe_dev_tx_queue_release(void *txq); 212 213 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 214 uint16_t nb_rx_desc, unsigned int socket_id, 215 const struct rte_eth_rxconf *rx_conf, 216 struct rte_mempool *mb_pool); 217 218 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 219 uint16_t nb_tx_desc, unsigned int socket_id, 220 const struct rte_eth_txconf *tx_conf); 221 222 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev, 223 uint16_t rx_queue_id); 224 225 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); 226 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); 227 228 int txgbe_dev_rx_init(struct rte_eth_dev *dev); 229 230 void txgbe_dev_tx_init(struct rte_eth_dev *dev); 231 232 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev); 233 234 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id); 235 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id); 236 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id); 237 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id); 238 239 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id); 240 241 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id); 242 243 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id); 244 245 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id); 246 247 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 248 struct rte_eth_rxq_info *qinfo); 249 250 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 251 struct rte_eth_txq_info *qinfo); 252 253 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 254 uint16_t nb_pkts); 255 256 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts, 257 uint16_t nb_pkts); 258 259 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue, 260 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 261 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, 262 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 263 264 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 265 uint16_t nb_pkts); 266 267 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts, 268 uint16_t nb_pkts); 269 270 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 271 uint16_t nb_pkts); 272 273 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 274 struct rte_eth_rss_conf *rss_conf); 275 276 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 277 struct rte_eth_rss_conf *rss_conf); 278 279 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type); 280 281 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction, 282 uint8_t queue, uint8_t msix_vector); 283 284 void txgbe_configure_pb(struct rte_eth_dev *dev); 285 void txgbe_configure_port(struct rte_eth_dev *dev); 286 void txgbe_configure_dcb(struct rte_eth_dev *dev); 287 288 int 289 txgbe_dev_link_update_share(struct rte_eth_dev *dev, 290 int wait_to_complete); 291 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev); 292 293 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev); 294 295 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev); 296 297 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev); 298 299 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val); 300 301 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 302 uint16_t tx_rate, uint64_t q_msk); 303 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx, 304 uint16_t tx_rate); 305 static inline int 306 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info, 307 uint16_t ethertype) 308 { 309 int i; 310 311 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 312 if (filter_info->ethertype_filters[i].ethertype == ethertype && 313 (filter_info->ethertype_mask & (1 << i))) 314 return i; 315 } 316 return -1; 317 } 318 319 static inline int 320 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info, 321 struct txgbe_ethertype_filter *ethertype_filter) 322 { 323 int i; 324 325 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) { 326 if (filter_info->ethertype_mask & (1 << i)) 327 continue; 328 329 filter_info->ethertype_mask |= 1 << i; 330 filter_info->ethertype_filters[i].ethertype = 331 ethertype_filter->ethertype; 332 filter_info->ethertype_filters[i].etqf = 333 ethertype_filter->etqf; 334 filter_info->ethertype_filters[i].etqs = 335 ethertype_filter->etqs; 336 filter_info->ethertype_filters[i].conf = 337 ethertype_filter->conf; 338 break; 339 } 340 return (i < TXGBE_ETF_ID_MAX ? i : -1); 341 } 342 343 /* High threshold controlling when to start sending XOFF frames. */ 344 #define TXGBE_FC_XOFF_HITH 128 /*KB*/ 345 /* Low threshold controlling when to start sending XON frames. */ 346 #define TXGBE_FC_XON_LOTH 64 /*KB*/ 347 348 /* Timer value included in XOFF frames. */ 349 #define TXGBE_FC_PAUSE_TIME 0x680 350 351 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 352 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 353 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 354 355 /* 356 * Default values for RX/TX configuration 357 */ 358 #define TXGBE_DEFAULT_RX_FREE_THRESH 32 359 #define TXGBE_DEFAULT_RX_PTHRESH 8 360 #define TXGBE_DEFAULT_RX_HTHRESH 8 361 #define TXGBE_DEFAULT_RX_WTHRESH 0 362 363 #define TXGBE_DEFAULT_TX_FREE_THRESH 32 364 #define TXGBE_DEFAULT_TX_PTHRESH 32 365 #define TXGBE_DEFAULT_TX_HTHRESH 0 366 #define TXGBE_DEFAULT_TX_WTHRESH 0 367 368 /* Additional timesync values. */ 369 #define NSEC_PER_SEC 1000000000L 370 #define TXGBE_INCVAL_10GB 0xCCCCCC 371 #define TXGBE_INCVAL_1GB 0x800000 372 #define TXGBE_INCVAL_100 0xA00000 373 #define TXGBE_INCVAL_10 0xC7F380 374 #define TXGBE_INCVAL_FPGA 0x800000 375 #define TXGBE_INCVAL_SHIFT_10GB 20 376 #define TXGBE_INCVAL_SHIFT_1GB 18 377 #define TXGBE_INCVAL_SHIFT_100 15 378 #define TXGBE_INCVAL_SHIFT_10 12 379 #define TXGBE_INCVAL_SHIFT_FPGA 17 380 381 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 382 383 /* store statistics names and its offset in stats structure */ 384 struct rte_txgbe_xstats_name_off { 385 char name[RTE_ETH_XSTATS_NAME_SIZE]; 386 unsigned int offset; 387 }; 388 389 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 390 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 391 struct rte_ether_addr *mc_addr_set, 392 uint32_t nb_mc_addr); 393 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 394 struct rte_eth_rss_reta_entry64 *reta_conf, 395 uint16_t reta_size); 396 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 397 struct rte_eth_rss_reta_entry64 *reta_conf, 398 uint16_t reta_size); 399 void txgbe_dev_setup_link_alarm_handler(void *param); 400 void txgbe_read_stats_registers(struct txgbe_hw *hw, 401 struct txgbe_hw_stats *hw_stats); 402 403 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev); 404 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev); 405 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev); 406 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 407 uint16_t queue, bool on); 408 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 409 int mask); 410 411 #endif /* _TXGBE_ETHDEV_H_ */ 412