1a9643ea8Slogwang /* 2a9643ea8Slogwang * BSD LICENSE 3a9643ea8Slogwang * 4*2bfe3f2eSlogwang * Copyright (C) Cavium, Inc. 2016. 5a9643ea8Slogwang * 6a9643ea8Slogwang * Redistribution and use in source and binary forms, with or without 7a9643ea8Slogwang * modification, are permitted provided that the following conditions 8a9643ea8Slogwang * are met: 9a9643ea8Slogwang * 10a9643ea8Slogwang * * Redistributions of source code must retain the above copyright 11a9643ea8Slogwang * notice, this list of conditions and the following disclaimer. 12a9643ea8Slogwang * * Redistributions in binary form must reproduce the above copyright 13a9643ea8Slogwang * notice, this list of conditions and the following disclaimer in 14a9643ea8Slogwang * the documentation and/or other materials provided with the 15a9643ea8Slogwang * distribution. 16*2bfe3f2eSlogwang * * Neither the name of Cavium, Inc nor the names of its 17a9643ea8Slogwang * contributors may be used to endorse or promote products derived 18a9643ea8Slogwang * from this software without specific prior written permission. 19a9643ea8Slogwang * 20a9643ea8Slogwang * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21a9643ea8Slogwang * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22a9643ea8Slogwang * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23a9643ea8Slogwang * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24a9643ea8Slogwang * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25a9643ea8Slogwang * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26a9643ea8Slogwang * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27a9643ea8Slogwang * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28a9643ea8Slogwang * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29a9643ea8Slogwang * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30a9643ea8Slogwang * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31a9643ea8Slogwang */ 32a9643ea8Slogwang 33a9643ea8Slogwang #ifndef __THUNDERX_NICVF_ETHDEV_H__ 34a9643ea8Slogwang #define __THUNDERX_NICVF_ETHDEV_H__ 35a9643ea8Slogwang 36a9643ea8Slogwang #include <rte_ethdev.h> 37a9643ea8Slogwang 38*2bfe3f2eSlogwang #define THUNDERX_NICVF_PMD_VERSION "2.0" 39a9643ea8Slogwang #define THUNDERX_REG_BYTES 8 40a9643ea8Slogwang 41a9643ea8Slogwang #define NICVF_INTR_POLL_INTERVAL_MS 50 42a9643ea8Slogwang #define NICVF_HALF_DUPLEX 0x00 43a9643ea8Slogwang #define NICVF_FULL_DUPLEX 0x01 44a9643ea8Slogwang #define NICVF_UNKNOWN_DUPLEX 0xff 45a9643ea8Slogwang 46a9643ea8Slogwang #define NICVF_RSS_OFFLOAD_PASS1 ( \ 47a9643ea8Slogwang ETH_RSS_PORT | \ 48a9643ea8Slogwang ETH_RSS_IPV4 | \ 49a9643ea8Slogwang ETH_RSS_NONFRAG_IPV4_TCP | \ 50a9643ea8Slogwang ETH_RSS_NONFRAG_IPV4_UDP | \ 51a9643ea8Slogwang ETH_RSS_IPV6 | \ 52a9643ea8Slogwang ETH_RSS_NONFRAG_IPV6_TCP | \ 53a9643ea8Slogwang ETH_RSS_NONFRAG_IPV6_UDP) 54a9643ea8Slogwang 55a9643ea8Slogwang #define NICVF_RSS_OFFLOAD_TUNNEL ( \ 56a9643ea8Slogwang ETH_RSS_VXLAN | \ 57a9643ea8Slogwang ETH_RSS_GENEVE | \ 58a9643ea8Slogwang ETH_RSS_NVGRE) 59a9643ea8Slogwang 60a9643ea8Slogwang #define NICVF_DEFAULT_RX_FREE_THRESH 224 61a9643ea8Slogwang #define NICVF_DEFAULT_TX_FREE_THRESH 224 62a9643ea8Slogwang #define NICVF_TX_FREE_MPOOL_THRESH 16 63a9643ea8Slogwang #define NICVF_MAX_RX_FREE_THRESH 1024 64a9643ea8Slogwang #define NICVF_MAX_TX_FREE_THRESH 1024 65a9643ea8Slogwang 66a9643ea8Slogwang #define VLAN_TAG_SIZE 4 /* 802.3ac tag */ 67a9643ea8Slogwang 68a9643ea8Slogwang static inline struct nicvf * 69a9643ea8Slogwang nicvf_pmd_priv(struct rte_eth_dev *eth_dev) 70a9643ea8Slogwang { 71a9643ea8Slogwang return eth_dev->data->dev_private; 72a9643ea8Slogwang } 73a9643ea8Slogwang 74a9643ea8Slogwang static inline uint64_t 75a9643ea8Slogwang nicvf_mempool_phy_offset(struct rte_mempool *mp) 76a9643ea8Slogwang { 77a9643ea8Slogwang struct rte_mempool_memhdr *hdr; 78a9643ea8Slogwang 79a9643ea8Slogwang hdr = STAILQ_FIRST(&mp->mem_list); 80a9643ea8Slogwang assert(hdr != NULL); 81*2bfe3f2eSlogwang return (uint64_t)((uintptr_t)hdr->addr - hdr->iova); 82a9643ea8Slogwang } 83a9643ea8Slogwang 84a9643ea8Slogwang static inline uint16_t 85a9643ea8Slogwang nicvf_mbuff_meta_length(struct rte_mbuf *mbuf) 86a9643ea8Slogwang { 87a9643ea8Slogwang return (uint16_t)((uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf); 88a9643ea8Slogwang } 89a9643ea8Slogwang 90*2bfe3f2eSlogwang static inline uint16_t 91*2bfe3f2eSlogwang nicvf_netdev_qidx(struct nicvf *nic, uint8_t local_qidx) 92*2bfe3f2eSlogwang { 93*2bfe3f2eSlogwang uint16_t global_qidx = local_qidx; 94*2bfe3f2eSlogwang 95*2bfe3f2eSlogwang if (nic->sqs_mode) 96*2bfe3f2eSlogwang global_qidx += ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS); 97*2bfe3f2eSlogwang 98*2bfe3f2eSlogwang return global_qidx; 99*2bfe3f2eSlogwang } 100*2bfe3f2eSlogwang 101a9643ea8Slogwang /* 102a9643ea8Slogwang * Simple phy2virt functions assuming mbufs are in a single huge page 103a9643ea8Slogwang * V = P + offset 104a9643ea8Slogwang * P = V - offset 105a9643ea8Slogwang */ 106a9643ea8Slogwang static inline uintptr_t 107*2bfe3f2eSlogwang nicvf_mbuff_phy2virt(rte_iova_t phy, uint64_t mbuf_phys_off) 108a9643ea8Slogwang { 109a9643ea8Slogwang return (uintptr_t)(phy + mbuf_phys_off); 110a9643ea8Slogwang } 111a9643ea8Slogwang 112a9643ea8Slogwang static inline uintptr_t 113a9643ea8Slogwang nicvf_mbuff_virt2phy(uintptr_t virt, uint64_t mbuf_phys_off) 114a9643ea8Slogwang { 115*2bfe3f2eSlogwang return (rte_iova_t)(virt - mbuf_phys_off); 116*2bfe3f2eSlogwang } 117*2bfe3f2eSlogwang 118*2bfe3f2eSlogwang static inline void 119*2bfe3f2eSlogwang nicvf_tx_range(struct rte_eth_dev *dev, struct nicvf *nic, uint16_t *tx_start, 120*2bfe3f2eSlogwang uint16_t *tx_end) 121*2bfe3f2eSlogwang { 122*2bfe3f2eSlogwang uint16_t tmp; 123*2bfe3f2eSlogwang 124*2bfe3f2eSlogwang *tx_start = RTE_ALIGN_FLOOR(nicvf_netdev_qidx(nic, 0), 125*2bfe3f2eSlogwang MAX_SND_QUEUES_PER_QS); 126*2bfe3f2eSlogwang tmp = RTE_ALIGN_CEIL(nicvf_netdev_qidx(nic, 0) + 1, 127*2bfe3f2eSlogwang MAX_SND_QUEUES_PER_QS) - 1; 128*2bfe3f2eSlogwang *tx_end = dev->data->nb_tx_queues ? 129*2bfe3f2eSlogwang RTE_MIN(tmp, dev->data->nb_tx_queues - 1) : 0; 130*2bfe3f2eSlogwang } 131*2bfe3f2eSlogwang 132*2bfe3f2eSlogwang static inline void 133*2bfe3f2eSlogwang nicvf_rx_range(struct rte_eth_dev *dev, struct nicvf *nic, uint16_t *rx_start, 134*2bfe3f2eSlogwang uint16_t *rx_end) 135*2bfe3f2eSlogwang { 136*2bfe3f2eSlogwang uint16_t tmp; 137*2bfe3f2eSlogwang 138*2bfe3f2eSlogwang *rx_start = RTE_ALIGN_FLOOR(nicvf_netdev_qidx(nic, 0), 139*2bfe3f2eSlogwang MAX_RCV_QUEUES_PER_QS); 140*2bfe3f2eSlogwang tmp = RTE_ALIGN_CEIL(nicvf_netdev_qidx(nic, 0) + 1, 141*2bfe3f2eSlogwang MAX_RCV_QUEUES_PER_QS) - 1; 142*2bfe3f2eSlogwang *rx_end = dev->data->nb_rx_queues ? 143*2bfe3f2eSlogwang RTE_MIN(tmp, dev->data->nb_rx_queues - 1) : 0; 144a9643ea8Slogwang } 145a9643ea8Slogwang 146a9643ea8Slogwang #endif /* __THUNDERX_NICVF_ETHDEV_H__ */ 147