1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 8 0 9 10 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 11 0xfffUL << 0) 12 13 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 14 12 15 16 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 17 0xfffUL << 12) 18 19 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 20 24 21 22 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 23 0xffUL << 24) /* @DPDK */ 24 25 #define XSDM_REG_OPERATION_GEN \ 26 0xf80408UL 27 #define NIG_REG_RX_BRB_OUT_EN \ 28 0x500e18UL 29 #define NIG_REG_STORM_OUT_EN \ 30 0x500e08UL 31 #define PSWRQ2_REG_L2P_VALIDATE_VFID \ 32 0x240c50UL 33 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 34 0x2aae04UL 35 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 36 0x2aa16cUL 37 #define BAR0_MAP_REG_MSDM_RAM \ 38 0x1d00000UL 39 #define BAR0_MAP_REG_USDM_RAM \ 40 0x1d80000UL 41 #define BAR0_MAP_REG_PSDM_RAM \ 42 0x1f00000UL 43 #define BAR0_MAP_REG_TSDM_RAM \ 44 0x1c80000UL 45 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 46 0x5011f4UL 47 #define PRS_REG_SEARCH_TCP \ 48 0x1f0400UL 49 #define PRS_REG_SEARCH_UDP \ 50 0x1f0404UL 51 #define PRS_REG_SEARCH_OPENFLOW \ 52 0x1f0434UL 53 #define TM_REG_PF_ENABLE_CONN \ 54 0x2c043cUL 55 #define TM_REG_PF_ENABLE_TASK \ 56 0x2c0444UL 57 #define TM_REG_PF_SCAN_ACTIVE_CONN \ 58 0x2c04fcUL 59 #define TM_REG_PF_SCAN_ACTIVE_TASK \ 60 0x2c0500UL 61 #define IGU_REG_LEADING_EDGE_LATCH \ 62 0x18082cUL 63 #define IGU_REG_TRAILING_EDGE_LATCH \ 64 0x180830UL 65 #define QM_REG_USG_CNT_PF_TX \ 66 0x2f2eacUL 67 #define QM_REG_USG_CNT_PF_OTHER \ 68 0x2f2eb0UL 69 #define DORQ_REG_PF_DB_ENABLE \ 70 0x100508UL 71 #define QM_REG_PF_EN \ 72 0x2f2ea4UL 73 #define TCFC_REG_STRONG_ENABLE_PF \ 74 0x2d0708UL 75 #define CCFC_REG_STRONG_ENABLE_PF \ 76 0x2e0708UL 77 #define PGLUE_B_REG_PGL_ADDR_88_F0 \ 78 0x2aa404UL 79 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \ 80 0x2aa408UL 81 #define PGLUE_B_REG_PGL_ADDR_90_F0 \ 82 0x2aa40cUL 83 #define PGLUE_B_REG_PGL_ADDR_94_F0 \ 84 0x2aa410UL 85 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 86 0x2aa138UL 87 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 88 0x2aa174UL 89 #define MISC_REG_GEN_PURP_CR0 \ 90 0x008c80UL 91 #define MCP_REG_SCRATCH \ 92 0xe20000UL 93 #define CNIG_REG_NW_PORT_MODE_BB_B0 \ 94 0x218200UL 95 #define MISCS_REG_CHIP_NUM \ 96 0x00976cUL 97 #define MISCS_REG_CHIP_REV \ 98 0x009770UL 99 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 100 0x00971cUL 101 #define MISCS_REG_CHIP_TEST_REG \ 102 0x009778UL 103 #define MISCS_REG_CHIP_METAL \ 104 0x009774UL 105 #define BRB_REG_HEADER_SIZE \ 106 0x340804UL 107 #define BTB_REG_HEADER_SIZE \ 108 0xdb0804UL 109 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 110 0x1c0708UL 111 #define CCFC_REG_ACTIVITY_COUNTER \ 112 0x2e8800UL 113 #define CDU_REG_CID_ADDR_PARAMS \ 114 0x580900UL 115 #define DBG_REG_CLIENT_ENABLE \ 116 0x010004UL 117 #define DMAE_REG_INIT \ 118 0x00c000UL 119 #define DORQ_REG_IFEN \ 120 0x100040UL 121 #define GRC_REG_TIMEOUT_EN \ 122 0x050404UL 123 #define IGU_REG_BLOCK_CONFIGURATION \ 124 0x180040UL 125 #define MCM_REG_INIT \ 126 0x1200000UL 127 #define MCP2_REG_DBG_DWORD_ENABLE \ 128 0x052404UL 129 #define MISC_REG_PORT_MODE \ 130 0x008c00UL 131 #define MISC_REG_BLOCK_256B_EN \ 132 0x008c14UL 133 #define MISCS_REG_RESET_PL_HV \ 134 0x009060UL 135 #define MISCS_REG_CLK_100G_MODE \ 136 0x009070UL 137 #define MISCS_REG_RESET_PL_HV_2 \ 138 0x009150UL 139 #define MSDM_REG_ENABLE_IN1 \ 140 0xfc0004UL 141 #define MSEM_REG_ENABLE_IN \ 142 0x1800004UL 143 #define NIG_REG_CM_HDR \ 144 0x500840UL 145 #define NCSI_REG_CONFIG \ 146 0x040200UL 147 #define PSWRQ2_REG_RBC_DONE \ 148 0x240000UL 149 #define PSWRQ2_REG_CFG_DONE \ 150 0x240004UL 151 #define PBF_REG_INIT \ 152 0xd80000UL 153 #define PTU_REG_ATC_INIT_ARRAY \ 154 0x560000UL 155 #define PCM_REG_INIT \ 156 0x1100000UL 157 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 158 0x2a9000UL 159 #define PRM_REG_DISABLE_PRM \ 160 0x230000UL 161 #define PRS_REG_SOFT_RST \ 162 0x1f0000UL 163 #define PSDM_REG_ENABLE_IN1 \ 164 0xfa0004UL 165 #define PSEM_REG_ENABLE_IN \ 166 0x1600004UL 167 #define PSWRQ_REG_DBG_SELECT \ 168 0x280020UL 169 #define PSWRQ2_REG_CDUT_P_SIZE \ 170 0x24000cUL 171 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 172 0x2a0040UL 173 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 174 0x29e050UL 175 #define PSWRD_REG_DBG_SELECT \ 176 0x29c040UL 177 #define PSWRD2_REG_CONF11 \ 178 0x29d064UL 179 #define PSWWR_REG_USDM_FULL_TH \ 180 0x29a040UL 181 #define PSWWR2_REG_CDU_FULL_TH2 \ 182 0x29b040UL 183 #define QM_REG_MAXPQSIZE_0 \ 184 0x2f0434UL 185 #define RSS_REG_RSS_INIT_EN \ 186 0x238804UL 187 #define RDIF_REG_STOP_ON_ERROR \ 188 0x300040UL 189 #define SRC_REG_SOFT_RST \ 190 0x23874cUL 191 #define TCFC_REG_ACTIVITY_COUNTER \ 192 0x2d8800UL 193 #define TCM_REG_INIT \ 194 0x1180000UL 195 #define TM_REG_PXP_READ_DATA_FIFO_INIT \ 196 0x2c0014UL 197 #define TSDM_REG_ENABLE_IN1 \ 198 0xfb0004UL 199 #define TSEM_REG_ENABLE_IN \ 200 0x1700004UL 201 #define TDIF_REG_STOP_ON_ERROR \ 202 0x310040UL 203 #define UCM_REG_INIT \ 204 0x1280000UL 205 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 206 0x051004UL 207 #define USDM_REG_ENABLE_IN1 \ 208 0xfd0004UL 209 #define USEM_REG_ENABLE_IN \ 210 0x1900004UL 211 #define XCM_REG_INIT \ 212 0x1000000UL 213 #define XSDM_REG_ENABLE_IN1 \ 214 0xf80004UL 215 #define XSEM_REG_ENABLE_IN \ 216 0x1400004UL 217 #define YCM_REG_INIT \ 218 0x1080000UL 219 #define YSDM_REG_ENABLE_IN1 \ 220 0xf90004UL 221 #define YSEM_REG_ENABLE_IN \ 222 0x1500004UL 223 #define XYLD_REG_SCBD_STRICT_PRIO \ 224 0x4c0000UL 225 #define TMLD_REG_SCBD_STRICT_PRIO \ 226 0x4d0000UL 227 #define MULD_REG_SCBD_STRICT_PRIO \ 228 0x4e0000UL 229 #define YULD_REG_SCBD_STRICT_PRIO \ 230 0x4c8000UL 231 #define MISC_REG_SHARED_MEM_ADDR \ 232 0x008c20UL 233 #define DMAE_REG_GO_C0 \ 234 0x00c048UL 235 #define DMAE_REG_GO_C1 \ 236 0x00c04cUL 237 #define DMAE_REG_GO_C2 \ 238 0x00c050UL 239 #define DMAE_REG_GO_C3 \ 240 0x00c054UL 241 #define DMAE_REG_GO_C4 \ 242 0x00c058UL 243 #define DMAE_REG_GO_C5 \ 244 0x00c05cUL 245 #define DMAE_REG_GO_C6 \ 246 0x00c060UL 247 #define DMAE_REG_GO_C7 \ 248 0x00c064UL 249 #define DMAE_REG_GO_C8 \ 250 0x00c068UL 251 #define DMAE_REG_GO_C9 \ 252 0x00c06cUL 253 #define DMAE_REG_GO_C10 \ 254 0x00c070UL 255 #define DMAE_REG_GO_C11 \ 256 0x00c074UL 257 #define DMAE_REG_GO_C12 \ 258 0x00c078UL 259 #define DMAE_REG_GO_C13 \ 260 0x00c07cUL 261 #define DMAE_REG_GO_C14 \ 262 0x00c080UL 263 #define DMAE_REG_GO_C15 \ 264 0x00c084UL 265 #define DMAE_REG_GO_C16 \ 266 0x00c088UL 267 #define DMAE_REG_GO_C17 \ 268 0x00c08cUL 269 #define DMAE_REG_GO_C18 \ 270 0x00c090UL 271 #define DMAE_REG_GO_C19 \ 272 0x00c094UL 273 #define DMAE_REG_GO_C20 \ 274 0x00c098UL 275 #define DMAE_REG_GO_C21 \ 276 0x00c09cUL 277 #define DMAE_REG_GO_C22 \ 278 0x00c0a0UL 279 #define DMAE_REG_GO_C23 \ 280 0x00c0a4UL 281 #define DMAE_REG_GO_C24 \ 282 0x00c0a8UL 283 #define DMAE_REG_GO_C25 \ 284 0x00c0acUL 285 #define DMAE_REG_GO_C26 \ 286 0x00c0b0UL 287 #define DMAE_REG_GO_C27 \ 288 0x00c0b4UL 289 #define DMAE_REG_GO_C28 \ 290 0x00c0b8UL 291 #define DMAE_REG_GO_C29 \ 292 0x00c0bcUL 293 #define DMAE_REG_GO_C30 \ 294 0x00c0c0UL 295 #define DMAE_REG_GO_C31 \ 296 0x00c0c4UL 297 #define DMAE_REG_CMD_MEM \ 298 0x00c800UL 299 #define QM_REG_MAXPQSIZETXSEL_0 \ 300 0x2f0440UL 301 #define QM_REG_SDMCMDREADY \ 302 0x2f1e10UL 303 #define QM_REG_SDMCMDADDR \ 304 0x2f1e04UL 305 #define QM_REG_SDMCMDDATALSB \ 306 0x2f1e08UL 307 #define QM_REG_SDMCMDDATAMSB \ 308 0x2f1e0cUL 309 #define QM_REG_SDMCMDGO \ 310 0x2f1e14UL 311 #define QM_REG_RLPFCRD \ 312 0x2f4d80UL 313 #define QM_REG_RLPFINCVAL \ 314 0x2f4c80UL 315 #define QM_REG_RLGLBLCRD \ 316 0x2f4400UL 317 #define QM_REG_RLGLBLINCVAL \ 318 0x2f3400UL 319 #define IGU_REG_ATTENTION_ENABLE \ 320 0x18083cUL 321 #define IGU_REG_ATTN_MSG_ADDR_L \ 322 0x180820UL 323 #define IGU_REG_ATTN_MSG_ADDR_H \ 324 0x180824UL 325 #define IGU_REG_LEADING_EDGE_LATCH \ 326 0x18082cUL 327 #define IGU_REG_TRAILING_EDGE_LATCH \ 328 0x180830UL 329 #define IGU_REG_ATTENTION_ACK_BITS \ 330 0x180838UL 331 #define IGU_REG_PBA_STS_PF \ 332 0x180d20UL 333 #define IGU_REG_PF_FUNCTIONAL_CLEANUP \ 334 0x181210UL 335 #define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \ 336 0x18042cUL 337 #define IGU_REG_PBA_STS_PF_SIZE 5 338 #define IGU_REG_PBA_STS_PF \ 339 0x180d20UL 340 #define MISC_REG_AEU_GENERAL_ATTN_0 \ 341 0x008400UL 342 #define CAU_REG_SB_ADDR_MEMORY \ 343 0x1c8000UL 344 #define CAU_REG_SB_VAR_MEMORY \ 345 0x1c6000UL 346 #define CAU_REG_PI_MEMORY \ 347 0x1d0000UL 348 #define IGU_REG_PF_CONFIGURATION \ 349 0x180800UL 350 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 351 0x00849cUL 352 #define MISC_REG_AEU_MASK_ATTN_IGU \ 353 0x008494UL 354 #define IGU_REG_CLEANUP_STATUS_0 \ 355 0x180980UL 356 #define IGU_REG_CLEANUP_STATUS_1 \ 357 0x180a00UL 358 #define IGU_REG_CLEANUP_STATUS_2 \ 359 0x180a80UL 360 #define IGU_REG_CLEANUP_STATUS_3 \ 361 0x180b00UL 362 #define IGU_REG_CLEANUP_STATUS_4 \ 363 0x180b80UL 364 #define IGU_REG_COMMAND_REG_32LSB_DATA \ 365 0x180840UL 366 #define IGU_REG_COMMAND_REG_CTRL \ 367 0x180848UL 368 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 369 0x1UL << 1) 370 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 371 0x1UL << 0) 372 #define IGU_REG_MAPPING_MEMORY \ 373 0x184000UL 374 #define MISCS_REG_GENERIC_POR_0 \ 375 0x0096d4UL 376 #define MCP_REG_NVM_CFG4 \ 377 0xe0642cUL 378 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 379 0x7UL << 0) 380 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 381 0 382 #define CCFC_REG_STRONG_ENABLE_VF 0x2e070cUL 383 #define CNIG_REG_PMEG_IF_CMD_BB_B0 0x21821cUL 384 #define CNIG_REG_PMEG_IF_ADDR_BB_B0 0x218224UL 385 #define CNIG_REG_PMEG_IF_WRDATA_BB_B0 0x218228UL 386 #define NWM_REG_MAC0 0x800400UL 387 #define NWM_REG_MAC0_SIZE 256 388 #define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL 389 #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT 0 390 #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT 1 391 #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT 3 392 #define ETH_MAC_REG_XIF_MODE 0x000080UL 393 #define ETH_MAC_REG_XIF_MODE_XGMII_SHIFT 0 394 #define ETH_MAC_REG_FRM_LENGTH 0x000014UL 395 #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT 0 396 #define ETH_MAC_REG_TX_IPG_LENGTH 0x000044UL 397 #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT 0 398 #define ETH_MAC_REG_RX_FIFO_SECTIONS 0x00001cUL 399 #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT 0 400 #define ETH_MAC_REG_TX_FIFO_SECTIONS 0x000020UL 401 #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT 16 402 #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT 0 403 #define ETH_MAC_REG_COMMAND_CONFIG 0x000008UL 404 #define MISC_REG_RESET_PL_PDA_VAUX 0x008090UL 405 #define MISC_REG_XMAC_CORE_PORT_MODE 0x008c08UL 406 #define MISC_REG_XMAC_PHY_PORT_MODE 0x008c04UL 407 #define XMAC_REG_MODE 0x210008UL 408 #define XMAC_REG_RX_MAX_SIZE 0x210040UL 409 #define XMAC_REG_TX_CTRL_LO 0x210020UL 410 #define XMAC_REG_CTRL 0x210000UL 411 #define XMAC_REG_RX_CTRL 0x210030UL 412 #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE (0x1UL << 12) 413 #define MISC_REG_CLK_100G_MODE 0x008c10UL 414 #define MISC_REG_OPTE_MODE 0x008c0cUL 415 #define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH 0x501b84UL 416 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL 417 #define PRS_REG_SEARCH_TAG1 0x1f0444UL 418 #define PRS_REG_SEARCH_TCP_FIRST_FRAG 0x1f0410UL 419 #define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL 420 #define MISCS_REG_ECO_RESERVED 0x0097b4UL 421 #define PGLUE_B_REG_PF_BAR0_SIZE 0x2aae60UL 422 #define PGLUE_B_REG_PF_BAR1_SIZE 0x2aae64UL 423 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 424 #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL 425 #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL 426 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE 0x501b00UL 427 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 428 #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL 429 #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL 430 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 431 #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL 432 #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL 433 #define NIG_REG_LLH_FUNC_FILTER_MODE 0x501ac0UL 434 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE 0x501b00UL 435 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 436 #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL 437 #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL 438 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 439 #define NIG_REG_LLH_FUNC_FILTER_EN 0x501a80UL 440 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE 16 441 #define NIG_REG_LLH_FUNC_FILTER_VALUE 0x501a00UL 442 #define XMAC_REG_CTRL_TX_EN (0x1UL << 0) 443 #define XMAC_REG_CTRL_RX_EN (0x1UL << 1) 444 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE (0xffUL << 24) /* @DPDK */ 445 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE (0xffUL << 16) 446 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 16 447 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE (0xffUL << 16) 448 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE (0xffUL << 24) /* @DPDK */ 449 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK (0xfffUL << 0) 450 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 0 451 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK (0xfffUL << 0) 452 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 0 453 #define PSWRQ2_REG_ILT_MEMORY 0x260000UL 454 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL 455 #define QM_REG_WFQVPWEIGHT 0x2fa000UL 456 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_0 0x50160cUL 457 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_0 0x501f88UL 458 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_1 0x501610UL 459 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_1 0x501f8cUL 460 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 0x5015e4UL 461 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0 0x501f58UL 462 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1 0x5015e8UL 463 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1 0x501f5cUL 464 #define NIG_REG_LB_ARB_CLIENT_IS_STRICT 0x5015c0UL 465 #define NIG_REG_TX_ARB_CLIENT_IS_STRICT 0x501f34UL 466 #define NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ 0x5015c4UL 467 #define NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x501f38UL 468 #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT 1 469 #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL 0x501f1cUL 470 #define NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD 0x501f20UL 471 #define NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE 0x501f24UL 472 #define NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE 0x501f28UL 473 #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT 0 474 #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT 1 475 #define NIG_REG_LB_BRBRATELIMIT_CTRL 0x50150cUL 476 #define NIG_REG_LB_BRBRATELIMIT_INC_PERIOD 0x501510UL 477 #define NIG_REG_LB_BRBRATELIMIT_INC_VALUE 0x501514UL 478 #define NIG_REG_LB_BRBRATELIMIT_MAX_VALUE 0x501518UL 479 #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT 0 480 #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT 1 481 #define NIG_REG_LB_TCRATELIMIT_CTRL_0 0x501520UL 482 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 0x501540UL 483 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 0x501560UL 484 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 0x501580UL 485 #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT 0 486 #define NIG_REG_PRIORITY_FOR_TC_0 0x501bccUL 487 #define NIG_REG_RX_TC0_PRIORITY_MASK 0x501becUL 488 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_1 0x1f0540UL 489 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_0 0x1f0534UL 490 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1 0x1f053cUL 491 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0 0x1f0530UL 492 #define PRS_REG_ETS_ARB_CLIENT_IS_STRICT 0x1f0514UL 493 #define PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ 0x1f0518UL 494 #define BRB_REG_TOTAL_MAC_SIZE 0x3408c0UL 495 #define BRB_REG_SHARED_HR_AREA 0x340880UL 496 #define BRB_REG_TC_GUARANTIED_0 0x340900UL 497 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_0 0x340978UL 498 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0 0x340c60UL 499 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 0x340d38UL 500 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0 0x340ab0UL 501 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0 0x340b88UL 502 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0 0x340c00UL 503 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0 0x340cd8UL 504 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0 0x340a50UL 505 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0 0x340b28UL 506 #define PRS_REG_VXLAN_PORT 0x1f0738UL 507 #define NIG_REG_VXLAN_PORT 0x50105cUL 508 #define PBF_REG_VXLAN_PORT 0xd80518UL 509 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 510 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL 511 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 512 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 513 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL 514 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 515 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL 516 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 517 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 518 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 519 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL 520 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL 521 #define PRS_REG_NGE_PORT 0x1f086cUL 522 #define NIG_REG_NGE_PORT 0x508b38UL 523 #define PBF_REG_NGE_PORT 0xd8051cUL 524 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 525 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL 526 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL 527 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL 528 #define NIG_REG_NGE_COMP_VER 0x508b30UL 529 #define PBF_REG_NGE_COMP_VER 0xd80524UL 530 #define PRS_REG_NGE_COMP_VER 0x1f0878UL 531 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL 532 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL 533 #define NIG_REG_PKT_PRIORITY_TO_TC 0x501ba4UL 534 #define PGLUE_B_REG_START_INIT_PTT_GTT 0x2a8008UL 535 #define PGLUE_B_REG_INIT_DONE_PTT_GTT 0x2a800cUL 536 #define MISC_REG_AEU_GENERAL_ATTN_35 0x00848cUL 537 #define MCP_REG_CPU_STATE 0xe05004UL 538 #define MCP_REG_CPU_MODE 0xe05000UL 539 #define MCP_REG_CPU_MODE_SOFT_HALT (0x1UL << 10) 540 #define MCP_REG_CPU_EVENT_MASK 0xe05008UL 541 #define PSWHST_REG_VF_DISABLED_ERROR_VALID 0x2a0060UL 542 #define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS 0x2a0064UL 543 #define PSWHST_REG_VF_DISABLED_ERROR_DATA 0x2a005cUL 544 #define PSWHST_REG_INCORRECT_ACCESS_VALID 0x2a0070UL 545 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS 0x2a0074UL 546 #define PSWHST_REG_INCORRECT_ACCESS_DATA 0x2a0068UL 547 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH 0x2a006cUL 548 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL 549 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL 550 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 0x050050UL 551 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x2aa150UL 552 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x2aa144UL 553 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x2aa148UL 554 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x2aa14cUL 555 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x2aa160UL 556 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x2aa154UL 557 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x2aa158UL 558 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x2aa15cUL 559 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL 0x2aa164UL 560 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS 0x2aa54cUL 561 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 0x2aa544UL 562 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 0x2aa548UL 563 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 0x2aae80UL 564 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 0x2aae74UL 565 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 0x2aae78UL 566 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS 0x2aae7cUL 567 #define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x2aa3bcUL 568 #define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT (0x1UL << 10) 569 #define DORQ_REG_DB_DROP_REASON 0x100a2cUL 570 #define DORQ_REG_DB_DROP_DETAILS 0x100a24UL 571 #define TM_REG_INT_STS_1 0x2c0190UL 572 #define TM_REG_INT_STS_1_PEND_TASK_SCAN (0x1UL << 6) 573 #define TM_REG_INT_STS_1_PEND_CONN_SCAN (0x1UL << 5) 574 #define TM_REG_INT_MASK_1 0x2c0194UL 575 #define TM_REG_INT_MASK_1_PEND_CONN_SCAN (0x1UL << 5) 576 #define TM_REG_INT_MASK_1_PEND_TASK_SCAN (0x1UL << 6) 577 #define MISC_REG_AEU_AFTER_INVERT_1_IGU 0x0087b4UL 578 #define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL 579 #define MISC_REG_AEU_ENABLE3_IGU_OUT_0 0x0084a4UL 580 #define YSEM_REG_FAST_MEMORY 0x1540000UL 581 #define NIG_REG_FLOWCTRL_MODE 0x501ba0UL 582 #define TSEM_REG_FAST_MEMORY 0x1740000UL 583 #define TSEM_REG_DBG_FRAME_MODE 0x1701408UL 584 #define TSEM_REG_SLOW_DBG_ACTIVE 0x1701400UL 585 #define TSEM_REG_SLOW_DBG_MODE 0x1701404UL 586 #define TSEM_REG_DBG_MODE1_CFG 0x1701420UL 587 #define TSEM_REG_SYNC_DBG_EMPTY 0x1701160UL 588 #define TSEM_REG_SLOW_DBG_EMPTY 0x1701140UL 589 #define TCM_REG_CTX_RBC_ACCS 0x11814c0UL 590 #define TCM_REG_AGG_CON_CTX 0x11814c4UL 591 #define TCM_REG_SM_CON_CTX 0x11814ccUL 592 #define TCM_REG_AGG_TASK_CTX 0x11814c8UL 593 #define TCM_REG_SM_TASK_CTX 0x11814d0UL 594 #define MSEM_REG_FAST_MEMORY 0x1840000UL 595 #define MSEM_REG_DBG_FRAME_MODE 0x1801408UL 596 #define MSEM_REG_SLOW_DBG_ACTIVE 0x1801400UL 597 #define MSEM_REG_SLOW_DBG_MODE 0x1801404UL 598 #define MSEM_REG_DBG_MODE1_CFG 0x1801420UL 599 #define MSEM_REG_SYNC_DBG_EMPTY 0x1801160UL 600 #define MSEM_REG_SLOW_DBG_EMPTY 0x1801140UL 601 #define MCM_REG_CTX_RBC_ACCS 0x1201800UL 602 #define MCM_REG_AGG_CON_CTX 0x1201804UL 603 #define MCM_REG_SM_CON_CTX 0x120180cUL 604 #define MCM_REG_AGG_TASK_CTX 0x1201808UL 605 #define MCM_REG_SM_TASK_CTX 0x1201810UL 606 #define USEM_REG_FAST_MEMORY 0x1940000UL 607 #define USEM_REG_DBG_FRAME_MODE 0x1901408UL 608 #define USEM_REG_SLOW_DBG_ACTIVE 0x1901400UL 609 #define USEM_REG_SLOW_DBG_MODE 0x1901404UL 610 #define USEM_REG_DBG_MODE1_CFG 0x1901420UL 611 #define USEM_REG_SYNC_DBG_EMPTY 0x1901160UL 612 #define USEM_REG_SLOW_DBG_EMPTY 0x1901140UL 613 #define UCM_REG_CTX_RBC_ACCS 0x1281700UL 614 #define UCM_REG_AGG_CON_CTX 0x1281704UL 615 #define UCM_REG_SM_CON_CTX 0x128170cUL 616 #define UCM_REG_AGG_TASK_CTX 0x1281708UL 617 #define UCM_REG_SM_TASK_CTX 0x1281710UL 618 #define XSEM_REG_FAST_MEMORY 0x1440000UL 619 #define XSEM_REG_DBG_FRAME_MODE 0x1401408UL 620 #define XSEM_REG_SLOW_DBG_ACTIVE 0x1401400UL 621 #define XSEM_REG_SLOW_DBG_MODE 0x1401404UL 622 #define XSEM_REG_DBG_MODE1_CFG 0x1401420UL 623 #define XSEM_REG_SYNC_DBG_EMPTY 0x1401160UL 624 #define XSEM_REG_SLOW_DBG_EMPTY 0x1401140UL 625 #define XCM_REG_CTX_RBC_ACCS 0x1001800UL 626 #define XCM_REG_AGG_CON_CTX 0x1001804UL 627 #define XCM_REG_SM_CON_CTX 0x1001808UL 628 #define YSEM_REG_DBG_FRAME_MODE 0x1501408UL 629 #define YSEM_REG_SLOW_DBG_ACTIVE 0x1501400UL 630 #define YSEM_REG_SLOW_DBG_MODE 0x1501404UL 631 #define YSEM_REG_DBG_MODE1_CFG 0x1501420UL 632 #define YSEM_REG_SYNC_DBG_EMPTY 0x1501160UL 633 #define YCM_REG_CTX_RBC_ACCS 0x1081800UL 634 #define YCM_REG_AGG_CON_CTX 0x1081804UL 635 #define YCM_REG_SM_CON_CTX 0x108180cUL 636 #define YCM_REG_AGG_TASK_CTX 0x1081808UL 637 #define YCM_REG_SM_TASK_CTX 0x1081810UL 638 #define PSEM_REG_FAST_MEMORY 0x1640000UL 639 #define PSEM_REG_DBG_FRAME_MODE 0x1601408UL 640 #define PSEM_REG_SLOW_DBG_ACTIVE 0x1601400UL 641 #define PSEM_REG_SLOW_DBG_MODE 0x1601404UL 642 #define PSEM_REG_DBG_MODE1_CFG 0x1601420UL 643 #define PSEM_REG_SYNC_DBG_EMPTY 0x1601160UL 644 #define PSEM_REG_SLOW_DBG_EMPTY 0x1601140UL 645 #define PCM_REG_CTX_RBC_ACCS 0x1101440UL 646 #define PCM_REG_SM_CON_CTX 0x1101444UL 647 #define GRC_REG_DBG_SELECT 0x0500a4UL 648 #define GRC_REG_DBG_DWORD_ENABLE 0x0500a8UL 649 #define GRC_REG_DBG_SHIFT 0x0500acUL 650 #define GRC_REG_DBG_FORCE_VALID 0x0500b0UL 651 #define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL 652 #define PGLUE_B_REG_DBG_SELECT 0x2a8400UL 653 #define PGLUE_B_REG_DBG_DWORD_ENABLE 0x2a8404UL 654 #define PGLUE_B_REG_DBG_SHIFT 0x2a8408UL 655 #define PGLUE_B_REG_DBG_FORCE_VALID 0x2a840cUL 656 #define PGLUE_B_REG_DBG_FORCE_FRAME 0x2a8410UL 657 #define CNIG_REG_DBG_SELECT_K2 0x218254UL 658 #define CNIG_REG_DBG_DWORD_ENABLE_K2 0x218258UL 659 #define CNIG_REG_DBG_SHIFT_K2 0x21825cUL 660 #define CNIG_REG_DBG_FORCE_VALID_K2 0x218260UL 661 #define CNIG_REG_DBG_FORCE_FRAME_K2 0x218264UL 662 #define NCSI_REG_DBG_SELECT 0x040474UL 663 #define NCSI_REG_DBG_DWORD_ENABLE 0x040478UL 664 #define NCSI_REG_DBG_SHIFT 0x04047cUL 665 #define NCSI_REG_DBG_FORCE_VALID 0x040480UL 666 #define NCSI_REG_DBG_FORCE_FRAME 0x040484UL 667 #define BMB_REG_DBG_SELECT 0x540a7cUL 668 #define BMB_REG_DBG_DWORD_ENABLE 0x540a80UL 669 #define BMB_REG_DBG_SHIFT 0x540a84UL 670 #define BMB_REG_DBG_FORCE_VALID 0x540a88UL 671 #define BMB_REG_DBG_FORCE_FRAME 0x540a8cUL 672 #define PCIE_REG_DBG_SELECT 0x0547e8UL 673 #define PHY_PCIE_REG_DBG_SELECT 0x629fe8UL 674 #define PCIE_REG_DBG_DWORD_ENABLE 0x0547ecUL 675 #define PHY_PCIE_REG_DBG_DWORD_ENABLE 0x629fecUL 676 #define PCIE_REG_DBG_SHIFT 0x0547f0UL 677 #define PHY_PCIE_REG_DBG_SHIFT 0x629ff0UL 678 #define PCIE_REG_DBG_FORCE_VALID 0x0547f4UL 679 #define PHY_PCIE_REG_DBG_FORCE_VALID 0x629ff4UL 680 #define PCIE_REG_DBG_FORCE_FRAME 0x0547f8UL 681 #define PHY_PCIE_REG_DBG_FORCE_FRAME 0x629ff8UL 682 #define MCP2_REG_DBG_SELECT 0x052400UL 683 #define MCP2_REG_DBG_SHIFT 0x052408UL 684 #define MCP2_REG_DBG_FORCE_VALID 0x052440UL 685 #define MCP2_REG_DBG_FORCE_FRAME 0x052444UL 686 #define PSWHST_REG_DBG_SELECT 0x2a0100UL 687 #define PSWHST_REG_DBG_DWORD_ENABLE 0x2a0104UL 688 #define PSWHST_REG_DBG_SHIFT 0x2a0108UL 689 #define PSWHST_REG_DBG_FORCE_VALID 0x2a010cUL 690 #define PSWHST_REG_DBG_FORCE_FRAME 0x2a0110UL 691 #define PSWHST2_REG_DBG_SELECT 0x29e058UL 692 #define PSWHST2_REG_DBG_DWORD_ENABLE 0x29e05cUL 693 #define PSWHST2_REG_DBG_SHIFT 0x29e060UL 694 #define PSWHST2_REG_DBG_FORCE_VALID 0x29e064UL 695 #define PSWHST2_REG_DBG_FORCE_FRAME 0x29e068UL 696 #define PSWRD_REG_DBG_DWORD_ENABLE 0x29c044UL 697 #define PSWRD_REG_DBG_SHIFT 0x29c048UL 698 #define PSWRD_REG_DBG_FORCE_VALID 0x29c04cUL 699 #define PSWRD_REG_DBG_FORCE_FRAME 0x29c050UL 700 #define PSWRD2_REG_DBG_SELECT 0x29d400UL 701 #define PSWRD2_REG_DBG_DWORD_ENABLE 0x29d404UL 702 #define PSWRD2_REG_DBG_SHIFT 0x29d408UL 703 #define PSWRD2_REG_DBG_FORCE_VALID 0x29d40cUL 704 #define PSWRD2_REG_DBG_FORCE_FRAME 0x29d410UL 705 #define PSWWR_REG_DBG_SELECT 0x29a084UL 706 #define PSWWR_REG_DBG_DWORD_ENABLE 0x29a088UL 707 #define PSWWR_REG_DBG_SHIFT 0x29a08cUL 708 #define PSWWR_REG_DBG_FORCE_VALID 0x29a090UL 709 #define PSWWR_REG_DBG_FORCE_FRAME 0x29a094UL 710 #define PSWRQ_REG_DBG_DWORD_ENABLE 0x280024UL 711 #define PSWRQ_REG_DBG_SHIFT 0x280028UL 712 #define PSWRQ_REG_DBG_FORCE_VALID 0x28002cUL 713 #define PSWRQ_REG_DBG_FORCE_FRAME 0x280030UL 714 #define PSWRQ2_REG_DBG_SELECT 0x240100UL 715 #define PSWRQ2_REG_DBG_DWORD_ENABLE 0x240104UL 716 #define PSWRQ2_REG_DBG_SHIFT 0x240108UL 717 #define PSWRQ2_REG_DBG_FORCE_VALID 0x24010cUL 718 #define PSWRQ2_REG_DBG_FORCE_FRAME 0x240110UL 719 #define PGLCS_REG_DBG_SELECT 0x001d14UL 720 #define PGLCS_REG_DBG_DWORD_ENABLE 0x001d18UL 721 #define PGLCS_REG_DBG_SHIFT 0x001d1cUL 722 #define PGLCS_REG_DBG_FORCE_VALID 0x001d20UL 723 #define PGLCS_REG_DBG_FORCE_FRAME 0x001d24UL 724 #define PTU_REG_DBG_SELECT 0x560100UL 725 #define PTU_REG_DBG_DWORD_ENABLE 0x560104UL 726 #define PTU_REG_DBG_SHIFT 0x560108UL 727 #define PTU_REG_DBG_FORCE_VALID 0x56010cUL 728 #define PTU_REG_DBG_FORCE_FRAME 0x560110UL 729 #define DMAE_REG_DBG_SELECT 0x00c510UL 730 #define DMAE_REG_DBG_DWORD_ENABLE 0x00c514UL 731 #define DMAE_REG_DBG_SHIFT 0x00c518UL 732 #define DMAE_REG_DBG_FORCE_VALID 0x00c51cUL 733 #define DMAE_REG_DBG_FORCE_FRAME 0x00c520UL 734 #define TCM_REG_DBG_SELECT 0x1180040UL 735 #define TCM_REG_DBG_DWORD_ENABLE 0x1180044UL 736 #define TCM_REG_DBG_SHIFT 0x1180048UL 737 #define TCM_REG_DBG_FORCE_VALID 0x118004cUL 738 #define TCM_REG_DBG_FORCE_FRAME 0x1180050UL 739 #define MCM_REG_DBG_SELECT 0x1200040UL 740 #define MCM_REG_DBG_DWORD_ENABLE 0x1200044UL 741 #define MCM_REG_DBG_SHIFT 0x1200048UL 742 #define MCM_REG_DBG_FORCE_VALID 0x120004cUL 743 #define MCM_REG_DBG_FORCE_FRAME 0x1200050UL 744 #define UCM_REG_DBG_SELECT 0x1280050UL 745 #define UCM_REG_DBG_DWORD_ENABLE 0x1280054UL 746 #define UCM_REG_DBG_SHIFT 0x1280058UL 747 #define UCM_REG_DBG_FORCE_VALID 0x128005cUL 748 #define UCM_REG_DBG_FORCE_FRAME 0x1280060UL 749 #define XCM_REG_DBG_SELECT 0x1000040UL 750 #define XCM_REG_DBG_DWORD_ENABLE 0x1000044UL 751 #define XCM_REG_DBG_SHIFT 0x1000048UL 752 #define XCM_REG_DBG_FORCE_VALID 0x100004cUL 753 #define XCM_REG_DBG_FORCE_FRAME 0x1000050UL 754 #define YCM_REG_DBG_SELECT 0x1080040UL 755 #define YCM_REG_DBG_DWORD_ENABLE 0x1080044UL 756 #define YCM_REG_DBG_SHIFT 0x1080048UL 757 #define YCM_REG_DBG_FORCE_VALID 0x108004cUL 758 #define YCM_REG_DBG_FORCE_FRAME 0x1080050UL 759 #define PCM_REG_DBG_SELECT 0x1100040UL 760 #define PCM_REG_DBG_DWORD_ENABLE 0x1100044UL 761 #define PCM_REG_DBG_SHIFT 0x1100048UL 762 #define PCM_REG_DBG_FORCE_VALID 0x110004cUL 763 #define PCM_REG_DBG_FORCE_FRAME 0x1100050UL 764 #define QM_REG_DBG_SELECT 0x2f2e74UL 765 #define QM_REG_DBG_DWORD_ENABLE 0x2f2e78UL 766 #define QM_REG_DBG_SHIFT 0x2f2e7cUL 767 #define QM_REG_DBG_FORCE_VALID 0x2f2e80UL 768 #define QM_REG_DBG_FORCE_FRAME 0x2f2e84UL 769 #define TM_REG_DBG_SELECT 0x2c07a8UL 770 #define TM_REG_DBG_DWORD_ENABLE 0x2c07acUL 771 #define TM_REG_DBG_SHIFT 0x2c07b0UL 772 #define TM_REG_DBG_FORCE_VALID 0x2c07b4UL 773 #define TM_REG_DBG_FORCE_FRAME 0x2c07b8UL 774 #define DORQ_REG_DBG_SELECT 0x100ad0UL 775 #define DORQ_REG_DBG_DWORD_ENABLE 0x100ad4UL 776 #define DORQ_REG_DBG_SHIFT 0x100ad8UL 777 #define DORQ_REG_DBG_FORCE_VALID 0x100adcUL 778 #define DORQ_REG_DBG_FORCE_FRAME 0x100ae0UL 779 #define BRB_REG_DBG_SELECT 0x340ed0UL 780 #define BRB_REG_DBG_DWORD_ENABLE 0x340ed4UL 781 #define BRB_REG_DBG_SHIFT 0x340ed8UL 782 #define BRB_REG_DBG_FORCE_VALID 0x340edcUL 783 #define BRB_REG_DBG_FORCE_FRAME 0x340ee0UL 784 #define SRC_REG_DBG_SELECT 0x238700UL 785 #define SRC_REG_DBG_DWORD_ENABLE 0x238704UL 786 #define SRC_REG_DBG_SHIFT 0x238708UL 787 #define SRC_REG_DBG_FORCE_VALID 0x23870cUL 788 #define SRC_REG_DBG_FORCE_FRAME 0x238710UL 789 #define PRS_REG_DBG_SELECT 0x1f0b6cUL 790 #define PRS_REG_DBG_DWORD_ENABLE 0x1f0b70UL 791 #define PRS_REG_DBG_SHIFT 0x1f0b74UL 792 #define PRS_REG_DBG_FORCE_VALID 0x1f0ba0UL 793 #define PRS_REG_DBG_FORCE_FRAME 0x1f0ba4UL 794 #define TSDM_REG_DBG_SELECT 0xfb0e28UL 795 #define TSDM_REG_DBG_DWORD_ENABLE 0xfb0e2cUL 796 #define TSDM_REG_DBG_SHIFT 0xfb0e30UL 797 #define TSDM_REG_DBG_FORCE_VALID 0xfb0e34UL 798 #define TSDM_REG_DBG_FORCE_FRAME 0xfb0e38UL 799 #define MSDM_REG_DBG_SELECT 0xfc0e28UL 800 #define MSDM_REG_DBG_DWORD_ENABLE 0xfc0e2cUL 801 #define MSDM_REG_DBG_SHIFT 0xfc0e30UL 802 #define MSDM_REG_DBG_FORCE_VALID 0xfc0e34UL 803 #define MSDM_REG_DBG_FORCE_FRAME 0xfc0e38UL 804 #define USDM_REG_DBG_SELECT 0xfd0e28UL 805 #define USDM_REG_DBG_DWORD_ENABLE 0xfd0e2cUL 806 #define USDM_REG_DBG_SHIFT 0xfd0e30UL 807 #define USDM_REG_DBG_FORCE_VALID 0xfd0e34UL 808 #define USDM_REG_DBG_FORCE_FRAME 0xfd0e38UL 809 #define XSDM_REG_DBG_SELECT 0xf80e28UL 810 #define XSDM_REG_DBG_DWORD_ENABLE 0xf80e2cUL 811 #define XSDM_REG_DBG_SHIFT 0xf80e30UL 812 #define XSDM_REG_DBG_FORCE_VALID 0xf80e34UL 813 #define XSDM_REG_DBG_FORCE_FRAME 0xf80e38UL 814 #define YSDM_REG_DBG_SELECT 0xf90e28UL 815 #define YSDM_REG_DBG_DWORD_ENABLE 0xf90e2cUL 816 #define YSDM_REG_DBG_SHIFT 0xf90e30UL 817 #define YSDM_REG_DBG_FORCE_VALID 0xf90e34UL 818 #define YSDM_REG_DBG_FORCE_FRAME 0xf90e38UL 819 #define PSDM_REG_DBG_SELECT 0xfa0e28UL 820 #define PSDM_REG_DBG_DWORD_ENABLE 0xfa0e2cUL 821 #define PSDM_REG_DBG_SHIFT 0xfa0e30UL 822 #define PSDM_REG_DBG_FORCE_VALID 0xfa0e34UL 823 #define PSDM_REG_DBG_FORCE_FRAME 0xfa0e38UL 824 #define TSEM_REG_DBG_SELECT 0x1701528UL 825 #define TSEM_REG_DBG_DWORD_ENABLE 0x170152cUL 826 #define TSEM_REG_DBG_SHIFT 0x1701530UL 827 #define TSEM_REG_DBG_FORCE_VALID 0x1701534UL 828 #define TSEM_REG_DBG_FORCE_FRAME 0x1701538UL 829 #define MSEM_REG_DBG_SELECT 0x1801528UL 830 #define MSEM_REG_DBG_DWORD_ENABLE 0x180152cUL 831 #define MSEM_REG_DBG_SHIFT 0x1801530UL 832 #define MSEM_REG_DBG_FORCE_VALID 0x1801534UL 833 #define MSEM_REG_DBG_FORCE_FRAME 0x1801538UL 834 #define USEM_REG_DBG_SELECT 0x1901528UL 835 #define USEM_REG_DBG_DWORD_ENABLE 0x190152cUL 836 #define USEM_REG_DBG_SHIFT 0x1901530UL 837 #define USEM_REG_DBG_FORCE_VALID 0x1901534UL 838 #define USEM_REG_DBG_FORCE_FRAME 0x1901538UL 839 #define XSEM_REG_DBG_SELECT 0x1401528UL 840 #define XSEM_REG_DBG_DWORD_ENABLE 0x140152cUL 841 #define XSEM_REG_DBG_SHIFT 0x1401530UL 842 #define XSEM_REG_DBG_FORCE_VALID 0x1401534UL 843 #define XSEM_REG_DBG_FORCE_FRAME 0x1401538UL 844 #define YSEM_REG_DBG_SELECT 0x1501528UL 845 #define YSEM_REG_DBG_DWORD_ENABLE 0x150152cUL 846 #define YSEM_REG_DBG_SHIFT 0x1501530UL 847 #define YSEM_REG_DBG_FORCE_VALID 0x1501534UL 848 #define YSEM_REG_DBG_FORCE_FRAME 0x1501538UL 849 #define PSEM_REG_DBG_SELECT 0x1601528UL 850 #define PSEM_REG_DBG_DWORD_ENABLE 0x160152cUL 851 #define PSEM_REG_DBG_SHIFT 0x1601530UL 852 #define PSEM_REG_DBG_FORCE_VALID 0x1601534UL 853 #define PSEM_REG_DBG_FORCE_FRAME 0x1601538UL 854 #define RSS_REG_DBG_SELECT 0x238c4cUL 855 #define RSS_REG_DBG_DWORD_ENABLE 0x238c50UL 856 #define RSS_REG_DBG_SHIFT 0x238c54UL 857 #define RSS_REG_DBG_FORCE_VALID 0x238c58UL 858 #define RSS_REG_DBG_FORCE_FRAME 0x238c5cUL 859 #define TMLD_REG_DBG_SELECT 0x4d1600UL 860 #define TMLD_REG_DBG_DWORD_ENABLE 0x4d1604UL 861 #define TMLD_REG_DBG_SHIFT 0x4d1608UL 862 #define TMLD_REG_DBG_FORCE_VALID 0x4d160cUL 863 #define TMLD_REG_DBG_FORCE_FRAME 0x4d1610UL 864 #define MULD_REG_DBG_SELECT 0x4e1600UL 865 #define MULD_REG_DBG_DWORD_ENABLE 0x4e1604UL 866 #define MULD_REG_DBG_SHIFT 0x4e1608UL 867 #define MULD_REG_DBG_FORCE_VALID 0x4e160cUL 868 #define MULD_REG_DBG_FORCE_FRAME 0x4e1610UL 869 #define YULD_REG_DBG_SELECT 0x4c9600UL 870 #define YULD_REG_DBG_DWORD_ENABLE 0x4c9604UL 871 #define YULD_REG_DBG_SHIFT 0x4c9608UL 872 #define YULD_REG_DBG_FORCE_VALID 0x4c960cUL 873 #define YULD_REG_DBG_FORCE_FRAME 0x4c9610UL 874 #define XYLD_REG_DBG_SELECT 0x4c1600UL 875 #define XYLD_REG_DBG_DWORD_ENABLE 0x4c1604UL 876 #define XYLD_REG_DBG_SHIFT 0x4c1608UL 877 #define XYLD_REG_DBG_FORCE_VALID 0x4c160cUL 878 #define XYLD_REG_DBG_FORCE_FRAME 0x4c1610UL 879 #define PRM_REG_DBG_SELECT 0x2306a8UL 880 #define PRM_REG_DBG_DWORD_ENABLE 0x2306acUL 881 #define PRM_REG_DBG_SHIFT 0x2306b0UL 882 #define PRM_REG_DBG_FORCE_VALID 0x2306b4UL 883 #define PRM_REG_DBG_FORCE_FRAME 0x2306b8UL 884 #define PBF_PB1_REG_DBG_SELECT 0xda0728UL 885 #define PBF_PB1_REG_DBG_DWORD_ENABLE 0xda072cUL 886 #define PBF_PB1_REG_DBG_SHIFT 0xda0730UL 887 #define PBF_PB1_REG_DBG_FORCE_VALID 0xda0734UL 888 #define PBF_PB1_REG_DBG_FORCE_FRAME 0xda0738UL 889 #define PBF_PB2_REG_DBG_SELECT 0xda4728UL 890 #define PBF_PB2_REG_DBG_DWORD_ENABLE 0xda472cUL 891 #define PBF_PB2_REG_DBG_SHIFT 0xda4730UL 892 #define PBF_PB2_REG_DBG_FORCE_VALID 0xda4734UL 893 #define PBF_PB2_REG_DBG_FORCE_FRAME 0xda4738UL 894 #define RPB_REG_DBG_SELECT 0x23c728UL 895 #define RPB_REG_DBG_DWORD_ENABLE 0x23c72cUL 896 #define RPB_REG_DBG_SHIFT 0x23c730UL 897 #define RPB_REG_DBG_FORCE_VALID 0x23c734UL 898 #define RPB_REG_DBG_FORCE_FRAME 0x23c738UL 899 #define BTB_REG_DBG_SELECT 0xdb08c8UL 900 #define BTB_REG_DBG_DWORD_ENABLE 0xdb08ccUL 901 #define BTB_REG_DBG_SHIFT 0xdb08d0UL 902 #define BTB_REG_DBG_FORCE_VALID 0xdb08d4UL 903 #define BTB_REG_DBG_FORCE_FRAME 0xdb08d8UL 904 #define PBF_REG_DBG_SELECT 0xd80060UL 905 #define PBF_REG_DBG_DWORD_ENABLE 0xd80064UL 906 #define PBF_REG_DBG_SHIFT 0xd80068UL 907 #define PBF_REG_DBG_FORCE_VALID 0xd8006cUL 908 #define PBF_REG_DBG_FORCE_FRAME 0xd80070UL 909 #define RDIF_REG_DBG_SELECT 0x300500UL 910 #define RDIF_REG_DBG_DWORD_ENABLE 0x300504UL 911 #define RDIF_REG_DBG_SHIFT 0x300508UL 912 #define RDIF_REG_DBG_FORCE_VALID 0x30050cUL 913 #define RDIF_REG_DBG_FORCE_FRAME 0x300510UL 914 #define TDIF_REG_DBG_SELECT 0x310500UL 915 #define TDIF_REG_DBG_DWORD_ENABLE 0x310504UL 916 #define TDIF_REG_DBG_SHIFT 0x310508UL 917 #define TDIF_REG_DBG_FORCE_VALID 0x31050cUL 918 #define TDIF_REG_DBG_FORCE_FRAME 0x310510UL 919 #define CDU_REG_DBG_SELECT 0x580704UL 920 #define CDU_REG_DBG_DWORD_ENABLE 0x580708UL 921 #define CDU_REG_DBG_SHIFT 0x58070cUL 922 #define CDU_REG_DBG_FORCE_VALID 0x580710UL 923 #define CDU_REG_DBG_FORCE_FRAME 0x580714UL 924 #define CCFC_REG_DBG_SELECT 0x2e0500UL 925 #define CCFC_REG_DBG_DWORD_ENABLE 0x2e0504UL 926 #define CCFC_REG_DBG_SHIFT 0x2e0508UL 927 #define CCFC_REG_DBG_FORCE_VALID 0x2e050cUL 928 #define CCFC_REG_DBG_FORCE_FRAME 0x2e0510UL 929 #define TCFC_REG_DBG_SELECT 0x2d0500UL 930 #define TCFC_REG_DBG_DWORD_ENABLE 0x2d0504UL 931 #define TCFC_REG_DBG_SHIFT 0x2d0508UL 932 #define TCFC_REG_DBG_FORCE_VALID 0x2d050cUL 933 #define TCFC_REG_DBG_FORCE_FRAME 0x2d0510UL 934 #define IGU_REG_DBG_SELECT 0x181578UL 935 #define IGU_REG_DBG_DWORD_ENABLE 0x18157cUL 936 #define IGU_REG_DBG_SHIFT 0x181580UL 937 #define IGU_REG_DBG_FORCE_VALID 0x181584UL 938 #define IGU_REG_DBG_FORCE_FRAME 0x181588UL 939 #define CAU_REG_DBG_SELECT 0x1c0ea8UL 940 #define CAU_REG_DBG_DWORD_ENABLE 0x1c0eacUL 941 #define CAU_REG_DBG_SHIFT 0x1c0eb0UL 942 #define CAU_REG_DBG_FORCE_VALID 0x1c0eb4UL 943 #define CAU_REG_DBG_FORCE_FRAME 0x1c0eb8UL 944 #define UMAC_REG_DBG_SELECT 0x051094UL 945 #define UMAC_REG_DBG_DWORD_ENABLE 0x051098UL 946 #define UMAC_REG_DBG_SHIFT 0x05109cUL 947 #define UMAC_REG_DBG_FORCE_VALID 0x0510a0UL 948 #define UMAC_REG_DBG_FORCE_FRAME 0x0510a4UL 949 #define NIG_REG_DBG_SELECT 0x502140UL 950 #define NIG_REG_DBG_DWORD_ENABLE 0x502144UL 951 #define NIG_REG_DBG_SHIFT 0x502148UL 952 #define NIG_REG_DBG_FORCE_VALID 0x50214cUL 953 #define NIG_REG_DBG_FORCE_FRAME 0x502150UL 954 #define WOL_REG_DBG_SELECT 0x600140UL 955 #define WOL_REG_DBG_DWORD_ENABLE 0x600144UL 956 #define WOL_REG_DBG_SHIFT 0x600148UL 957 #define WOL_REG_DBG_FORCE_VALID 0x60014cUL 958 #define WOL_REG_DBG_FORCE_FRAME 0x600150UL 959 #define BMBN_REG_DBG_SELECT 0x610140UL 960 #define BMBN_REG_DBG_DWORD_ENABLE 0x610144UL 961 #define BMBN_REG_DBG_SHIFT 0x610148UL 962 #define BMBN_REG_DBG_FORCE_VALID 0x61014cUL 963 #define BMBN_REG_DBG_FORCE_FRAME 0x610150UL 964 #define NWM_REG_DBG_SELECT 0x8000ecUL 965 #define NWM_REG_DBG_DWORD_ENABLE 0x8000f0UL 966 #define NWM_REG_DBG_SHIFT 0x8000f4UL 967 #define NWM_REG_DBG_FORCE_VALID 0x8000f8UL 968 #define NWM_REG_DBG_FORCE_FRAME 0x8000fcUL 969 #define BRB_REG_BIG_RAM_ADDRESS 0x340800UL 970 #define BRB_REG_BIG_RAM_DATA 0x341500UL 971 #define BTB_REG_BIG_RAM_ADDRESS 0xdb0800UL 972 #define BTB_REG_BIG_RAM_DATA 0xdb0c00UL 973 #define BMB_REG_BIG_RAM_ADDRESS 0x540800UL 974 #define BMB_REG_BIG_RAM_DATA 0x540f00UL 975 #define MISCS_REG_RESET_PL_UA 0x009050UL 976 #define MISC_REG_RESET_PL_UA 0x008050UL 977 #define MISC_REG_RESET_PL_HV 0x008060UL 978 #define MISC_REG_RESET_PL_PDA_VMAIN_1 0x008070UL 979 #define MISC_REG_RESET_PL_PDA_VMAIN_2 0x008080UL 980 #define SEM_FAST_REG_INT_RAM 0x020000UL 981 #define DBG_REG_DBG_BLOCK_ON 0x010454UL 982 #define DBG_REG_FRAMING_MODE 0x010058UL 983 #define SEM_FAST_REG_DEBUG_MODE 0x000744UL 984 #define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL 985 #define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL 986 #define SEM_FAST_REG_FILTER_CID 0x000754UL 987 #define SEM_FAST_REG_EVENT_ID_RANGE_STRT 0x000760UL 988 #define SEM_FAST_REG_EVENT_ID_RANGE_END 0x000764UL 989 #define SEM_FAST_REG_FILTER_EVENT_ID 0x000758UL 990 #define SEM_FAST_REG_EVENT_ID_MASK 0x00075cUL 991 #define SEM_FAST_REG_RECORD_FILTER_ENABLE 0x000768UL 992 #define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE 0x000750UL 993 #define SEM_FAST_REG_DEBUG_ACTIVE 0x000740UL 994 #define SEM_FAST_REG_RECORD_FILTER_ENABLE 0x000768UL 995 #define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL 996 #define DBG_REG_FILTER_ENABLE 0x0109d0UL 997 #define DBG_REG_TRIGGER_ENABLE 0x01054cUL 998 #define DBG_REG_FILTER_CNSTR_OPRTN_0 0x010a28UL 999 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0 0x01071cUL 1000 #define DBG_REG_FILTER_CNSTR_DATA_0 0x0109d8UL 1001 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0 0x01059cUL 1002 #define DBG_REG_FILTER_CNSTR_DATA_MASK_0 0x0109f8UL 1003 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0 0x01065cUL 1004 #define DBG_REG_FILTER_CNSTR_FRAME_0 0x0109e8UL 1005 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0 0x0105fcUL 1006 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_0 0x010a08UL 1007 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0 0x0106bcUL 1008 #define DBG_REG_FILTER_CNSTR_OFFSET_0 0x010a18UL 1009 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0 0x0107dcUL 1010 #define DBG_REG_FILTER_CNSTR_RANGE_0 0x010a38UL 1011 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0 0x01077cUL 1012 #define DBG_REG_FILTER_CNSTR_CYCLIC_0 0x010a68UL 1013 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0 0x0108fcUL 1014 #define DBG_REG_FILTER_CNSTR_MUST_0 0x010a48UL 1015 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0 0x01083cUL 1016 #define DBG_REG_INTR_BUFFER 0x014000UL 1017 #define DBG_REG_INTR_BUFFER_WR_PTR 0x010404UL 1018 #define DBG_REG_WRAP_ON_INT_BUFFER 0x010418UL 1019 #define DBG_REG_INTR_BUFFER_RD_PTR 0x010400UL 1020 #define DBG_REG_EXT_BUFFER_WR_PTR 0x010410UL 1021 #define DBG_REG_WRAP_ON_EXT_BUFFER 0x01041cUL 1022 #define SEM_FAST_REG_STALL_0 0x000488UL 1023 #define SEM_FAST_REG_STALLED 0x000494UL 1024 #define SEM_FAST_REG_STORM_REG_FILE 0x008000UL 1025 #define SEM_FAST_REG_VFC_DATA_WR 0x000b40UL 1026 #define SEM_FAST_REG_VFC_ADDR 0x000b44UL 1027 #define SEM_FAST_REG_VFC_DATA_RD 0x000b48UL 1028 #define SEM_FAST_REG_VFC_DATA_WR 0x000b40UL 1029 #define SEM_FAST_REG_VFC_ADDR 0x000b44UL 1030 #define SEM_FAST_REG_VFC_DATA_RD 0x000b48UL 1031 #define RSS_REG_RSS_RAM_ADDR 0x238c30UL 1032 #define RSS_REG_RSS_RAM_DATA 0x238c20UL 1033 #define MISCS_REG_BLOCK_256B_EN 0x009074UL 1034 #define MCP_REG_CPU_REG_FILE 0xe05200UL 1035 #define MCP_REG_CPU_REG_FILE_SIZE 32 1036 #define DBG_REG_CALENDAR_OUT_DATA 0x010480UL 1037 #define DBG_REG_FULL_MODE 0x010060UL 1038 #define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_LSB 0x010430UL 1039 #define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_MSB 0x010434UL 1040 #define DBG_REG_TARGET_PACKET_SIZE 0x010b3cUL 1041 #define DBG_REG_PCI_EXT_BUFFER_SIZE 0x010438UL 1042 #define DBG_REG_PCI_FUNC_NUM 0x010a98UL 1043 #define DBG_REG_PCI_LOGIC_ADDR 0x010460UL 1044 #define DBG_REG_PCI_REQ_CREDIT 0x010440UL 1045 #define DBG_REG_DEBUG_TARGET 0x01005cUL 1046 #define DBG_REG_OUTPUT_ENABLE 0x01000cUL 1047 #define DBG_REG_OUTPUT_ENABLE 0x01000cUL 1048 #define DBG_REG_DEBUG_TARGET 0x01005cUL 1049 #define DBG_REG_OTHER_ENGINE_MODE 0x010010UL 1050 #define NIG_REG_DEBUG_PORT 0x5020d0UL 1051 #define DBG_REG_ETHERNET_HDR_WIDTH 0x010b38UL 1052 #define DBG_REG_ETHERNET_HDR_7 0x010b34UL 1053 #define DBG_REG_ETHERNET_HDR_6 0x010b30UL 1054 #define DBG_REG_ETHERNET_HDR_5 0x010b2cUL 1055 #define DBG_REG_ETHERNET_HDR_4 0x010b28UL 1056 #define DBG_REG_TARGET_PACKET_SIZE 0x010b3cUL 1057 #define DBG_REG_NIG_DATA_LIMIT_SIZE 0x01043cUL 1058 #define DBG_REG_TIMESTAMP_VALID_EN 0x010b58UL 1059 #define DBG_REG_TIMESTAMP_FRAME_EN 0x010b54UL 1060 #define DBG_REG_TIMESTAMP_TICK 0x010b50UL 1061 #define DBG_REG_FILTER_ID_NUM 0x0109d4UL 1062 #define DBG_REG_FILTER_MSG_LENGTH_ENABLE 0x010a78UL 1063 #define DBG_REG_FILTER_MSG_LENGTH 0x010a7cUL 1064 #define DBG_REG_RCRD_ON_WINDOW_PRE_NUM_CHUNKS 0x010a90UL 1065 #define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES 0x010a94UL 1066 #define DBG_REG_RCRD_ON_WINDOW_PRE_TRGR_EVNT_MODE 0x010a88UL 1067 #define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE 0x010a8cUL 1068 #define DBG_REG_TRIGGER_ENABLE 0x01054cUL 1069 #define DBG_REG_TRIGGER_STATE_ID_0 0x010554UL 1070 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0 0x01095cUL 1071 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0 0x010968UL 1072 #define DBG_REG_TRIGGER_STATE_SET_COUNT_0 0x010584UL 1073 #define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0 0x01056cUL 1074 #define DBG_REG_NO_GRANT_ON_FULL 0x010458UL 1075 #define DBG_REG_STORM_ID_NUM 0x010b14UL 1076 #define DBG_REG_CALENDAR_SLOT0 0x010014UL 1077 #define DBG_REG_HW_ID_NUM 0x010b10UL 1078 #define DBG_REG_FILTER_ENABLE 0x0109d0UL 1079 #define DBG_REG_TIMESTAMP 0x010b4cUL 1080 #define DBG_REG_CPU_TIMEOUT 0x010450UL 1081 #define DBG_REG_TRIGGER_STATUS_CUR_STATE 0x010b60UL 1082 #define GRC_REG_TRACE_FIFO_VALID_DATA 0x050064UL 1083 #define GRC_REG_TRACE_FIFO 0x050068UL 1084 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x181530UL 1085 #define IGU_REG_ERROR_HANDLING_MEMORY 0x181520UL 1086 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW 0x05040cUL 1087 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW 0x05040cUL 1088 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW 0x050500UL 1089 #define TSEM_REG_VF_ERROR 0x1700408UL 1090 #define USEM_REG_VF_ERROR 0x1900408UL 1091 #define MSEM_REG_VF_ERROR 0x1800408UL 1092 #define XSEM_REG_VF_ERROR 0x1400408UL 1093 #define YSEM_REG_VF_ERROR 0x1500408UL 1094 #define PSEM_REG_VF_ERROR 0x1600408UL 1095 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x2aa118UL 1096 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT 0x180408UL 1097 #define IGU_REG_VF_CONFIGURATION 0x180804UL 1098 #define PSWHST_REG_ZONE_PERMISSION_TABLE 0x2a0800UL 1099 #define DORQ_REG_VF_USAGE_CNT 0x1009c4UL 1100 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 0xd806ccUL 1101 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 0xd806c8UL 1102 #define PRS_REG_MSG_CT_MAIN_0 0x1f0a24UL 1103 #define PRS_REG_MSG_CT_LB_0 0x1f0a28UL 1104 #define BRB_REG_PER_TC_COUNTERS 0x341a00UL 1105 1106 /* added */ 1107 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL 1108 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL 1109 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL 1110 #define MISCS_REG_FUNCTION_HIDE 0x0096f0UL 1111 #define PCIE_REG_PRTY_MASK 0x0547b4UL 1112 #define PGLUE_B_REG_VF_BAR0_SIZE 0x2aaeb4UL 1113 #define BAR0_MAP_REG_YSDM_RAM 0x1e80000UL 1114 #define SEM_FAST_REG_INT_RAM_SIZE 20480 1115 #define MCP_REG_SCRATCH_SIZE 57344 1116 1117 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 24 1118 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 24 1119 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 16 1120 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS 0x100a1cUL 1121 1122 /* 8.10.9.0 FW */ 1123 #define NIG_REG_VXLAN_CTRL 0x50105cUL 1124 #define PRS_REG_SEARCH_ROCE 0x1f040cUL 1125 #define PRS_REG_CM_HDR_GFT 0x1f11c8UL 1126 #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0 1127 #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8 1128 #define CCFC_REG_WEAK_ENABLE_VF 0x2e0704UL 1129 #define TCFC_REG_STRONG_ENABLE_VF 0x2d070cUL 1130 #define TCFC_REG_WEAK_ENABLE_VF 0x2d0704UL 1131 #define PRS_REG_SEARCH_GFT 0x1f11bcUL 1132 #define PRS_REG_LOAD_L2_FILTER 0x1f0198UL 1133 #define PRS_REG_GFT_CAM 0x1f1100UL 1134 #define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL 1135 #define PGLUE_B_REG_MSDM_VF_SHIFT_B 0x2aa1c4UL 1136 #define PGLUE_B_REG_MSDM_OFFSET_MASK_B 0x2aa1c0UL 1137 #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST 0x1f0a0cUL 1138 #define PRS_REG_SEARCH_FCOE 0x1f0408UL 1139 #define PGLUE_B_REG_PGL_ADDR_E8_F0 0x2aaf98UL 1140 #define NIG_REG_DSCP_TO_TC_MAP_ENABLE 0x5088f8UL 1141 #define PGLUE_B_REG_PGL_ADDR_EC_F0 0x2aaf9cUL 1142 #define PGLUE_B_REG_PGL_ADDR_F0_F0 0x2aafa0UL 1143 #define PRS_REG_ROCE_DEST_QP_MAX_PF 0x1f0430UL 1144 #define PGLUE_B_REG_PGL_ADDR_F4_F0 0x2aafa4UL 1145 #define IGU_REG_WRITE_DONE_PENDING 0x180900UL 1146 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR 0x50196cUL 1147 #define PRS_REG_MSG_INFO 0x1f0a1cUL 1148 #define BAR0_MAP_REG_XSDM_RAM 0x1e00000UL 1149 1150 /* 8.18.7.0 FW */ 1151 #define BRB_REG_INT_MASK_10 0x3401b8UL 1152 1153 #define IGU_REG_PRODUCER_MEMORY 0x182000UL 1154 #define IGU_REG_CONSUMER_MEM 0x183000UL 1155 1156 #define CDU_REG_CCFC_CTX_VALID0 0x580400UL 1157 #define CDU_REG_CCFC_CTX_VALID1 0x580404UL 1158 #define CDU_REG_TCFC_CTX_VALID0 0x580408UL 1159 1160 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL 1161 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL 1162 #define MISCS_REG_RESET_PL_HV_2_K2_E5 0x009150UL 1163 #define CNIG_REG_NW_PORT_MODE_BB 0x218200UL 1164 #define CNIG_REG_PMEG_IF_CMD_BB 0x21821cUL 1165 #define CNIG_REG_PMEG_IF_ADDR_BB 0x218224UL 1166 #define CNIG_REG_PMEG_IF_WRDATA_BB 0x218228UL 1167 #define NWM_REG_MAC0_K2_E5 0x800400UL 1168 #define CNIG_REG_NIG_PORT0_CONF_K2_E5 0x218200UL 1169 #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_K2_E5_SHIFT 0 1170 #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_K2_E5_SHIFT 1 1171 #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_K2_E5_SHIFT 3 1172 #define ETH_MAC_REG_XIF_MODE_K2_E5 0x000080UL 1173 #define ETH_MAC_REG_XIF_MODE_XGMII_K2_E5_SHIFT 0 1174 #define ETH_MAC_REG_FRM_LENGTH_K2_E5 0x000014UL 1175 #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_K2_E5_SHIFT 0 1176 #define ETH_MAC_REG_TX_IPG_LENGTH_K2_E5 0x000044UL 1177 #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_K2_E5_SHIFT 0 1178 #define ETH_MAC_REG_RX_FIFO_SECTIONS_K2_E5 0x00001cUL 1179 #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_K2_E5_SHIFT 0 1180 #define ETH_MAC_REG_TX_FIFO_SECTIONS_K2_E5 0x000020UL 1181 #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_K2_E5_SHIFT 16 1182 #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_K2_E5_SHIFT 0 1183 #define ETH_MAC_REG_COMMAND_CONFIG_K2_E5 0x000008UL 1184 #define MISC_REG_XMAC_CORE_PORT_MODE_BB 0x008c08UL 1185 #define MISC_REG_XMAC_PHY_PORT_MODE_BB 0x008c04UL 1186 #define XMAC_REG_MODE_BB 0x210008UL 1187 #define XMAC_REG_RX_MAX_SIZE_BB 0x210040UL 1188 #define XMAC_REG_TX_CTRL_LO_BB 0x210020UL 1189 #define XMAC_REG_CTRL_BB 0x210000UL 1190 #define XMAC_REG_CTRL_TX_EN_BB (0x1UL << 0) 1191 #define XMAC_REG_CTRL_RX_EN_BB (0x1UL << 1) 1192 #define XMAC_REG_RX_CTRL_BB 0x210030UL 1193 #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_BB (0x1UL << 12) 1194 1195 #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2_E5 0x2aaf98UL 1196 #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2_E5 0x2aaf9cUL 1197 #define PGLUE_B_REG_PGL_ADDR_F0_F0_K2_E5 0x2aafa0UL 1198 #define PGLUE_B_REG_PGL_ADDR_F4_F0_K2_E5 0x2aafa4UL 1199 #define PGLUE_B_REG_PGL_ADDR_88_F0_BB 0x2aa404UL 1200 #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB 0x2aa408UL 1201 #define PGLUE_B_REG_PGL_ADDR_90_F0_BB 0x2aa40cUL 1202 #define PGLUE_B_REG_PGL_ADDR_94_F0_BB 0x2aa410UL 1203 #define MISCS_REG_FUNCTION_HIDE_BB_K2 0x0096f0UL 1204 #define PCIE_REG_PRTY_MASK_K2_E5 0x0547b4UL 1205 #define PGLUE_B_REG_VF_BAR0_SIZE_K2_E5 0x2aaeb4UL 1206 1207 #define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL 1208 1209 #define NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 0x501a00UL 1210 #define NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 0x501a80UL 1211 #define NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 0x501ac0UL 1212 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 0x501b00UL 1213 1214 #define PSWRQ2_REG_WR_MBS0 0x240400UL 1215 #define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL 1216 #define DORQ_REG_PF_USAGE_CNT 0x1009c0UL 1217 #define DORQ_REG_DPM_FORCE_ABORT 0x1009d8UL 1218 #define DORQ_REG_PF_OVFL_STICKY 0x1009d0UL 1219 #define DORQ_REG_INT_STS 0x100180UL 1220 #define DORQ_REG_INT_STS_DB_DROP (0x1UL << 1) 1221 #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR (0x1UL << 2) 1222 #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL (0x1UL << 3) 1223 #define DORQ_REG_DB_DROP_DETAILS_REL 0x100a28UL 1224 #define DORQ_REG_INT_STS_WR 0x100188UL 1225 #define DORQ_REG_DB_DROP_DETAILS_REASON 0x100a20UL 1226 #define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL 1227 #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10) 1228 #define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL 1229 #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL 1230 1231 #define RSS_REG_RSS_RAM_MASK 0x238c10UL 1232 1233 #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL 1234 #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL 1235 #define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL 1236 #define DORQ_REG_PF_PCP_BB_K2 0x1008c4UL 1237 #define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL 1238 #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL 1239 #define NIG_REG_LLH_PPFID2PFID_TBL_0 0x501970UL 1240 #define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL 1241 #define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL 0x501b98UL 1242 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 0x501b40UL 1243