1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #include "bcm_osal.h" 8 #include "ecore.h" 9 #include "ecore_sp_commands.h" 10 #include "ecore_dcbx.h" 11 #include "ecore_cxt.h" 12 #include "ecore_gtt_reg_addr.h" 13 #include "ecore_iro.h" 14 #include "ecore_iov_api.h" 15 16 #define ECORE_DCBX_MAX_MIB_READ_TRY (100) 17 #define ECORE_ETH_TYPE_DEFAULT (0) 18 19 #define ECORE_DCBX_INVALID_PRIORITY 0xFF 20 21 /* Get Traffic Class from priority traffic class table, 4 bits represent 22 * the traffic class corresponding to the priority. 23 */ 24 #define ECORE_DCBX_PRIO2TC(prio_tc_tbl, prio) \ 25 ((u32)(prio_tc_tbl >> ((7 - prio) * 4)) & 0x7) 26 27 static bool ecore_dcbx_app_ethtype(u32 app_info_bitmap) 28 { 29 return !!(GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF) == 30 DCBX_APP_SF_ETHTYPE); 31 } 32 33 static bool ecore_dcbx_ieee_app_ethtype(u32 app_info_bitmap) 34 { 35 u8 mfw_val = GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE); 36 37 /* Old MFW */ 38 if (mfw_val == DCBX_APP_SF_IEEE_RESERVED) 39 return ecore_dcbx_app_ethtype(app_info_bitmap); 40 41 return !!(mfw_val == DCBX_APP_SF_IEEE_ETHTYPE); 42 } 43 44 static bool ecore_dcbx_app_port(u32 app_info_bitmap) 45 { 46 return !!(GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF) == 47 DCBX_APP_SF_PORT); 48 } 49 50 static bool ecore_dcbx_ieee_app_port(u32 app_info_bitmap, u8 type) 51 { 52 u8 mfw_val = GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE); 53 54 /* Old MFW */ 55 if (mfw_val == DCBX_APP_SF_IEEE_RESERVED) 56 return ecore_dcbx_app_port(app_info_bitmap); 57 58 return !!(mfw_val == type || mfw_val == DCBX_APP_SF_IEEE_TCP_UDP_PORT); 59 } 60 61 static bool ecore_dcbx_default_tlv(u32 app_info_bitmap, u16 proto_id, bool ieee) 62 { 63 bool ethtype; 64 65 if (ieee) 66 ethtype = ecore_dcbx_ieee_app_ethtype(app_info_bitmap); 67 else 68 ethtype = ecore_dcbx_app_ethtype(app_info_bitmap); 69 70 return !!(ethtype && (proto_id == ECORE_ETH_TYPE_DEFAULT)); 71 } 72 73 static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap, 74 u16 proto_id, bool ieee) 75 { 76 bool port; 77 78 if (!p_hwfn->p_dcbx_info->iwarp_port) 79 return false; 80 81 if (ieee) 82 port = ecore_dcbx_ieee_app_port(app_info_bitmap, 83 DCBX_APP_SF_IEEE_TCP_PORT); 84 else 85 port = ecore_dcbx_app_port(app_info_bitmap); 86 87 return !!(port && (proto_id == p_hwfn->p_dcbx_info->iwarp_port)); 88 } 89 90 static void 91 ecore_dcbx_dp_protocol(struct ecore_hwfn *p_hwfn, 92 struct ecore_dcbx_results *p_data) 93 { 94 enum dcbx_protocol_type id; 95 int i; 96 97 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "DCBX negotiated: %d\n", 98 p_data->dcbx_enabled); 99 100 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) { 101 id = ecore_dcbx_app_update[i].id; 102 103 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 104 "%s info: update %d, enable %d, prio %d, tc %d," 105 " num_active_tc %d dscp_enable = %d dscp_val = %d\n", 106 ecore_dcbx_app_update[i].name, 107 p_data->arr[id].update, 108 p_data->arr[id].enable, p_data->arr[id].priority, 109 p_data->arr[id].tc, p_hwfn->hw_info.num_active_tc, 110 p_data->arr[id].dscp_enable, 111 p_data->arr[id].dscp_val); 112 } 113 } 114 115 u8 ecore_dcbx_get_dscp_value(struct ecore_hwfn *p_hwfn, u8 pri) 116 { 117 struct ecore_dcbx_dscp_params *dscp = &p_hwfn->p_dcbx_info->get.dscp; 118 u8 i; 119 120 if (!dscp->enabled) 121 return ECORE_DCBX_DSCP_DISABLED; 122 123 for (i = 0; i < ECORE_DCBX_DSCP_SIZE; i++) 124 if (pri == dscp->dscp_pri_map[i]) 125 return i; 126 127 return ECORE_DCBX_DSCP_DISABLED; 128 } 129 130 static void 131 ecore_dcbx_set_params(struct ecore_dcbx_results *p_data, 132 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 133 bool enable, u8 prio, u8 tc, 134 enum dcbx_protocol_type type, 135 enum ecore_pci_personality personality) 136 { 137 /* PF update ramrod data */ 138 p_data->arr[type].enable = enable; 139 p_data->arr[type].priority = prio; 140 p_data->arr[type].tc = tc; 141 p_data->arr[type].dscp_val = ecore_dcbx_get_dscp_value(p_hwfn, prio); 142 if (p_data->arr[type].dscp_val == ECORE_DCBX_DSCP_DISABLED) { 143 p_data->arr[type].dscp_enable = false; 144 p_data->arr[type].dscp_val = 0; 145 } else { 146 p_data->arr[type].dscp_enable = true; 147 } 148 p_data->arr[type].update = UPDATE_DCB_DSCP; 149 150 /* Do not add valn tag 0 when DCB is enabled and port is in UFP mode */ 151 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) 152 p_data->arr[type].dont_add_vlan0 = true; 153 154 /* QM reconf data */ 155 if (p_hwfn->hw_info.personality == personality) 156 p_hwfn->hw_info.offload_tc = tc; 157 158 /* Configure dcbx vlan priority in doorbell block for roce EDPM */ 159 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) && 160 (type == DCBX_PROTOCOL_ROCE)) { 161 ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1); 162 ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_PCP_BB_K2, prio << 1); 163 } 164 } 165 166 /* Update app protocol data and hw_info fields with the TLV info */ 167 static void 168 ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data, 169 struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 170 bool enable, u8 prio, u8 tc, 171 enum dcbx_protocol_type type) 172 { 173 enum ecore_pci_personality personality; 174 enum dcbx_protocol_type id; 175 int i; 176 177 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) { 178 id = ecore_dcbx_app_update[i].id; 179 180 if (type != id) 181 continue; 182 183 personality = ecore_dcbx_app_update[i].personality; 184 185 ecore_dcbx_set_params(p_data, p_hwfn, p_ptt, enable, 186 prio, tc, type, personality); 187 } 188 } 189 190 static enum _ecore_status_t 191 ecore_dcbx_get_app_priority(u8 pri_bitmap, u8 *priority) 192 { 193 u32 pri_mask, pri = ECORE_MAX_PFC_PRIORITIES; 194 u32 index = ECORE_MAX_PFC_PRIORITIES - 1; 195 enum _ecore_status_t rc = ECORE_SUCCESS; 196 197 /* Bitmap 1 corresponds to priority 0, return priority 0 */ 198 if (pri_bitmap == 1) { 199 *priority = 0; 200 return rc; 201 } 202 203 /* Choose the highest priority */ 204 while ((pri == ECORE_MAX_PFC_PRIORITIES) && index) { 205 pri_mask = 1 << index; 206 if (pri_bitmap & pri_mask) 207 pri = index; 208 index--; 209 } 210 211 if (pri < ECORE_MAX_PFC_PRIORITIES) 212 *priority = (u8)pri; 213 else 214 rc = ECORE_INVAL; 215 216 return rc; 217 } 218 219 static bool 220 ecore_dcbx_get_app_protocol_type(struct ecore_hwfn *p_hwfn, 221 u32 app_prio_bitmap, u16 id, 222 enum dcbx_protocol_type *type, bool ieee) 223 { 224 if (ecore_dcbx_default_tlv(app_prio_bitmap, id, ieee)) { 225 *type = DCBX_PROTOCOL_ETH; 226 } else { 227 *type = DCBX_MAX_PROTOCOL_TYPE; 228 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 229 "No action required, App TLV entry = 0x%x\n", 230 app_prio_bitmap); 231 return false; 232 } 233 234 return true; 235 } 236 237 /* Parse app TLV's to update TC information in hw_info structure for 238 * reconfiguring QM. Get protocol specific data for PF update ramrod command. 239 */ 240 static enum _ecore_status_t 241 ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 242 struct ecore_dcbx_results *p_data, 243 struct dcbx_app_priority_entry *p_tbl, u32 pri_tc_tbl, 244 int count, u8 dcbx_version) 245 { 246 enum dcbx_protocol_type type; 247 bool enable, ieee, eth_tlv; 248 u8 tc, priority_map; 249 u16 protocol_id; 250 u8 priority; 251 enum _ecore_status_t rc = ECORE_SUCCESS; 252 int i; 253 254 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 255 "Num APP entries = %d pri_tc_tbl = 0x%x dcbx_version = %u\n", 256 count, pri_tc_tbl, dcbx_version); 257 258 ieee = (dcbx_version == DCBX_CONFIG_VERSION_IEEE); 259 eth_tlv = false; 260 /* Parse APP TLV */ 261 for (i = 0; i < count; i++) { 262 protocol_id = GET_MFW_FIELD(p_tbl[i].entry, 263 DCBX_APP_PROTOCOL_ID); 264 priority_map = GET_MFW_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP); 265 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Id = 0x%x pri_map = %u\n", 266 protocol_id, priority_map); 267 rc = ecore_dcbx_get_app_priority(priority_map, &priority); 268 if (rc == ECORE_INVAL) { 269 DP_ERR(p_hwfn, "Invalid priority\n"); 270 return ECORE_INVAL; 271 } 272 273 tc = ECORE_DCBX_PRIO2TC(pri_tc_tbl, priority); 274 if (ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry, 275 protocol_id, &type, 276 ieee)) { 277 /* ETH always have the enable bit reset, as it gets 278 * vlan information per packet. For other protocols, 279 * should be set according to the dcbx_enabled 280 * indication, but we only got here if there was an 281 * app tlv for the protocol, so dcbx must be enabled. 282 */ 283 if (type == DCBX_PROTOCOL_ETH) { 284 enable = false; 285 eth_tlv = true; 286 } else { 287 enable = true; 288 } 289 290 ecore_dcbx_update_app_info(p_data, p_hwfn, p_ptt, 291 enable, priority, tc, type); 292 } 293 } 294 295 /* If Eth TLV is not detected, use UFP TC as default TC */ 296 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, 297 &p_hwfn->p_dev->mf_bits) && !eth_tlv) 298 p_data->arr[DCBX_PROTOCOL_ETH].tc = p_hwfn->ufp_info.tc; 299 300 /* Update ramrod protocol data and hw_info fields 301 * with default info when corresponding APP TLV's are not detected. 302 * The enabled field has a different logic for ethernet as only for 303 * ethernet dcb should disabled by default, as the information arrives 304 * from the OS (unless an explicit app tlv was present). 305 */ 306 tc = p_data->arr[DCBX_PROTOCOL_ETH].tc; 307 priority = p_data->arr[DCBX_PROTOCOL_ETH].priority; 308 for (type = 0; type < DCBX_MAX_PROTOCOL_TYPE; type++) { 309 if (p_data->arr[type].update) 310 continue; 311 312 /* if no app tlv was present, don't override in FW */ 313 ecore_dcbx_update_app_info(p_data, p_hwfn, p_ptt, false, 314 priority, tc, type); 315 } 316 317 return ECORE_SUCCESS; 318 } 319 320 /* Parse app TLV's to update TC information in hw_info structure for 321 * reconfiguring QM. Get protocol specific data for PF update ramrod command. 322 */ 323 static enum _ecore_status_t 324 ecore_dcbx_process_mib_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 325 { 326 struct dcbx_app_priority_feature *p_app; 327 struct dcbx_app_priority_entry *p_tbl; 328 struct ecore_dcbx_results data; 329 struct dcbx_ets_feature *p_ets; 330 struct ecore_hw_info *p_info; 331 u32 pri_tc_tbl, flags; 332 u8 dcbx_version; 333 int num_entries; 334 enum _ecore_status_t rc = ECORE_SUCCESS; 335 336 flags = p_hwfn->p_dcbx_info->operational.flags; 337 dcbx_version = GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION); 338 339 p_app = &p_hwfn->p_dcbx_info->operational.features.app; 340 p_tbl = p_app->app_pri_tbl; 341 342 p_ets = &p_hwfn->p_dcbx_info->operational.features.ets; 343 pri_tc_tbl = p_ets->pri_tc_tbl[0]; 344 345 p_info = &p_hwfn->hw_info; 346 num_entries = GET_MFW_FIELD(p_app->flags, DCBX_APP_NUM_ENTRIES); 347 348 OSAL_MEMSET(&data, 0, sizeof(struct ecore_dcbx_results)); 349 rc = ecore_dcbx_process_tlv(p_hwfn, p_ptt, &data, p_tbl, pri_tc_tbl, 350 num_entries, dcbx_version); 351 if (rc != ECORE_SUCCESS) 352 return rc; 353 354 p_info->num_active_tc = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS); 355 p_hwfn->qm_info.ooo_tc = GET_MFW_FIELD(p_ets->flags, DCBX_OOO_TC); 356 data.pf_id = p_hwfn->rel_pf_id; 357 data.dcbx_enabled = !!dcbx_version; 358 359 ecore_dcbx_dp_protocol(p_hwfn, &data); 360 361 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->results, &data, 362 sizeof(struct ecore_dcbx_results)); 363 364 return ECORE_SUCCESS; 365 } 366 367 static enum _ecore_status_t 368 ecore_dcbx_copy_mib(struct ecore_hwfn *p_hwfn, 369 struct ecore_ptt *p_ptt, 370 struct ecore_dcbx_mib_meta_data *p_data, 371 enum ecore_mib_read_type type) 372 { 373 u32 prefix_seq_num, suffix_seq_num; 374 int read_count = 0; 375 enum _ecore_status_t rc = ECORE_SUCCESS; 376 377 /* The data is considered to be valid only if both sequence numbers are 378 * the same. 379 */ 380 do { 381 if (type == ECORE_DCBX_REMOTE_LLDP_MIB) { 382 ecore_memcpy_from(p_hwfn, p_ptt, p_data->lldp_remote, 383 p_data->addr, p_data->size); 384 prefix_seq_num = p_data->lldp_remote->prefix_seq_num; 385 suffix_seq_num = p_data->lldp_remote->suffix_seq_num; 386 } else if (type == ECORE_DCBX_LLDP_TLVS) { 387 ecore_memcpy_from(p_hwfn, p_ptt, p_data->lldp_tlvs, 388 p_data->addr, p_data->size); 389 prefix_seq_num = p_data->lldp_tlvs->prefix_seq_num; 390 suffix_seq_num = p_data->lldp_tlvs->suffix_seq_num; 391 392 } else { 393 ecore_memcpy_from(p_hwfn, p_ptt, p_data->mib, 394 p_data->addr, p_data->size); 395 prefix_seq_num = p_data->mib->prefix_seq_num; 396 suffix_seq_num = p_data->mib->suffix_seq_num; 397 } 398 read_count++; 399 400 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 401 "mib type = %d, try count = %d prefix seq num =" 402 " %d suffix seq num = %d\n", 403 type, read_count, prefix_seq_num, suffix_seq_num); 404 } while ((prefix_seq_num != suffix_seq_num) && 405 (read_count < ECORE_DCBX_MAX_MIB_READ_TRY)); 406 407 if (read_count >= ECORE_DCBX_MAX_MIB_READ_TRY) { 408 DP_ERR(p_hwfn, 409 "MIB read err, mib type = %d, try count =" 410 " %d prefix seq num = %d suffix seq num = %d\n", 411 type, read_count, prefix_seq_num, suffix_seq_num); 412 rc = ECORE_IO; 413 } 414 415 return rc; 416 } 417 418 static void 419 ecore_dcbx_get_priority_info(struct ecore_hwfn *p_hwfn, 420 struct ecore_dcbx_app_prio *p_prio, 421 struct ecore_dcbx_results *p_results) 422 { 423 u8 val; 424 425 if (p_results->arr[DCBX_PROTOCOL_ETH].update && 426 p_results->arr[DCBX_PROTOCOL_ETH].enable) 427 p_prio->eth = p_results->arr[DCBX_PROTOCOL_ETH].priority; 428 429 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 430 "Priorities: eth %d\n", 431 p_prio->eth); 432 } 433 434 static void 435 ecore_dcbx_get_app_data(struct ecore_hwfn *p_hwfn, 436 struct dcbx_app_priority_feature *p_app, 437 struct dcbx_app_priority_entry *p_tbl, 438 struct ecore_dcbx_params *p_params, bool ieee) 439 { 440 struct ecore_app_entry *entry; 441 u8 pri_map; 442 int i; 443 444 p_params->app_willing = GET_MFW_FIELD(p_app->flags, DCBX_APP_WILLING); 445 p_params->app_valid = GET_MFW_FIELD(p_app->flags, DCBX_APP_ENABLED); 446 p_params->app_error = GET_MFW_FIELD(p_app->flags, DCBX_APP_ERROR); 447 p_params->num_app_entries = GET_MFW_FIELD(p_app->flags, 448 DCBX_APP_NUM_ENTRIES); 449 for (i = 0; i < p_params->num_app_entries; i++) { 450 entry = &p_params->app_entry[i]; 451 if (ieee) { 452 u8 sf_ieee; 453 u32 val; 454 455 sf_ieee = GET_MFW_FIELD(p_tbl[i].entry, 456 DCBX_APP_SF_IEEE); 457 switch (sf_ieee) { 458 case DCBX_APP_SF_IEEE_RESERVED: 459 /* Old MFW */ 460 val = GET_MFW_FIELD(p_tbl[i].entry, 461 DCBX_APP_SF); 462 entry->sf_ieee = val ? 463 ECORE_DCBX_SF_IEEE_TCP_UDP_PORT : 464 ECORE_DCBX_SF_IEEE_ETHTYPE; 465 break; 466 case DCBX_APP_SF_IEEE_ETHTYPE: 467 entry->sf_ieee = ECORE_DCBX_SF_IEEE_ETHTYPE; 468 break; 469 case DCBX_APP_SF_IEEE_TCP_PORT: 470 entry->sf_ieee = ECORE_DCBX_SF_IEEE_TCP_PORT; 471 break; 472 case DCBX_APP_SF_IEEE_UDP_PORT: 473 entry->sf_ieee = ECORE_DCBX_SF_IEEE_UDP_PORT; 474 break; 475 case DCBX_APP_SF_IEEE_TCP_UDP_PORT: 476 entry->sf_ieee = 477 ECORE_DCBX_SF_IEEE_TCP_UDP_PORT; 478 break; 479 } 480 } else { 481 entry->ethtype = !(GET_MFW_FIELD(p_tbl[i].entry, 482 DCBX_APP_SF)); 483 } 484 485 pri_map = GET_MFW_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP); 486 ecore_dcbx_get_app_priority(pri_map, &entry->prio); 487 entry->proto_id = GET_MFW_FIELD(p_tbl[i].entry, 488 DCBX_APP_PROTOCOL_ID); 489 ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry, 490 entry->proto_id, 491 &entry->proto_type, ieee); 492 } 493 494 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 495 "APP params: willing %d, valid %d error = %d\n", 496 p_params->app_willing, p_params->app_valid, 497 p_params->app_error); 498 } 499 500 static void 501 ecore_dcbx_get_pfc_data(struct ecore_hwfn *p_hwfn, 502 u32 pfc, struct ecore_dcbx_params *p_params) 503 { 504 u8 pfc_map; 505 506 p_params->pfc.willing = GET_MFW_FIELD(pfc, DCBX_PFC_WILLING); 507 p_params->pfc.max_tc = GET_MFW_FIELD(pfc, DCBX_PFC_CAPS); 508 p_params->pfc.enabled = GET_MFW_FIELD(pfc, DCBX_PFC_ENABLED); 509 pfc_map = GET_MFW_FIELD(pfc, DCBX_PFC_PRI_EN_BITMAP); 510 p_params->pfc.prio[0] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_0); 511 p_params->pfc.prio[1] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_1); 512 p_params->pfc.prio[2] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_2); 513 p_params->pfc.prio[3] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_3); 514 p_params->pfc.prio[4] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_4); 515 p_params->pfc.prio[5] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_5); 516 p_params->pfc.prio[6] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_6); 517 p_params->pfc.prio[7] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_7); 518 519 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 520 "PFC params: willing %d, pfc_bitmap %u max_tc = %u enabled = %d\n", 521 p_params->pfc.willing, pfc_map, p_params->pfc.max_tc, 522 p_params->pfc.enabled); 523 } 524 525 static void 526 ecore_dcbx_get_ets_data(struct ecore_hwfn *p_hwfn, 527 struct dcbx_ets_feature *p_ets, 528 struct ecore_dcbx_params *p_params) 529 { 530 u32 bw_map[2], tsa_map[2], pri_map; 531 int i; 532 533 p_params->ets_willing = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_WILLING); 534 p_params->ets_enabled = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_ENABLED); 535 p_params->ets_cbs = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_CBS); 536 p_params->max_ets_tc = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS); 537 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 538 "ETS params: willing %d, enabled = %d ets_cbs %d pri_tc_tbl_0 %x max_ets_tc %d\n", 539 p_params->ets_willing, p_params->ets_enabled, 540 p_params->ets_cbs, p_ets->pri_tc_tbl[0], 541 p_params->max_ets_tc); 542 543 /* 8 bit tsa and bw data corresponding to each of the 8 TC's are 544 * encoded in a type u32 array of size 2. 545 */ 546 bw_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[0]); 547 bw_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[1]); 548 tsa_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[0]); 549 tsa_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[1]); 550 pri_map = p_ets->pri_tc_tbl[0]; 551 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) { 552 p_params->ets_tc_bw_tbl[i] = ((u8 *)bw_map)[i]; 553 p_params->ets_tc_tsa_tbl[i] = ((u8 *)tsa_map)[i]; 554 p_params->ets_pri_tc_tbl[i] = ECORE_DCBX_PRIO2TC(pri_map, i); 555 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 556 "elem %d bw_tbl %x tsa_tbl %x\n", 557 i, p_params->ets_tc_bw_tbl[i], 558 p_params->ets_tc_tsa_tbl[i]); 559 } 560 } 561 562 static void 563 ecore_dcbx_get_common_params(struct ecore_hwfn *p_hwfn, 564 struct dcbx_app_priority_feature *p_app, 565 struct dcbx_app_priority_entry *p_tbl, 566 struct dcbx_ets_feature *p_ets, 567 u32 pfc, struct ecore_dcbx_params *p_params, 568 bool ieee) 569 { 570 ecore_dcbx_get_app_data(p_hwfn, p_app, p_tbl, p_params, ieee); 571 ecore_dcbx_get_ets_data(p_hwfn, p_ets, p_params); 572 ecore_dcbx_get_pfc_data(p_hwfn, pfc, p_params); 573 } 574 575 static void 576 ecore_dcbx_get_local_params(struct ecore_hwfn *p_hwfn, 577 struct ecore_dcbx_get *params) 578 { 579 struct dcbx_features *p_feat; 580 581 p_feat = &p_hwfn->p_dcbx_info->local_admin.features; 582 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app, 583 p_feat->app.app_pri_tbl, &p_feat->ets, 584 p_feat->pfc, ¶ms->local.params, false); 585 params->local.valid = true; 586 } 587 588 static void 589 ecore_dcbx_get_remote_params(struct ecore_hwfn *p_hwfn, 590 struct ecore_dcbx_get *params) 591 { 592 struct dcbx_features *p_feat; 593 594 p_feat = &p_hwfn->p_dcbx_info->remote.features; 595 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app, 596 p_feat->app.app_pri_tbl, &p_feat->ets, 597 p_feat->pfc, ¶ms->remote.params, 598 false); 599 params->remote.valid = true; 600 } 601 602 static void ecore_dcbx_get_dscp_params(struct ecore_hwfn *p_hwfn, 603 struct ecore_dcbx_get *params) 604 { 605 struct ecore_dcbx_dscp_params *p_dscp; 606 struct dcb_dscp_map *p_dscp_map; 607 int i, j, entry; 608 u32 pri_map; 609 610 p_dscp = ¶ms->dscp; 611 p_dscp_map = &p_hwfn->p_dcbx_info->dscp_map; 612 p_dscp->enabled = GET_MFW_FIELD(p_dscp_map->flags, DCB_DSCP_ENABLE); 613 614 /* MFW encodes 64 dscp entries into 8 element array of u32 entries, 615 * where each entry holds the 4bit priority map for 8 dscp entries. 616 */ 617 for (i = 0, entry = 0; i < ECORE_DCBX_DSCP_SIZE / 8; i++) { 618 pri_map = OSAL_BE32_TO_CPU(p_dscp_map->dscp_pri_map[i]); 619 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "elem %d pri_map 0x%x\n", 620 entry, pri_map); 621 for (j = 0; j < ECORE_DCBX_DSCP_SIZE / 8; j++, entry++) 622 p_dscp->dscp_pri_map[entry] = (u32)(pri_map >> 623 (j * 4)) & 0xf; 624 } 625 } 626 627 static void 628 ecore_dcbx_get_operational_params(struct ecore_hwfn *p_hwfn, 629 struct ecore_dcbx_get *params) 630 { 631 struct ecore_dcbx_operational_params *p_operational; 632 struct ecore_dcbx_results *p_results; 633 struct dcbx_features *p_feat; 634 bool enabled, err; 635 u32 flags; 636 bool val; 637 638 flags = p_hwfn->p_dcbx_info->operational.flags; 639 640 /* If DCBx version is non zero, then negotiation 641 * was successfuly performed 642 */ 643 p_operational = ¶ms->operational; 644 enabled = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) != 645 DCBX_CONFIG_VERSION_DISABLED); 646 if (!enabled) { 647 p_operational->enabled = enabled; 648 p_operational->valid = false; 649 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Dcbx is disabled\n"); 650 return; 651 } 652 653 p_feat = &p_hwfn->p_dcbx_info->operational.features; 654 p_results = &p_hwfn->p_dcbx_info->results; 655 656 val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) == 657 DCBX_CONFIG_VERSION_IEEE); 658 p_operational->ieee = val; 659 660 val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) == 661 DCBX_CONFIG_VERSION_CEE); 662 p_operational->cee = val; 663 664 val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) == 665 DCBX_CONFIG_VERSION_STATIC); 666 p_operational->local = val; 667 668 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 669 "Version support: ieee %d, cee %d, static %d\n", 670 p_operational->ieee, p_operational->cee, 671 p_operational->local); 672 673 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app, 674 p_feat->app.app_pri_tbl, &p_feat->ets, 675 p_feat->pfc, ¶ms->operational.params, 676 p_operational->ieee); 677 ecore_dcbx_get_priority_info(p_hwfn, &p_operational->app_prio, 678 p_results); 679 err = GET_MFW_FIELD(p_feat->app.flags, DCBX_APP_ERROR); 680 p_operational->err = err; 681 p_operational->enabled = enabled; 682 p_operational->valid = true; 683 } 684 685 static void ecore_dcbx_get_local_lldp_params(struct ecore_hwfn *p_hwfn, 686 struct ecore_dcbx_get *params) 687 { 688 struct lldp_config_params_s *p_local; 689 690 p_local = &p_hwfn->p_dcbx_info->lldp_local[LLDP_NEAREST_BRIDGE]; 691 692 OSAL_MEMCPY(params->lldp_local.local_chassis_id, 693 p_local->local_chassis_id, 694 sizeof(params->lldp_local.local_chassis_id)); 695 OSAL_MEMCPY(params->lldp_local.local_port_id, p_local->local_port_id, 696 sizeof(params->lldp_local.local_port_id)); 697 } 698 699 static void ecore_dcbx_get_remote_lldp_params(struct ecore_hwfn *p_hwfn, 700 struct ecore_dcbx_get *params) 701 { 702 struct lldp_status_params_s *p_remote; 703 704 p_remote = &p_hwfn->p_dcbx_info->lldp_remote[LLDP_NEAREST_BRIDGE]; 705 706 OSAL_MEMCPY(params->lldp_remote.peer_chassis_id, 707 p_remote->peer_chassis_id, 708 sizeof(params->lldp_remote.peer_chassis_id)); 709 OSAL_MEMCPY(params->lldp_remote.peer_port_id, p_remote->peer_port_id, 710 sizeof(params->lldp_remote.peer_port_id)); 711 } 712 713 static enum _ecore_status_t 714 ecore_dcbx_get_params(struct ecore_hwfn *p_hwfn, 715 struct ecore_dcbx_get *p_params, 716 enum ecore_mib_read_type type) 717 { 718 switch (type) { 719 case ECORE_DCBX_REMOTE_MIB: 720 ecore_dcbx_get_remote_params(p_hwfn, p_params); 721 break; 722 case ECORE_DCBX_LOCAL_MIB: 723 ecore_dcbx_get_local_params(p_hwfn, p_params); 724 break; 725 case ECORE_DCBX_OPERATIONAL_MIB: 726 ecore_dcbx_get_operational_params(p_hwfn, p_params); 727 break; 728 case ECORE_DCBX_REMOTE_LLDP_MIB: 729 ecore_dcbx_get_remote_lldp_params(p_hwfn, p_params); 730 break; 731 case ECORE_DCBX_LOCAL_LLDP_MIB: 732 ecore_dcbx_get_local_lldp_params(p_hwfn, p_params); 733 break; 734 default: 735 DP_ERR(p_hwfn, "MIB read err, unknown mib type %d\n", type); 736 return ECORE_INVAL; 737 } 738 739 return ECORE_SUCCESS; 740 } 741 742 static enum _ecore_status_t 743 ecore_dcbx_read_local_lldp_mib(struct ecore_hwfn *p_hwfn, 744 struct ecore_ptt *p_ptt) 745 { 746 struct ecore_dcbx_mib_meta_data data; 747 enum _ecore_status_t rc = ECORE_SUCCESS; 748 749 OSAL_MEM_ZERO(&data, sizeof(data)); 750 data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port, 751 lldp_config_params); 752 data.lldp_local = p_hwfn->p_dcbx_info->lldp_local; 753 data.size = sizeof(struct lldp_config_params_s); 754 ecore_memcpy_from(p_hwfn, p_ptt, data.lldp_local, data.addr, data.size); 755 756 return rc; 757 } 758 759 static enum _ecore_status_t 760 ecore_dcbx_read_remote_lldp_mib(struct ecore_hwfn *p_hwfn, 761 struct ecore_ptt *p_ptt, 762 enum ecore_mib_read_type type) 763 { 764 struct ecore_dcbx_mib_meta_data data; 765 enum _ecore_status_t rc = ECORE_SUCCESS; 766 767 OSAL_MEM_ZERO(&data, sizeof(data)); 768 data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port, 769 lldp_status_params); 770 data.lldp_remote = p_hwfn->p_dcbx_info->lldp_remote; 771 data.size = sizeof(struct lldp_status_params_s); 772 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type); 773 774 return rc; 775 } 776 777 static enum _ecore_status_t 778 ecore_dcbx_read_operational_mib(struct ecore_hwfn *p_hwfn, 779 struct ecore_ptt *p_ptt, 780 enum ecore_mib_read_type type) 781 { 782 struct ecore_dcbx_mib_meta_data data; 783 enum _ecore_status_t rc = ECORE_SUCCESS; 784 785 OSAL_MEM_ZERO(&data, sizeof(data)); 786 data.addr = p_hwfn->mcp_info->port_addr + 787 offsetof(struct public_port, operational_dcbx_mib); 788 data.mib = &p_hwfn->p_dcbx_info->operational; 789 data.size = sizeof(struct dcbx_mib); 790 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type); 791 792 return rc; 793 } 794 795 static enum _ecore_status_t 796 ecore_dcbx_read_remote_mib(struct ecore_hwfn *p_hwfn, 797 struct ecore_ptt *p_ptt, 798 enum ecore_mib_read_type type) 799 { 800 struct ecore_dcbx_mib_meta_data data; 801 enum _ecore_status_t rc = ECORE_SUCCESS; 802 803 OSAL_MEM_ZERO(&data, sizeof(data)); 804 data.addr = p_hwfn->mcp_info->port_addr + 805 offsetof(struct public_port, remote_dcbx_mib); 806 data.mib = &p_hwfn->p_dcbx_info->remote; 807 data.size = sizeof(struct dcbx_mib); 808 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type); 809 810 return rc; 811 } 812 813 static enum _ecore_status_t 814 ecore_dcbx_read_local_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 815 { 816 struct ecore_dcbx_mib_meta_data data; 817 enum _ecore_status_t rc = ECORE_SUCCESS; 818 819 OSAL_MEM_ZERO(&data, sizeof(data)); 820 data.addr = p_hwfn->mcp_info->port_addr + 821 offsetof(struct public_port, local_admin_dcbx_mib); 822 data.local_admin = &p_hwfn->p_dcbx_info->local_admin; 823 data.size = sizeof(struct dcbx_local_params); 824 ecore_memcpy_from(p_hwfn, p_ptt, data.local_admin, 825 data.addr, data.size); 826 827 return rc; 828 } 829 830 static void 831 ecore_dcbx_read_dscp_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 832 { 833 struct ecore_dcbx_mib_meta_data data; 834 835 data.addr = p_hwfn->mcp_info->port_addr + 836 offsetof(struct public_port, dcb_dscp_map); 837 data.dscp_map = &p_hwfn->p_dcbx_info->dscp_map; 838 data.size = sizeof(struct dcb_dscp_map); 839 ecore_memcpy_from(p_hwfn, p_ptt, data.dscp_map, data.addr, data.size); 840 } 841 842 static enum _ecore_status_t ecore_dcbx_read_mib(struct ecore_hwfn *p_hwfn, 843 struct ecore_ptt *p_ptt, 844 enum ecore_mib_read_type type) 845 { 846 enum _ecore_status_t rc = ECORE_INVAL; 847 848 switch (type) { 849 case ECORE_DCBX_OPERATIONAL_MIB: 850 ecore_dcbx_read_dscp_mib(p_hwfn, p_ptt); 851 rc = ecore_dcbx_read_operational_mib(p_hwfn, p_ptt, type); 852 break; 853 case ECORE_DCBX_REMOTE_MIB: 854 rc = ecore_dcbx_read_remote_mib(p_hwfn, p_ptt, type); 855 break; 856 case ECORE_DCBX_LOCAL_MIB: 857 rc = ecore_dcbx_read_local_mib(p_hwfn, p_ptt); 858 break; 859 case ECORE_DCBX_REMOTE_LLDP_MIB: 860 rc = ecore_dcbx_read_remote_lldp_mib(p_hwfn, p_ptt, type); 861 break; 862 case ECORE_DCBX_LOCAL_LLDP_MIB: 863 rc = ecore_dcbx_read_local_lldp_mib(p_hwfn, p_ptt); 864 break; 865 default: 866 DP_ERR(p_hwfn, "MIB read err, unknown mib type %d\n", type); 867 } 868 869 return ECORE_SUCCESS; 870 } 871 872 /* 873 * Read updated MIB. 874 * Reconfigure QM and invoke PF update ramrod command if operational MIB 875 * change is detected. 876 */ 877 enum _ecore_status_t 878 ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 879 enum ecore_mib_read_type type) 880 { 881 enum _ecore_status_t rc = ECORE_SUCCESS; 882 883 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type); 884 if (rc) 885 return rc; 886 887 if (type == ECORE_DCBX_OPERATIONAL_MIB) { 888 ecore_dcbx_get_dscp_params(p_hwfn, &p_hwfn->p_dcbx_info->get); 889 890 rc = ecore_dcbx_process_mib_info(p_hwfn, p_ptt); 891 if (!rc) { 892 /* reconfigure tcs of QM queues according 893 * to negotiation results 894 */ 895 ecore_qm_reconf(p_hwfn, p_ptt); 896 897 /* update storm FW with negotiation results */ 898 ecore_sp_pf_update_dcbx(p_hwfn); 899 } 900 } 901 902 ecore_dcbx_get_params(p_hwfn, &p_hwfn->p_dcbx_info->get, type); 903 904 /* Update the DSCP to TC mapping enable bit if required */ 905 if ((type == ECORE_DCBX_OPERATIONAL_MIB) && 906 p_hwfn->p_dcbx_info->dscp_nig_update) { 907 u8 val = !!p_hwfn->p_dcbx_info->get.dscp.enabled; 908 u32 addr = NIG_REG_DSCP_TO_TC_MAP_ENABLE; 909 910 rc = ecore_all_ppfids_wr(p_hwfn, p_ptt, addr, val); 911 if (rc != ECORE_SUCCESS) { 912 DP_NOTICE(p_hwfn, false, 913 "Failed to update the DSCP to TC mapping enable bit\n"); 914 return rc; 915 } 916 917 p_hwfn->p_dcbx_info->dscp_nig_update = false; 918 } 919 920 OSAL_DCBX_AEN(p_hwfn, type); 921 922 return rc; 923 } 924 925 enum _ecore_status_t ecore_dcbx_info_alloc(struct ecore_hwfn *p_hwfn) 926 { 927 p_hwfn->p_dcbx_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 928 sizeof(*p_hwfn->p_dcbx_info)); 929 if (!p_hwfn->p_dcbx_info) { 930 DP_NOTICE(p_hwfn, false, 931 "Failed to allocate `struct ecore_dcbx_info'"); 932 return ECORE_NOMEM; 933 } 934 935 p_hwfn->p_dcbx_info->iwarp_port = 936 p_hwfn->pf_params.rdma_pf_params.iwarp_port; 937 938 return ECORE_SUCCESS; 939 } 940 941 void ecore_dcbx_info_free(struct ecore_hwfn *p_hwfn) 942 { 943 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_dcbx_info); 944 } 945 946 static void ecore_dcbx_update_protocol_data(struct protocol_dcb_data *p_data, 947 struct ecore_dcbx_results *p_src, 948 enum dcbx_protocol_type type) 949 { 950 p_data->dcb_enable_flag = p_src->arr[type].enable; 951 p_data->dcb_priority = p_src->arr[type].priority; 952 p_data->dcb_tc = p_src->arr[type].tc; 953 p_data->dscp_enable_flag = p_src->arr[type].dscp_enable; 954 p_data->dscp_val = p_src->arr[type].dscp_val; 955 p_data->dcb_dont_add_vlan0 = p_src->arr[type].dont_add_vlan0; 956 } 957 958 /* Set pf update ramrod command params */ 959 void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src, 960 struct pf_update_ramrod_data *p_dest) 961 { 962 struct protocol_dcb_data *p_dcb_data; 963 u8 update_flag; 964 965 update_flag = p_src->arr[DCBX_PROTOCOL_ETH].update; 966 p_dest->update_eth_dcb_data_mode = update_flag; 967 update_flag = p_src->arr[DCBX_PROTOCOL_IWARP].update; 968 p_dest->update_iwarp_dcb_data_mode = update_flag; 969 970 p_dcb_data = &p_dest->eth_dcb_data; 971 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_ETH); 972 p_dcb_data = &p_dest->iwarp_dcb_data; 973 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_IWARP); 974 } 975 976 enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn, 977 struct ecore_dcbx_get *p_get, 978 enum ecore_mib_read_type type) 979 { 980 struct ecore_ptt *p_ptt; 981 enum _ecore_status_t rc; 982 983 if (IS_VF(p_hwfn->p_dev)) 984 return ECORE_INVAL; 985 986 p_ptt = ecore_ptt_acquire(p_hwfn); 987 if (!p_ptt) 988 return ECORE_TIMEOUT; 989 990 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type); 991 if (rc != ECORE_SUCCESS) 992 goto out; 993 994 ecore_dcbx_get_dscp_params(p_hwfn, p_get); 995 996 rc = ecore_dcbx_get_params(p_hwfn, p_get, type); 997 998 out: 999 ecore_ptt_release(p_hwfn, p_ptt); 1000 return rc; 1001 } 1002 1003 static void 1004 ecore_dcbx_set_pfc_data(struct ecore_hwfn *p_hwfn, 1005 u32 *pfc, struct ecore_dcbx_params *p_params) 1006 { 1007 u8 pfc_map = 0; 1008 int i; 1009 1010 if (p_params->pfc.willing) 1011 *pfc |= DCBX_PFC_WILLING_MASK; 1012 else 1013 *pfc &= ~DCBX_PFC_WILLING_MASK; 1014 1015 if (p_params->pfc.enabled) 1016 *pfc |= DCBX_PFC_ENABLED_MASK; 1017 else 1018 *pfc &= ~DCBX_PFC_ENABLED_MASK; 1019 1020 *pfc &= ~DCBX_PFC_CAPS_MASK; 1021 *pfc |= (u32)p_params->pfc.max_tc << DCBX_PFC_CAPS_OFFSET; 1022 1023 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) 1024 if (p_params->pfc.prio[i]) 1025 pfc_map |= (1 << i); 1026 *pfc &= ~DCBX_PFC_PRI_EN_BITMAP_MASK; 1027 *pfc |= (pfc_map << DCBX_PFC_PRI_EN_BITMAP_OFFSET); 1028 1029 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "pfc = 0x%x\n", *pfc); 1030 } 1031 1032 static void 1033 ecore_dcbx_set_ets_data(struct ecore_hwfn *p_hwfn, 1034 struct dcbx_ets_feature *p_ets, 1035 struct ecore_dcbx_params *p_params) 1036 { 1037 u8 *bw_map, *tsa_map; 1038 u32 val; 1039 int i; 1040 1041 if (p_params->ets_willing) 1042 p_ets->flags |= DCBX_ETS_WILLING_MASK; 1043 else 1044 p_ets->flags &= ~DCBX_ETS_WILLING_MASK; 1045 1046 if (p_params->ets_cbs) 1047 p_ets->flags |= DCBX_ETS_CBS_MASK; 1048 else 1049 p_ets->flags &= ~DCBX_ETS_CBS_MASK; 1050 1051 if (p_params->ets_enabled) 1052 p_ets->flags |= DCBX_ETS_ENABLED_MASK; 1053 else 1054 p_ets->flags &= ~DCBX_ETS_ENABLED_MASK; 1055 1056 p_ets->flags &= ~DCBX_ETS_MAX_TCS_MASK; 1057 p_ets->flags |= (u32)p_params->max_ets_tc << DCBX_ETS_MAX_TCS_OFFSET; 1058 1059 bw_map = (u8 *)&p_ets->tc_bw_tbl[0]; 1060 tsa_map = (u8 *)&p_ets->tc_tsa_tbl[0]; 1061 p_ets->pri_tc_tbl[0] = 0; 1062 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) { 1063 bw_map[i] = p_params->ets_tc_bw_tbl[i]; 1064 tsa_map[i] = p_params->ets_tc_tsa_tbl[i]; 1065 /* Copy the priority value to the corresponding 4 bits in the 1066 * traffic class table. 1067 */ 1068 val = (((u32)p_params->ets_pri_tc_tbl[i]) << ((7 - i) * 4)); 1069 p_ets->pri_tc_tbl[0] |= val; 1070 } 1071 for (i = 0; i < 2; i++) { 1072 p_ets->tc_bw_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_bw_tbl[i]); 1073 p_ets->tc_tsa_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_tsa_tbl[i]); 1074 } 1075 1076 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 1077 "flags = 0x%x pri_tc = 0x%x tc_bwl[] = {0x%x, 0x%x} tc_tsa = {0x%x, 0x%x}\n", 1078 p_ets->flags, p_ets->pri_tc_tbl[0], p_ets->tc_bw_tbl[0], 1079 p_ets->tc_bw_tbl[1], p_ets->tc_tsa_tbl[0], 1080 p_ets->tc_tsa_tbl[1]); 1081 } 1082 1083 static void 1084 ecore_dcbx_set_app_data(struct ecore_hwfn *p_hwfn, 1085 struct dcbx_app_priority_feature *p_app, 1086 struct ecore_dcbx_params *p_params, bool ieee) 1087 { 1088 u32 *entry; 1089 int i; 1090 1091 if (p_params->app_willing) 1092 p_app->flags |= DCBX_APP_WILLING_MASK; 1093 else 1094 p_app->flags &= ~DCBX_APP_WILLING_MASK; 1095 1096 if (p_params->app_valid) 1097 p_app->flags |= DCBX_APP_ENABLED_MASK; 1098 else 1099 p_app->flags &= ~DCBX_APP_ENABLED_MASK; 1100 1101 p_app->flags &= ~DCBX_APP_NUM_ENTRIES_MASK; 1102 p_app->flags |= (u32)p_params->num_app_entries << 1103 DCBX_APP_NUM_ENTRIES_OFFSET; 1104 1105 for (i = 0; i < p_params->num_app_entries; i++) { 1106 entry = &p_app->app_pri_tbl[i].entry; 1107 *entry = 0; 1108 if (ieee) { 1109 *entry &= ~(DCBX_APP_SF_IEEE_MASK | DCBX_APP_SF_MASK); 1110 switch (p_params->app_entry[i].sf_ieee) { 1111 case ECORE_DCBX_SF_IEEE_ETHTYPE: 1112 *entry |= ((u32)DCBX_APP_SF_IEEE_ETHTYPE << 1113 DCBX_APP_SF_IEEE_OFFSET); 1114 *entry |= ((u32)DCBX_APP_SF_ETHTYPE << 1115 DCBX_APP_SF_OFFSET); 1116 break; 1117 case ECORE_DCBX_SF_IEEE_TCP_PORT: 1118 *entry |= ((u32)DCBX_APP_SF_IEEE_TCP_PORT << 1119 DCBX_APP_SF_IEEE_OFFSET); 1120 *entry |= ((u32)DCBX_APP_SF_PORT << 1121 DCBX_APP_SF_OFFSET); 1122 break; 1123 case ECORE_DCBX_SF_IEEE_UDP_PORT: 1124 *entry |= ((u32)DCBX_APP_SF_IEEE_UDP_PORT << 1125 DCBX_APP_SF_IEEE_OFFSET); 1126 *entry |= ((u32)DCBX_APP_SF_PORT << 1127 DCBX_APP_SF_OFFSET); 1128 break; 1129 case ECORE_DCBX_SF_IEEE_TCP_UDP_PORT: 1130 *entry |= (u32)DCBX_APP_SF_IEEE_TCP_UDP_PORT << 1131 DCBX_APP_SF_IEEE_OFFSET; 1132 *entry |= ((u32)DCBX_APP_SF_PORT << 1133 DCBX_APP_SF_OFFSET); 1134 break; 1135 } 1136 } else { 1137 *entry &= ~DCBX_APP_SF_MASK; 1138 if (p_params->app_entry[i].ethtype) 1139 *entry |= ((u32)DCBX_APP_SF_ETHTYPE << 1140 DCBX_APP_SF_OFFSET); 1141 else 1142 *entry |= ((u32)DCBX_APP_SF_PORT << 1143 DCBX_APP_SF_OFFSET); 1144 } 1145 *entry &= ~DCBX_APP_PROTOCOL_ID_MASK; 1146 *entry |= ((u32)p_params->app_entry[i].proto_id << 1147 DCBX_APP_PROTOCOL_ID_OFFSET); 1148 *entry &= ~DCBX_APP_PRI_MAP_MASK; 1149 *entry |= ((u32)(p_params->app_entry[i].prio) << 1150 DCBX_APP_PRI_MAP_OFFSET); 1151 } 1152 1153 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_app->flags); 1154 } 1155 1156 static void 1157 ecore_dcbx_set_local_params(struct ecore_hwfn *p_hwfn, 1158 struct dcbx_local_params *local_admin, 1159 struct ecore_dcbx_set *params) 1160 { 1161 bool ieee = false; 1162 1163 local_admin->flags = 0; 1164 OSAL_MEMCPY(&local_admin->features, 1165 &p_hwfn->p_dcbx_info->operational.features, 1166 sizeof(local_admin->features)); 1167 1168 if (params->enabled) { 1169 local_admin->config = params->ver_num; 1170 ieee = !!(params->ver_num & DCBX_CONFIG_VERSION_IEEE); 1171 } else { 1172 local_admin->config = DCBX_CONFIG_VERSION_DISABLED; 1173 } 1174 1175 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Dcbx version = %d\n", 1176 local_admin->config); 1177 1178 if (params->override_flags & ECORE_DCBX_OVERRIDE_PFC_CFG) 1179 ecore_dcbx_set_pfc_data(p_hwfn, &local_admin->features.pfc, 1180 ¶ms->config.params); 1181 1182 if (params->override_flags & ECORE_DCBX_OVERRIDE_ETS_CFG) 1183 ecore_dcbx_set_ets_data(p_hwfn, &local_admin->features.ets, 1184 ¶ms->config.params); 1185 1186 if (params->override_flags & ECORE_DCBX_OVERRIDE_APP_CFG) 1187 ecore_dcbx_set_app_data(p_hwfn, &local_admin->features.app, 1188 ¶ms->config.params, ieee); 1189 } 1190 1191 static enum _ecore_status_t 1192 ecore_dcbx_set_dscp_params(struct ecore_hwfn *p_hwfn, 1193 struct dcb_dscp_map *p_dscp_map, 1194 struct ecore_dcbx_set *p_params) 1195 { 1196 int entry, i, j; 1197 u32 val; 1198 1199 OSAL_MEMCPY(p_dscp_map, &p_hwfn->p_dcbx_info->dscp_map, 1200 sizeof(*p_dscp_map)); 1201 1202 p_dscp_map->flags &= ~DCB_DSCP_ENABLE_MASK; 1203 if (p_params->dscp.enabled) 1204 p_dscp_map->flags |= DCB_DSCP_ENABLE_MASK; 1205 1206 for (i = 0, entry = 0; i < 8; i++) { 1207 val = 0; 1208 for (j = 0; j < 8; j++, entry++) 1209 val |= (((u32)p_params->dscp.dscp_pri_map[entry]) << 1210 (j * 4)); 1211 1212 p_dscp_map->dscp_pri_map[i] = OSAL_CPU_TO_BE32(val); 1213 } 1214 1215 p_hwfn->p_dcbx_info->dscp_nig_update = true; 1216 1217 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_dscp_map->flags); 1218 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 1219 "pri_map[] = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 1220 p_dscp_map->dscp_pri_map[0], p_dscp_map->dscp_pri_map[1], 1221 p_dscp_map->dscp_pri_map[2], p_dscp_map->dscp_pri_map[3], 1222 p_dscp_map->dscp_pri_map[4], p_dscp_map->dscp_pri_map[5], 1223 p_dscp_map->dscp_pri_map[6], p_dscp_map->dscp_pri_map[7]); 1224 1225 return ECORE_SUCCESS; 1226 } 1227 1228 enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *p_hwfn, 1229 struct ecore_ptt *p_ptt, 1230 struct ecore_dcbx_set *params, 1231 bool hw_commit) 1232 { 1233 struct dcbx_local_params local_admin; 1234 struct ecore_dcbx_mib_meta_data data; 1235 struct dcb_dscp_map dscp_map; 1236 u32 resp = 0, param = 0; 1237 enum _ecore_status_t rc = ECORE_SUCCESS; 1238 1239 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set, params, 1240 sizeof(p_hwfn->p_dcbx_info->set)); 1241 if (!hw_commit) 1242 return ECORE_SUCCESS; 1243 1244 OSAL_MEMSET(&local_admin, 0, sizeof(local_admin)); 1245 ecore_dcbx_set_local_params(p_hwfn, &local_admin, params); 1246 1247 data.addr = p_hwfn->mcp_info->port_addr + 1248 offsetof(struct public_port, local_admin_dcbx_mib); 1249 data.local_admin = &local_admin; 1250 data.size = sizeof(struct dcbx_local_params); 1251 ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.local_admin, data.size); 1252 1253 if (params->override_flags & ECORE_DCBX_OVERRIDE_DSCP_CFG) { 1254 OSAL_MEMSET(&dscp_map, 0, sizeof(dscp_map)); 1255 ecore_dcbx_set_dscp_params(p_hwfn, &dscp_map, params); 1256 1257 data.addr = p_hwfn->mcp_info->port_addr + 1258 offsetof(struct public_port, dcb_dscp_map); 1259 data.dscp_map = &dscp_map; 1260 data.size = sizeof(struct dcb_dscp_map); 1261 ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.dscp_map, 1262 data.size); 1263 } 1264 1265 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_DCBX, 1266 1 << DRV_MB_PARAM_LLDP_SEND_OFFSET, &resp, ¶m); 1267 if (rc != ECORE_SUCCESS) 1268 DP_NOTICE(p_hwfn, false, 1269 "Failed to send DCBX update request\n"); 1270 1271 return rc; 1272 } 1273 1274 enum _ecore_status_t ecore_dcbx_get_config_params(struct ecore_hwfn *p_hwfn, 1275 struct ecore_dcbx_set *params) 1276 { 1277 struct ecore_dcbx_get *dcbx_info; 1278 int rc; 1279 1280 if (p_hwfn->p_dcbx_info->set.config.valid) { 1281 OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set, 1282 sizeof(struct ecore_dcbx_set)); 1283 return ECORE_SUCCESS; 1284 } 1285 1286 dcbx_info = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL, 1287 sizeof(*dcbx_info)); 1288 if (!dcbx_info) 1289 return ECORE_NOMEM; 1290 1291 OSAL_MEMSET(dcbx_info, 0, sizeof(*dcbx_info)); 1292 rc = ecore_dcbx_query_params(p_hwfn, dcbx_info, 1293 ECORE_DCBX_OPERATIONAL_MIB); 1294 if (rc) { 1295 OSAL_FREE(p_hwfn->p_dev, dcbx_info); 1296 return rc; 1297 } 1298 p_hwfn->p_dcbx_info->set.override_flags = 0; 1299 1300 p_hwfn->p_dcbx_info->set.ver_num = DCBX_CONFIG_VERSION_DISABLED; 1301 if (dcbx_info->operational.cee) 1302 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_CEE; 1303 if (dcbx_info->operational.ieee) 1304 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_IEEE; 1305 if (dcbx_info->operational.local) 1306 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_STATIC; 1307 1308 p_hwfn->p_dcbx_info->set.enabled = dcbx_info->operational.enabled; 1309 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.dscp, 1310 &p_hwfn->p_dcbx_info->get.dscp, 1311 sizeof(struct ecore_dcbx_dscp_params)); 1312 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.config.params, 1313 &dcbx_info->operational.params, 1314 sizeof(p_hwfn->p_dcbx_info->set.config.params)); 1315 p_hwfn->p_dcbx_info->set.config.valid = true; 1316 1317 OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set, 1318 sizeof(struct ecore_dcbx_set)); 1319 1320 OSAL_FREE(p_hwfn->p_dev, dcbx_info); 1321 1322 return ECORE_SUCCESS; 1323 } 1324 1325 enum _ecore_status_t ecore_lldp_register_tlv(struct ecore_hwfn *p_hwfn, 1326 struct ecore_ptt *p_ptt, 1327 enum ecore_lldp_agent agent, 1328 u8 tlv_type) 1329 { 1330 u32 mb_param = 0, mcp_resp = 0, mcp_param = 0, val = 0; 1331 enum _ecore_status_t rc = ECORE_SUCCESS; 1332 1333 switch (agent) { 1334 case ECORE_LLDP_NEAREST_BRIDGE: 1335 val = LLDP_NEAREST_BRIDGE; 1336 break; 1337 case ECORE_LLDP_NEAREST_NON_TPMR_BRIDGE: 1338 val = LLDP_NEAREST_NON_TPMR_BRIDGE; 1339 break; 1340 case ECORE_LLDP_NEAREST_CUSTOMER_BRIDGE: 1341 val = LLDP_NEAREST_CUSTOMER_BRIDGE; 1342 break; 1343 default: 1344 DP_ERR(p_hwfn, "Invalid agent type %d\n", agent); 1345 return ECORE_INVAL; 1346 } 1347 1348 SET_MFW_FIELD(mb_param, DRV_MB_PARAM_LLDP_AGENT, val); 1349 SET_MFW_FIELD(mb_param, DRV_MB_PARAM_LLDP_TLV_RX_TYPE, tlv_type); 1350 1351 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX, 1352 mb_param, &mcp_resp, &mcp_param); 1353 if (rc != ECORE_SUCCESS) 1354 DP_NOTICE(p_hwfn, false, "Failed to register TLV\n"); 1355 1356 return rc; 1357 } 1358 1359 enum _ecore_status_t 1360 ecore_lldp_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 1361 { 1362 struct ecore_dcbx_mib_meta_data data; 1363 enum _ecore_status_t rc = ECORE_SUCCESS; 1364 struct lldp_received_tlvs_s tlvs; 1365 int i; 1366 1367 for (i = 0; i < LLDP_MAX_LLDP_AGENTS; i++) { 1368 OSAL_MEM_ZERO(&data, sizeof(data)); 1369 data.addr = p_hwfn->mcp_info->port_addr + 1370 offsetof(struct public_port, lldp_received_tlvs[i]); 1371 data.lldp_tlvs = &tlvs; 1372 data.size = sizeof(tlvs); 1373 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, 1374 ECORE_DCBX_LLDP_TLVS); 1375 if (rc != ECORE_SUCCESS) { 1376 DP_NOTICE(p_hwfn, false, "Failed to read lldp TLVs\n"); 1377 return rc; 1378 } 1379 1380 if (!tlvs.length) 1381 continue; 1382 1383 for (i = 0; i < MAX_TLV_BUFFER; i++) 1384 tlvs.tlvs_buffer[i] = 1385 OSAL_CPU_TO_BE32(tlvs.tlvs_buffer[i]); 1386 1387 OSAL_LLDP_RX_TLVS(p_hwfn, tlvs.tlvs_buffer, tlvs.length); 1388 } 1389 1390 return rc; 1391 } 1392 1393 enum _ecore_status_t 1394 ecore_lldp_get_params(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1395 struct ecore_lldp_config_params *p_params) 1396 { 1397 struct lldp_config_params_s lldp_params; 1398 u32 addr, val; 1399 int i; 1400 1401 switch (p_params->agent) { 1402 case ECORE_LLDP_NEAREST_BRIDGE: 1403 val = LLDP_NEAREST_BRIDGE; 1404 break; 1405 case ECORE_LLDP_NEAREST_NON_TPMR_BRIDGE: 1406 val = LLDP_NEAREST_NON_TPMR_BRIDGE; 1407 break; 1408 case ECORE_LLDP_NEAREST_CUSTOMER_BRIDGE: 1409 val = LLDP_NEAREST_CUSTOMER_BRIDGE; 1410 break; 1411 default: 1412 DP_ERR(p_hwfn, "Invalid agent type %d\n", p_params->agent); 1413 return ECORE_INVAL; 1414 } 1415 1416 addr = p_hwfn->mcp_info->port_addr + 1417 offsetof(struct public_port, lldp_config_params[val]); 1418 1419 ecore_memcpy_from(p_hwfn, p_ptt, &lldp_params, addr, 1420 sizeof(lldp_params)); 1421 1422 p_params->tx_interval = GET_MFW_FIELD(lldp_params.config, 1423 LLDP_CONFIG_TX_INTERVAL); 1424 p_params->tx_hold = GET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_HOLD); 1425 p_params->tx_credit = GET_MFW_FIELD(lldp_params.config, 1426 LLDP_CONFIG_MAX_CREDIT); 1427 p_params->rx_enable = GET_MFW_FIELD(lldp_params.config, 1428 LLDP_CONFIG_ENABLE_RX); 1429 p_params->tx_enable = GET_MFW_FIELD(lldp_params.config, 1430 LLDP_CONFIG_ENABLE_TX); 1431 1432 OSAL_MEMCPY(p_params->chassis_id_tlv, lldp_params.local_chassis_id, 1433 sizeof(p_params->chassis_id_tlv)); 1434 for (i = 0; i < ECORE_LLDP_CHASSIS_ID_STAT_LEN; i++) 1435 p_params->chassis_id_tlv[i] = 1436 OSAL_BE32_TO_CPU(p_params->chassis_id_tlv[i]); 1437 1438 OSAL_MEMCPY(p_params->port_id_tlv, lldp_params.local_port_id, 1439 sizeof(p_params->port_id_tlv)); 1440 for (i = 0; i < ECORE_LLDP_PORT_ID_STAT_LEN; i++) 1441 p_params->port_id_tlv[i] = 1442 OSAL_BE32_TO_CPU(p_params->port_id_tlv[i]); 1443 1444 return ECORE_SUCCESS; 1445 } 1446 1447 enum _ecore_status_t 1448 ecore_lldp_set_params(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1449 struct ecore_lldp_config_params *p_params) 1450 { 1451 u32 mb_param = 0, mcp_resp = 0, mcp_param = 0; 1452 struct lldp_config_params_s lldp_params; 1453 enum _ecore_status_t rc = ECORE_SUCCESS; 1454 u32 addr, val; 1455 int i; 1456 1457 switch (p_params->agent) { 1458 case ECORE_LLDP_NEAREST_BRIDGE: 1459 val = LLDP_NEAREST_BRIDGE; 1460 break; 1461 case ECORE_LLDP_NEAREST_NON_TPMR_BRIDGE: 1462 val = LLDP_NEAREST_NON_TPMR_BRIDGE; 1463 break; 1464 case ECORE_LLDP_NEAREST_CUSTOMER_BRIDGE: 1465 val = LLDP_NEAREST_CUSTOMER_BRIDGE; 1466 break; 1467 default: 1468 DP_ERR(p_hwfn, "Invalid agent type %d\n", p_params->agent); 1469 return ECORE_INVAL; 1470 } 1471 1472 SET_MFW_FIELD(mb_param, DRV_MB_PARAM_LLDP_AGENT, val); 1473 addr = p_hwfn->mcp_info->port_addr + 1474 offsetof(struct public_port, lldp_config_params[val]); 1475 1476 OSAL_MEMSET(&lldp_params, 0, sizeof(lldp_params)); 1477 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_TX_INTERVAL, 1478 p_params->tx_interval); 1479 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_HOLD, p_params->tx_hold); 1480 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_MAX_CREDIT, 1481 p_params->tx_credit); 1482 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_ENABLE_RX, 1483 !!p_params->rx_enable); 1484 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_ENABLE_TX, 1485 !!p_params->tx_enable); 1486 1487 for (i = 0; i < ECORE_LLDP_CHASSIS_ID_STAT_LEN; i++) 1488 p_params->chassis_id_tlv[i] = 1489 OSAL_CPU_TO_BE32(p_params->chassis_id_tlv[i]); 1490 OSAL_MEMCPY(lldp_params.local_chassis_id, p_params->chassis_id_tlv, 1491 sizeof(lldp_params.local_chassis_id)); 1492 1493 for (i = 0; i < ECORE_LLDP_PORT_ID_STAT_LEN; i++) 1494 p_params->port_id_tlv[i] = 1495 OSAL_CPU_TO_BE32(p_params->port_id_tlv[i]); 1496 OSAL_MEMCPY(lldp_params.local_port_id, p_params->port_id_tlv, 1497 sizeof(lldp_params.local_port_id)); 1498 1499 ecore_memcpy_to(p_hwfn, p_ptt, addr, &lldp_params, sizeof(lldp_params)); 1500 1501 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LLDP, 1502 mb_param, &mcp_resp, &mcp_param); 1503 if (rc != ECORE_SUCCESS) 1504 DP_NOTICE(p_hwfn, false, "SET_LLDP failed, error = %d\n", rc); 1505 1506 return rc; 1507 } 1508 1509 enum _ecore_status_t 1510 ecore_lldp_set_system_tlvs(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1511 struct ecore_lldp_sys_tlvs *p_params) 1512 { 1513 u32 mb_param = 0, mcp_resp = 0, mcp_param = 0; 1514 enum _ecore_status_t rc = ECORE_SUCCESS; 1515 struct lldp_system_tlvs_buffer_s lld_tlv_buf; 1516 u32 addr, *p_val; 1517 u8 len; 1518 int i; 1519 1520 p_val = (u32 *)p_params->buf; 1521 for (i = 0; i < ECORE_LLDP_SYS_TLV_SIZE / 4; i++) 1522 p_val[i] = OSAL_CPU_TO_BE32(p_val[i]); 1523 1524 OSAL_MEMSET(&lld_tlv_buf, 0, sizeof(lld_tlv_buf)); 1525 SET_MFW_FIELD(lld_tlv_buf.flags, LLDP_SYSTEM_TLV_VALID, 1); 1526 SET_MFW_FIELD(lld_tlv_buf.flags, LLDP_SYSTEM_TLV_MANDATORY, 1527 !!p_params->discard_mandatory_tlv); 1528 SET_MFW_FIELD(lld_tlv_buf.flags, LLDP_SYSTEM_TLV_LENGTH, 1529 p_params->buf_size); 1530 len = ECORE_LLDP_SYS_TLV_SIZE / 2; 1531 OSAL_MEMCPY(lld_tlv_buf.data, p_params->buf, len); 1532 1533 addr = p_hwfn->mcp_info->port_addr + 1534 offsetof(struct public_port, system_lldp_tlvs_buf); 1535 ecore_memcpy_to(p_hwfn, p_ptt, addr, &lld_tlv_buf, sizeof(lld_tlv_buf)); 1536 1537 if (p_params->buf_size > len) { 1538 addr = p_hwfn->mcp_info->port_addr + 1539 offsetof(struct public_port, system_lldp_tlvs_buf2); 1540 ecore_memcpy_to(p_hwfn, p_ptt, addr, &p_params->buf[len], 1541 ECORE_LLDP_SYS_TLV_SIZE / 2); 1542 } 1543 1544 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LLDP, 1545 mb_param, &mcp_resp, &mcp_param); 1546 if (rc != ECORE_SUCCESS) 1547 DP_NOTICE(p_hwfn, false, "SET_LLDP failed, error = %d\n", rc); 1548 1549 return rc; 1550 } 1551 1552 enum _ecore_status_t 1553 ecore_dcbx_get_dscp_priority(struct ecore_hwfn *p_hwfn, 1554 u8 dscp_index, u8 *p_dscp_pri) 1555 { 1556 struct ecore_dcbx_get *p_dcbx_info; 1557 enum _ecore_status_t rc; 1558 1559 if (dscp_index >= ECORE_DCBX_DSCP_SIZE) { 1560 DP_ERR(p_hwfn, "Invalid dscp index %d\n", dscp_index); 1561 return ECORE_INVAL; 1562 } 1563 1564 p_dcbx_info = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL, 1565 sizeof(*p_dcbx_info)); 1566 if (!p_dcbx_info) 1567 return ECORE_NOMEM; 1568 1569 OSAL_MEMSET(p_dcbx_info, 0, sizeof(*p_dcbx_info)); 1570 rc = ecore_dcbx_query_params(p_hwfn, p_dcbx_info, 1571 ECORE_DCBX_OPERATIONAL_MIB); 1572 if (rc) { 1573 OSAL_FREE(p_hwfn->p_dev, p_dcbx_info); 1574 return rc; 1575 } 1576 1577 *p_dscp_pri = p_dcbx_info->dscp.dscp_pri_map[dscp_index]; 1578 OSAL_FREE(p_hwfn->p_dev, p_dcbx_info); 1579 1580 return ECORE_SUCCESS; 1581 } 1582 1583 enum _ecore_status_t 1584 ecore_dcbx_set_dscp_priority(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1585 u8 dscp_index, u8 pri_val) 1586 { 1587 struct ecore_dcbx_set dcbx_set; 1588 enum _ecore_status_t rc; 1589 1590 if (dscp_index >= ECORE_DCBX_DSCP_SIZE || 1591 pri_val >= ECORE_MAX_PFC_PRIORITIES) { 1592 DP_ERR(p_hwfn, "Invalid dscp params: index = %d pri = %d\n", 1593 dscp_index, pri_val); 1594 return ECORE_INVAL; 1595 } 1596 1597 OSAL_MEMSET(&dcbx_set, 0, sizeof(dcbx_set)); 1598 rc = ecore_dcbx_get_config_params(p_hwfn, &dcbx_set); 1599 if (rc) 1600 return rc; 1601 1602 dcbx_set.override_flags = ECORE_DCBX_OVERRIDE_DSCP_CFG; 1603 dcbx_set.dscp.dscp_pri_map[dscp_index] = pri_val; 1604 1605 return ecore_dcbx_config_params(p_hwfn, p_ptt, &dcbx_set, 1); 1606 } 1607