1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #include "bcm_osal.h" 10 #include "ecore.h" 11 #include "ecore_sp_commands.h" 12 #include "ecore_dcbx.h" 13 #include "ecore_cxt.h" 14 #include "ecore_gtt_reg_addr.h" 15 #include "ecore_iro.h" 16 #include "ecore_iov_api.h" 17 18 #define ECORE_DCBX_MAX_MIB_READ_TRY (100) 19 #define ECORE_ETH_TYPE_DEFAULT (0) 20 21 #define ECORE_DCBX_INVALID_PRIORITY 0xFF 22 23 /* Get Traffic Class from priority traffic class table, 4 bits represent 24 * the traffic class corresponding to the priority. 25 */ 26 #define ECORE_DCBX_PRIO2TC(prio_tc_tbl, prio) \ 27 ((u32)(prio_tc_tbl >> ((7 - prio) * 4)) & 0x7) 28 29 static bool ecore_dcbx_app_ethtype(u32 app_info_bitmap) 30 { 31 return !!(GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF) == 32 DCBX_APP_SF_ETHTYPE); 33 } 34 35 static bool ecore_dcbx_ieee_app_ethtype(u32 app_info_bitmap) 36 { 37 u8 mfw_val = GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE); 38 39 /* Old MFW */ 40 if (mfw_val == DCBX_APP_SF_IEEE_RESERVED) 41 return ecore_dcbx_app_ethtype(app_info_bitmap); 42 43 return !!(mfw_val == DCBX_APP_SF_IEEE_ETHTYPE); 44 } 45 46 static bool ecore_dcbx_app_port(u32 app_info_bitmap) 47 { 48 return !!(GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF) == 49 DCBX_APP_SF_PORT); 50 } 51 52 static bool ecore_dcbx_ieee_app_port(u32 app_info_bitmap, u8 type) 53 { 54 u8 mfw_val = GET_MFW_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE); 55 56 /* Old MFW */ 57 if (mfw_val == DCBX_APP_SF_IEEE_RESERVED) 58 return ecore_dcbx_app_port(app_info_bitmap); 59 60 return !!(mfw_val == type || mfw_val == DCBX_APP_SF_IEEE_TCP_UDP_PORT); 61 } 62 63 static bool ecore_dcbx_default_tlv(u32 app_info_bitmap, u16 proto_id, bool ieee) 64 { 65 bool ethtype; 66 67 if (ieee) 68 ethtype = ecore_dcbx_ieee_app_ethtype(app_info_bitmap); 69 else 70 ethtype = ecore_dcbx_app_ethtype(app_info_bitmap); 71 72 return !!(ethtype && (proto_id == ECORE_ETH_TYPE_DEFAULT)); 73 } 74 75 static bool ecore_dcbx_iwarp_tlv(struct ecore_hwfn *p_hwfn, u32 app_info_bitmap, 76 u16 proto_id, bool ieee) 77 { 78 bool port; 79 80 if (!p_hwfn->p_dcbx_info->iwarp_port) 81 return false; 82 83 if (ieee) 84 port = ecore_dcbx_ieee_app_port(app_info_bitmap, 85 DCBX_APP_SF_IEEE_TCP_PORT); 86 else 87 port = ecore_dcbx_app_port(app_info_bitmap); 88 89 return !!(port && (proto_id == p_hwfn->p_dcbx_info->iwarp_port)); 90 } 91 92 static void 93 ecore_dcbx_dp_protocol(struct ecore_hwfn *p_hwfn, 94 struct ecore_dcbx_results *p_data) 95 { 96 enum dcbx_protocol_type id; 97 int i; 98 99 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "DCBX negotiated: %d\n", 100 p_data->dcbx_enabled); 101 102 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) { 103 id = ecore_dcbx_app_update[i].id; 104 105 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 106 "%s info: update %d, enable %d, prio %d, tc %d," 107 " num_active_tc %d dscp_enable = %d dscp_val = %d\n", 108 ecore_dcbx_app_update[i].name, 109 p_data->arr[id].update, 110 p_data->arr[id].enable, p_data->arr[id].priority, 111 p_data->arr[id].tc, p_hwfn->hw_info.num_active_tc, 112 p_data->arr[id].dscp_enable, 113 p_data->arr[id].dscp_val); 114 } 115 } 116 117 u8 ecore_dcbx_get_dscp_value(struct ecore_hwfn *p_hwfn, u8 pri) 118 { 119 struct ecore_dcbx_dscp_params *dscp = &p_hwfn->p_dcbx_info->get.dscp; 120 u8 i; 121 122 if (!dscp->enabled) 123 return ECORE_DCBX_DSCP_DISABLED; 124 125 for (i = 0; i < ECORE_DCBX_DSCP_SIZE; i++) 126 if (pri == dscp->dscp_pri_map[i]) 127 return i; 128 129 return ECORE_DCBX_DSCP_DISABLED; 130 } 131 132 static void 133 ecore_dcbx_set_params(struct ecore_dcbx_results *p_data, 134 struct ecore_hwfn *p_hwfn, 135 bool enable, u8 prio, u8 tc, 136 enum dcbx_protocol_type type, 137 enum ecore_pci_personality personality) 138 { 139 /* PF update ramrod data */ 140 p_data->arr[type].enable = enable; 141 p_data->arr[type].priority = prio; 142 p_data->arr[type].tc = tc; 143 p_data->arr[type].dscp_val = ecore_dcbx_get_dscp_value(p_hwfn, prio); 144 if (p_data->arr[type].dscp_val == ECORE_DCBX_DSCP_DISABLED) { 145 p_data->arr[type].dscp_enable = false; 146 p_data->arr[type].dscp_val = 0; 147 } else { 148 p_data->arr[type].dscp_enable = true; 149 } 150 p_data->arr[type].update = UPDATE_DCB_DSCP; 151 152 /* Do not add valn tag 0 when DCB is enabled and port is in UFP mode */ 153 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) 154 p_data->arr[type].dont_add_vlan0 = true; 155 156 /* QM reconf data */ 157 if (p_hwfn->hw_info.personality == personality) 158 p_hwfn->hw_info.offload_tc = tc; 159 } 160 161 /* Update app protocol data and hw_info fields with the TLV info */ 162 static void 163 ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data, 164 struct ecore_hwfn *p_hwfn, 165 bool enable, u8 prio, u8 tc, 166 enum dcbx_protocol_type type) 167 { 168 enum ecore_pci_personality personality; 169 enum dcbx_protocol_type id; 170 int i; 171 172 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) { 173 id = ecore_dcbx_app_update[i].id; 174 175 if (type != id) 176 continue; 177 178 personality = ecore_dcbx_app_update[i].personality; 179 180 ecore_dcbx_set_params(p_data, p_hwfn, enable, 181 prio, tc, type, personality); 182 } 183 } 184 185 static enum _ecore_status_t 186 ecore_dcbx_get_app_priority(u8 pri_bitmap, u8 *priority) 187 { 188 u32 pri_mask, pri = ECORE_MAX_PFC_PRIORITIES; 189 u32 index = ECORE_MAX_PFC_PRIORITIES - 1; 190 enum _ecore_status_t rc = ECORE_SUCCESS; 191 192 /* Bitmap 1 corresponds to priority 0, return priority 0 */ 193 if (pri_bitmap == 1) { 194 *priority = 0; 195 return rc; 196 } 197 198 /* Choose the highest priority */ 199 while ((pri == ECORE_MAX_PFC_PRIORITIES) && index) { 200 pri_mask = 1 << index; 201 if (pri_bitmap & pri_mask) 202 pri = index; 203 index--; 204 } 205 206 if (pri < ECORE_MAX_PFC_PRIORITIES) 207 *priority = (u8)pri; 208 else 209 rc = ECORE_INVAL; 210 211 return rc; 212 } 213 214 static bool 215 ecore_dcbx_get_app_protocol_type(struct ecore_hwfn *p_hwfn, 216 u32 app_prio_bitmap, u16 id, 217 enum dcbx_protocol_type *type, bool ieee) 218 { 219 if (ecore_dcbx_default_tlv(app_prio_bitmap, id, ieee)) { 220 *type = DCBX_PROTOCOL_ETH; 221 } else { 222 *type = DCBX_MAX_PROTOCOL_TYPE; 223 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 224 "No action required, App TLV entry = 0x%x\n", 225 app_prio_bitmap); 226 return false; 227 } 228 229 return true; 230 } 231 232 /* Parse app TLV's to update TC information in hw_info structure for 233 * reconfiguring QM. Get protocol specific data for PF update ramrod command. 234 */ 235 static enum _ecore_status_t 236 ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn, 237 struct ecore_dcbx_results *p_data, 238 struct dcbx_app_priority_entry *p_tbl, u32 pri_tc_tbl, 239 int count, u8 dcbx_version) 240 { 241 enum dcbx_protocol_type type; 242 bool enable, ieee, eth_tlv; 243 u8 tc, priority_map; 244 u16 protocol_id; 245 u8 priority; 246 enum _ecore_status_t rc = ECORE_SUCCESS; 247 int i; 248 249 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 250 "Num APP entries = %d pri_tc_tbl = 0x%x dcbx_version = %u\n", 251 count, pri_tc_tbl, dcbx_version); 252 253 ieee = (dcbx_version == DCBX_CONFIG_VERSION_IEEE); 254 eth_tlv = false; 255 /* Parse APP TLV */ 256 for (i = 0; i < count; i++) { 257 protocol_id = GET_MFW_FIELD(p_tbl[i].entry, 258 DCBX_APP_PROTOCOL_ID); 259 priority_map = GET_MFW_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP); 260 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Id = 0x%x pri_map = %u\n", 261 protocol_id, priority_map); 262 rc = ecore_dcbx_get_app_priority(priority_map, &priority); 263 if (rc == ECORE_INVAL) { 264 DP_ERR(p_hwfn, "Invalid priority\n"); 265 return ECORE_INVAL; 266 } 267 268 tc = ECORE_DCBX_PRIO2TC(pri_tc_tbl, priority); 269 if (ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry, 270 protocol_id, &type, 271 ieee)) { 272 /* ETH always have the enable bit reset, as it gets 273 * vlan information per packet. For other protocols, 274 * should be set according to the dcbx_enabled 275 * indication, but we only got here if there was an 276 * app tlv for the protocol, so dcbx must be enabled. 277 */ 278 if (type == DCBX_PROTOCOL_ETH) { 279 enable = false; 280 eth_tlv = true; 281 } else { 282 enable = true; 283 } 284 285 ecore_dcbx_update_app_info(p_data, p_hwfn, enable, 286 priority, tc, type); 287 } 288 } 289 290 /* If Eth TLV is not detected, use UFP TC as default TC */ 291 if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, 292 &p_hwfn->p_dev->mf_bits) && !eth_tlv) 293 p_data->arr[DCBX_PROTOCOL_ETH].tc = p_hwfn->ufp_info.tc; 294 295 /* Update ramrod protocol data and hw_info fields 296 * with default info when corresponding APP TLV's are not detected. 297 * The enabled field has a different logic for ethernet as only for 298 * ethernet dcb should disabled by default, as the information arrives 299 * from the OS (unless an explicit app tlv was present). 300 */ 301 tc = p_data->arr[DCBX_PROTOCOL_ETH].tc; 302 priority = p_data->arr[DCBX_PROTOCOL_ETH].priority; 303 for (type = 0; type < DCBX_MAX_PROTOCOL_TYPE; type++) { 304 if (p_data->arr[type].update) 305 continue; 306 307 enable = (type == DCBX_PROTOCOL_ETH) ? false : !!dcbx_version; 308 ecore_dcbx_update_app_info(p_data, p_hwfn, enable, 309 priority, tc, type); 310 } 311 312 return ECORE_SUCCESS; 313 } 314 315 /* Parse app TLV's to update TC information in hw_info structure for 316 * reconfiguring QM. Get protocol specific data for PF update ramrod command. 317 */ 318 static enum _ecore_status_t 319 ecore_dcbx_process_mib_info(struct ecore_hwfn *p_hwfn) 320 { 321 struct dcbx_app_priority_feature *p_app; 322 struct dcbx_app_priority_entry *p_tbl; 323 struct ecore_dcbx_results data = { 0 }; 324 struct dcbx_ets_feature *p_ets; 325 struct ecore_hw_info *p_info; 326 u32 pri_tc_tbl, flags; 327 u8 dcbx_version; 328 int num_entries; 329 enum _ecore_status_t rc = ECORE_SUCCESS; 330 331 flags = p_hwfn->p_dcbx_info->operational.flags; 332 dcbx_version = GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION); 333 334 p_app = &p_hwfn->p_dcbx_info->operational.features.app; 335 p_tbl = p_app->app_pri_tbl; 336 337 p_ets = &p_hwfn->p_dcbx_info->operational.features.ets; 338 pri_tc_tbl = p_ets->pri_tc_tbl[0]; 339 340 p_info = &p_hwfn->hw_info; 341 num_entries = GET_MFW_FIELD(p_app->flags, DCBX_APP_NUM_ENTRIES); 342 343 rc = ecore_dcbx_process_tlv(p_hwfn, &data, p_tbl, pri_tc_tbl, 344 num_entries, dcbx_version); 345 if (rc != ECORE_SUCCESS) 346 return rc; 347 348 p_info->num_active_tc = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS); 349 p_hwfn->qm_info.ooo_tc = GET_MFW_FIELD(p_ets->flags, DCBX_OOO_TC); 350 data.pf_id = p_hwfn->rel_pf_id; 351 data.dcbx_enabled = !!dcbx_version; 352 353 ecore_dcbx_dp_protocol(p_hwfn, &data); 354 355 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->results, &data, 356 sizeof(struct ecore_dcbx_results)); 357 358 return ECORE_SUCCESS; 359 } 360 361 static enum _ecore_status_t 362 ecore_dcbx_copy_mib(struct ecore_hwfn *p_hwfn, 363 struct ecore_ptt *p_ptt, 364 struct ecore_dcbx_mib_meta_data *p_data, 365 enum ecore_mib_read_type type) 366 { 367 u32 prefix_seq_num, suffix_seq_num; 368 int read_count = 0; 369 enum _ecore_status_t rc = ECORE_SUCCESS; 370 371 /* The data is considered to be valid only if both sequence numbers are 372 * the same. 373 */ 374 do { 375 if (type == ECORE_DCBX_REMOTE_LLDP_MIB) { 376 ecore_memcpy_from(p_hwfn, p_ptt, p_data->lldp_remote, 377 p_data->addr, p_data->size); 378 prefix_seq_num = p_data->lldp_remote->prefix_seq_num; 379 suffix_seq_num = p_data->lldp_remote->suffix_seq_num; 380 } else if (type == ECORE_DCBX_LLDP_TLVS) { 381 ecore_memcpy_from(p_hwfn, p_ptt, p_data->lldp_tlvs, 382 p_data->addr, p_data->size); 383 prefix_seq_num = p_data->lldp_tlvs->prefix_seq_num; 384 suffix_seq_num = p_data->lldp_tlvs->suffix_seq_num; 385 386 } else { 387 ecore_memcpy_from(p_hwfn, p_ptt, p_data->mib, 388 p_data->addr, p_data->size); 389 prefix_seq_num = p_data->mib->prefix_seq_num; 390 suffix_seq_num = p_data->mib->suffix_seq_num; 391 } 392 read_count++; 393 394 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 395 "mib type = %d, try count = %d prefix seq num =" 396 " %d suffix seq num = %d\n", 397 type, read_count, prefix_seq_num, suffix_seq_num); 398 } while ((prefix_seq_num != suffix_seq_num) && 399 (read_count < ECORE_DCBX_MAX_MIB_READ_TRY)); 400 401 if (read_count >= ECORE_DCBX_MAX_MIB_READ_TRY) { 402 DP_ERR(p_hwfn, 403 "MIB read err, mib type = %d, try count =" 404 " %d prefix seq num = %d suffix seq num = %d\n", 405 type, read_count, prefix_seq_num, suffix_seq_num); 406 rc = ECORE_IO; 407 } 408 409 return rc; 410 } 411 412 static void 413 ecore_dcbx_get_priority_info(struct ecore_hwfn *p_hwfn, 414 struct ecore_dcbx_app_prio *p_prio, 415 struct ecore_dcbx_results *p_results) 416 { 417 u8 val; 418 419 if (p_results->arr[DCBX_PROTOCOL_ETH].update && 420 p_results->arr[DCBX_PROTOCOL_ETH].enable) 421 p_prio->eth = p_results->arr[DCBX_PROTOCOL_ETH].priority; 422 423 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 424 "Priorities: eth %d\n", 425 p_prio->eth); 426 } 427 428 static void 429 ecore_dcbx_get_app_data(struct ecore_hwfn *p_hwfn, 430 struct dcbx_app_priority_feature *p_app, 431 struct dcbx_app_priority_entry *p_tbl, 432 struct ecore_dcbx_params *p_params, bool ieee) 433 { 434 struct ecore_app_entry *entry; 435 u8 pri_map; 436 int i; 437 438 p_params->app_willing = GET_MFW_FIELD(p_app->flags, DCBX_APP_WILLING); 439 p_params->app_valid = GET_MFW_FIELD(p_app->flags, DCBX_APP_ENABLED); 440 p_params->app_error = GET_MFW_FIELD(p_app->flags, DCBX_APP_ERROR); 441 p_params->num_app_entries = GET_MFW_FIELD(p_app->flags, 442 DCBX_APP_NUM_ENTRIES); 443 for (i = 0; i < p_params->num_app_entries; i++) { 444 entry = &p_params->app_entry[i]; 445 if (ieee) { 446 u8 sf_ieee; 447 u32 val; 448 449 sf_ieee = GET_MFW_FIELD(p_tbl[i].entry, 450 DCBX_APP_SF_IEEE); 451 switch (sf_ieee) { 452 case DCBX_APP_SF_IEEE_RESERVED: 453 /* Old MFW */ 454 val = GET_MFW_FIELD(p_tbl[i].entry, 455 DCBX_APP_SF); 456 entry->sf_ieee = val ? 457 ECORE_DCBX_SF_IEEE_TCP_UDP_PORT : 458 ECORE_DCBX_SF_IEEE_ETHTYPE; 459 break; 460 case DCBX_APP_SF_IEEE_ETHTYPE: 461 entry->sf_ieee = ECORE_DCBX_SF_IEEE_ETHTYPE; 462 break; 463 case DCBX_APP_SF_IEEE_TCP_PORT: 464 entry->sf_ieee = ECORE_DCBX_SF_IEEE_TCP_PORT; 465 break; 466 case DCBX_APP_SF_IEEE_UDP_PORT: 467 entry->sf_ieee = ECORE_DCBX_SF_IEEE_UDP_PORT; 468 break; 469 case DCBX_APP_SF_IEEE_TCP_UDP_PORT: 470 entry->sf_ieee = 471 ECORE_DCBX_SF_IEEE_TCP_UDP_PORT; 472 break; 473 } 474 } else { 475 entry->ethtype = !(GET_MFW_FIELD(p_tbl[i].entry, 476 DCBX_APP_SF)); 477 } 478 479 pri_map = GET_MFW_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP); 480 ecore_dcbx_get_app_priority(pri_map, &entry->prio); 481 entry->proto_id = GET_MFW_FIELD(p_tbl[i].entry, 482 DCBX_APP_PROTOCOL_ID); 483 ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry, 484 entry->proto_id, 485 &entry->proto_type, ieee); 486 } 487 488 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 489 "APP params: willing %d, valid %d error = %d\n", 490 p_params->app_willing, p_params->app_valid, 491 p_params->app_error); 492 } 493 494 static void 495 ecore_dcbx_get_pfc_data(struct ecore_hwfn *p_hwfn, 496 u32 pfc, struct ecore_dcbx_params *p_params) 497 { 498 u8 pfc_map; 499 500 p_params->pfc.willing = GET_MFW_FIELD(pfc, DCBX_PFC_WILLING); 501 p_params->pfc.max_tc = GET_MFW_FIELD(pfc, DCBX_PFC_CAPS); 502 p_params->pfc.enabled = GET_MFW_FIELD(pfc, DCBX_PFC_ENABLED); 503 pfc_map = GET_MFW_FIELD(pfc, DCBX_PFC_PRI_EN_BITMAP); 504 p_params->pfc.prio[0] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_0); 505 p_params->pfc.prio[1] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_1); 506 p_params->pfc.prio[2] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_2); 507 p_params->pfc.prio[3] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_3); 508 p_params->pfc.prio[4] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_4); 509 p_params->pfc.prio[5] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_5); 510 p_params->pfc.prio[6] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_6); 511 p_params->pfc.prio[7] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_7); 512 513 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 514 "PFC params: willing %d, pfc_bitmap %u max_tc = %u enabled = %d\n", 515 p_params->pfc.willing, pfc_map, p_params->pfc.max_tc, 516 p_params->pfc.enabled); 517 } 518 519 static void 520 ecore_dcbx_get_ets_data(struct ecore_hwfn *p_hwfn, 521 struct dcbx_ets_feature *p_ets, 522 struct ecore_dcbx_params *p_params) 523 { 524 u32 bw_map[2], tsa_map[2], pri_map; 525 int i; 526 527 p_params->ets_willing = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_WILLING); 528 p_params->ets_enabled = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_ENABLED); 529 p_params->ets_cbs = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_CBS); 530 p_params->max_ets_tc = GET_MFW_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS); 531 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 532 "ETS params: willing %d, enabled = %d ets_cbs %d pri_tc_tbl_0 %x max_ets_tc %d\n", 533 p_params->ets_willing, p_params->ets_enabled, 534 p_params->ets_cbs, p_ets->pri_tc_tbl[0], 535 p_params->max_ets_tc); 536 537 /* 8 bit tsa and bw data corresponding to each of the 8 TC's are 538 * encoded in a type u32 array of size 2. 539 */ 540 bw_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[0]); 541 bw_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[1]); 542 tsa_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[0]); 543 tsa_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[1]); 544 pri_map = p_ets->pri_tc_tbl[0]; 545 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) { 546 p_params->ets_tc_bw_tbl[i] = ((u8 *)bw_map)[i]; 547 p_params->ets_tc_tsa_tbl[i] = ((u8 *)tsa_map)[i]; 548 p_params->ets_pri_tc_tbl[i] = ECORE_DCBX_PRIO2TC(pri_map, i); 549 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 550 "elem %d bw_tbl %x tsa_tbl %x\n", 551 i, p_params->ets_tc_bw_tbl[i], 552 p_params->ets_tc_tsa_tbl[i]); 553 } 554 } 555 556 static void 557 ecore_dcbx_get_common_params(struct ecore_hwfn *p_hwfn, 558 struct dcbx_app_priority_feature *p_app, 559 struct dcbx_app_priority_entry *p_tbl, 560 struct dcbx_ets_feature *p_ets, 561 u32 pfc, struct ecore_dcbx_params *p_params, 562 bool ieee) 563 { 564 ecore_dcbx_get_app_data(p_hwfn, p_app, p_tbl, p_params, ieee); 565 ecore_dcbx_get_ets_data(p_hwfn, p_ets, p_params); 566 ecore_dcbx_get_pfc_data(p_hwfn, pfc, p_params); 567 } 568 569 static void 570 ecore_dcbx_get_local_params(struct ecore_hwfn *p_hwfn, 571 struct ecore_dcbx_get *params) 572 { 573 struct dcbx_features *p_feat; 574 575 p_feat = &p_hwfn->p_dcbx_info->local_admin.features; 576 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app, 577 p_feat->app.app_pri_tbl, &p_feat->ets, 578 p_feat->pfc, ¶ms->local.params, false); 579 params->local.valid = true; 580 } 581 582 static void 583 ecore_dcbx_get_remote_params(struct ecore_hwfn *p_hwfn, 584 struct ecore_dcbx_get *params) 585 { 586 struct dcbx_features *p_feat; 587 588 p_feat = &p_hwfn->p_dcbx_info->remote.features; 589 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app, 590 p_feat->app.app_pri_tbl, &p_feat->ets, 591 p_feat->pfc, ¶ms->remote.params, 592 false); 593 params->remote.valid = true; 594 } 595 596 static void ecore_dcbx_get_dscp_params(struct ecore_hwfn *p_hwfn, 597 struct ecore_dcbx_get *params) 598 { 599 struct ecore_dcbx_dscp_params *p_dscp; 600 struct dcb_dscp_map *p_dscp_map; 601 int i, j, entry; 602 u32 pri_map; 603 604 p_dscp = ¶ms->dscp; 605 p_dscp_map = &p_hwfn->p_dcbx_info->dscp_map; 606 p_dscp->enabled = GET_MFW_FIELD(p_dscp_map->flags, DCB_DSCP_ENABLE); 607 608 /* MFW encodes 64 dscp entries into 8 element array of u32 entries, 609 * where each entry holds the 4bit priority map for 8 dscp entries. 610 */ 611 for (i = 0, entry = 0; i < ECORE_DCBX_DSCP_SIZE / 8; i++) { 612 pri_map = OSAL_BE32_TO_CPU(p_dscp_map->dscp_pri_map[i]); 613 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "elem %d pri_map 0x%x\n", 614 entry, pri_map); 615 for (j = 0; j < ECORE_DCBX_DSCP_SIZE / 8; j++, entry++) 616 p_dscp->dscp_pri_map[entry] = (u32)(pri_map >> 617 (j * 4)) & 0xf; 618 } 619 } 620 621 static void 622 ecore_dcbx_get_operational_params(struct ecore_hwfn *p_hwfn, 623 struct ecore_dcbx_get *params) 624 { 625 struct ecore_dcbx_operational_params *p_operational; 626 struct ecore_dcbx_results *p_results; 627 struct dcbx_features *p_feat; 628 bool enabled, err; 629 u32 flags; 630 bool val; 631 632 flags = p_hwfn->p_dcbx_info->operational.flags; 633 634 /* If DCBx version is non zero, then negotiation 635 * was successfuly performed 636 */ 637 p_operational = ¶ms->operational; 638 enabled = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) != 639 DCBX_CONFIG_VERSION_DISABLED); 640 if (!enabled) { 641 p_operational->enabled = enabled; 642 p_operational->valid = false; 643 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Dcbx is disabled\n"); 644 return; 645 } 646 647 p_feat = &p_hwfn->p_dcbx_info->operational.features; 648 p_results = &p_hwfn->p_dcbx_info->results; 649 650 val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) == 651 DCBX_CONFIG_VERSION_IEEE); 652 p_operational->ieee = val; 653 654 val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) == 655 DCBX_CONFIG_VERSION_CEE); 656 p_operational->cee = val; 657 658 val = !!(GET_MFW_FIELD(flags, DCBX_CONFIG_VERSION) == 659 DCBX_CONFIG_VERSION_STATIC); 660 p_operational->local = val; 661 662 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 663 "Version support: ieee %d, cee %d, static %d\n", 664 p_operational->ieee, p_operational->cee, 665 p_operational->local); 666 667 ecore_dcbx_get_common_params(p_hwfn, &p_feat->app, 668 p_feat->app.app_pri_tbl, &p_feat->ets, 669 p_feat->pfc, ¶ms->operational.params, 670 p_operational->ieee); 671 ecore_dcbx_get_priority_info(p_hwfn, &p_operational->app_prio, 672 p_results); 673 err = GET_MFW_FIELD(p_feat->app.flags, DCBX_APP_ERROR); 674 p_operational->err = err; 675 p_operational->enabled = enabled; 676 p_operational->valid = true; 677 } 678 679 static void ecore_dcbx_get_local_lldp_params(struct ecore_hwfn *p_hwfn, 680 struct ecore_dcbx_get *params) 681 { 682 struct lldp_config_params_s *p_local; 683 684 p_local = &p_hwfn->p_dcbx_info->lldp_local[LLDP_NEAREST_BRIDGE]; 685 686 OSAL_MEMCPY(params->lldp_local.local_chassis_id, 687 p_local->local_chassis_id, 688 sizeof(params->lldp_local.local_chassis_id)); 689 OSAL_MEMCPY(params->lldp_local.local_port_id, p_local->local_port_id, 690 sizeof(params->lldp_local.local_port_id)); 691 } 692 693 static void ecore_dcbx_get_remote_lldp_params(struct ecore_hwfn *p_hwfn, 694 struct ecore_dcbx_get *params) 695 { 696 struct lldp_status_params_s *p_remote; 697 698 p_remote = &p_hwfn->p_dcbx_info->lldp_remote[LLDP_NEAREST_BRIDGE]; 699 700 OSAL_MEMCPY(params->lldp_remote.peer_chassis_id, 701 p_remote->peer_chassis_id, 702 sizeof(params->lldp_remote.peer_chassis_id)); 703 OSAL_MEMCPY(params->lldp_remote.peer_port_id, p_remote->peer_port_id, 704 sizeof(params->lldp_remote.peer_port_id)); 705 } 706 707 static enum _ecore_status_t 708 ecore_dcbx_get_params(struct ecore_hwfn *p_hwfn, 709 struct ecore_dcbx_get *p_params, 710 enum ecore_mib_read_type type) 711 { 712 switch (type) { 713 case ECORE_DCBX_REMOTE_MIB: 714 ecore_dcbx_get_remote_params(p_hwfn, p_params); 715 break; 716 case ECORE_DCBX_LOCAL_MIB: 717 ecore_dcbx_get_local_params(p_hwfn, p_params); 718 break; 719 case ECORE_DCBX_OPERATIONAL_MIB: 720 ecore_dcbx_get_operational_params(p_hwfn, p_params); 721 break; 722 case ECORE_DCBX_REMOTE_LLDP_MIB: 723 ecore_dcbx_get_remote_lldp_params(p_hwfn, p_params); 724 break; 725 case ECORE_DCBX_LOCAL_LLDP_MIB: 726 ecore_dcbx_get_local_lldp_params(p_hwfn, p_params); 727 break; 728 default: 729 DP_ERR(p_hwfn, "MIB read err, unknown mib type %d\n", type); 730 return ECORE_INVAL; 731 } 732 733 return ECORE_SUCCESS; 734 } 735 736 static enum _ecore_status_t 737 ecore_dcbx_read_local_lldp_mib(struct ecore_hwfn *p_hwfn, 738 struct ecore_ptt *p_ptt) 739 { 740 struct ecore_dcbx_mib_meta_data data; 741 enum _ecore_status_t rc = ECORE_SUCCESS; 742 743 OSAL_MEM_ZERO(&data, sizeof(data)); 744 data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port, 745 lldp_config_params); 746 data.lldp_local = p_hwfn->p_dcbx_info->lldp_local; 747 data.size = sizeof(struct lldp_config_params_s); 748 ecore_memcpy_from(p_hwfn, p_ptt, data.lldp_local, data.addr, data.size); 749 750 return rc; 751 } 752 753 static enum _ecore_status_t 754 ecore_dcbx_read_remote_lldp_mib(struct ecore_hwfn *p_hwfn, 755 struct ecore_ptt *p_ptt, 756 enum ecore_mib_read_type type) 757 { 758 struct ecore_dcbx_mib_meta_data data; 759 enum _ecore_status_t rc = ECORE_SUCCESS; 760 761 OSAL_MEM_ZERO(&data, sizeof(data)); 762 data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port, 763 lldp_status_params); 764 data.lldp_remote = p_hwfn->p_dcbx_info->lldp_remote; 765 data.size = sizeof(struct lldp_status_params_s); 766 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type); 767 768 return rc; 769 } 770 771 static enum _ecore_status_t 772 ecore_dcbx_read_operational_mib(struct ecore_hwfn *p_hwfn, 773 struct ecore_ptt *p_ptt, 774 enum ecore_mib_read_type type) 775 { 776 struct ecore_dcbx_mib_meta_data data; 777 enum _ecore_status_t rc = ECORE_SUCCESS; 778 779 OSAL_MEM_ZERO(&data, sizeof(data)); 780 data.addr = p_hwfn->mcp_info->port_addr + 781 offsetof(struct public_port, operational_dcbx_mib); 782 data.mib = &p_hwfn->p_dcbx_info->operational; 783 data.size = sizeof(struct dcbx_mib); 784 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type); 785 786 return rc; 787 } 788 789 static enum _ecore_status_t 790 ecore_dcbx_read_remote_mib(struct ecore_hwfn *p_hwfn, 791 struct ecore_ptt *p_ptt, 792 enum ecore_mib_read_type type) 793 { 794 struct ecore_dcbx_mib_meta_data data; 795 enum _ecore_status_t rc = ECORE_SUCCESS; 796 797 OSAL_MEM_ZERO(&data, sizeof(data)); 798 data.addr = p_hwfn->mcp_info->port_addr + 799 offsetof(struct public_port, remote_dcbx_mib); 800 data.mib = &p_hwfn->p_dcbx_info->remote; 801 data.size = sizeof(struct dcbx_mib); 802 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, type); 803 804 return rc; 805 } 806 807 static enum _ecore_status_t 808 ecore_dcbx_read_local_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 809 { 810 struct ecore_dcbx_mib_meta_data data; 811 enum _ecore_status_t rc = ECORE_SUCCESS; 812 813 OSAL_MEM_ZERO(&data, sizeof(data)); 814 data.addr = p_hwfn->mcp_info->port_addr + 815 offsetof(struct public_port, local_admin_dcbx_mib); 816 data.local_admin = &p_hwfn->p_dcbx_info->local_admin; 817 data.size = sizeof(struct dcbx_local_params); 818 ecore_memcpy_from(p_hwfn, p_ptt, data.local_admin, 819 data.addr, data.size); 820 821 return rc; 822 } 823 824 static void 825 ecore_dcbx_read_dscp_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 826 { 827 struct ecore_dcbx_mib_meta_data data; 828 829 data.addr = p_hwfn->mcp_info->port_addr + 830 offsetof(struct public_port, dcb_dscp_map); 831 data.dscp_map = &p_hwfn->p_dcbx_info->dscp_map; 832 data.size = sizeof(struct dcb_dscp_map); 833 ecore_memcpy_from(p_hwfn, p_ptt, data.dscp_map, data.addr, data.size); 834 } 835 836 static enum _ecore_status_t ecore_dcbx_read_mib(struct ecore_hwfn *p_hwfn, 837 struct ecore_ptt *p_ptt, 838 enum ecore_mib_read_type type) 839 { 840 enum _ecore_status_t rc = ECORE_INVAL; 841 842 switch (type) { 843 case ECORE_DCBX_OPERATIONAL_MIB: 844 ecore_dcbx_read_dscp_mib(p_hwfn, p_ptt); 845 rc = ecore_dcbx_read_operational_mib(p_hwfn, p_ptt, type); 846 break; 847 case ECORE_DCBX_REMOTE_MIB: 848 rc = ecore_dcbx_read_remote_mib(p_hwfn, p_ptt, type); 849 break; 850 case ECORE_DCBX_LOCAL_MIB: 851 rc = ecore_dcbx_read_local_mib(p_hwfn, p_ptt); 852 break; 853 case ECORE_DCBX_REMOTE_LLDP_MIB: 854 rc = ecore_dcbx_read_remote_lldp_mib(p_hwfn, p_ptt, type); 855 break; 856 case ECORE_DCBX_LOCAL_LLDP_MIB: 857 rc = ecore_dcbx_read_local_lldp_mib(p_hwfn, p_ptt); 858 break; 859 default: 860 DP_ERR(p_hwfn, "MIB read err, unknown mib type %d\n", type); 861 } 862 863 return ECORE_SUCCESS; 864 } 865 866 /* 867 * Read updated MIB. 868 * Reconfigure QM and invoke PF update ramrod command if operational MIB 869 * change is detected. 870 */ 871 enum _ecore_status_t 872 ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 873 enum ecore_mib_read_type type) 874 { 875 enum _ecore_status_t rc = ECORE_SUCCESS; 876 877 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type); 878 if (rc) 879 return rc; 880 881 if (type == ECORE_DCBX_OPERATIONAL_MIB) { 882 ecore_dcbx_get_dscp_params(p_hwfn, &p_hwfn->p_dcbx_info->get); 883 884 rc = ecore_dcbx_process_mib_info(p_hwfn); 885 if (!rc) { 886 /* reconfigure tcs of QM queues according 887 * to negotiation results 888 */ 889 ecore_qm_reconf(p_hwfn, p_ptt); 890 891 /* update storm FW with negotiation results */ 892 ecore_sp_pf_update_dcbx(p_hwfn); 893 } 894 } 895 896 ecore_dcbx_get_params(p_hwfn, &p_hwfn->p_dcbx_info->get, type); 897 898 /* Update the DSCP to TC mapping bit if required */ 899 if ((type == ECORE_DCBX_OPERATIONAL_MIB) && 900 p_hwfn->p_dcbx_info->dscp_nig_update) { 901 u8 val = !!p_hwfn->p_dcbx_info->get.dscp.enabled; 902 903 ecore_wr(p_hwfn, p_ptt, NIG_REG_DSCP_TO_TC_MAP_ENABLE, val); 904 p_hwfn->p_dcbx_info->dscp_nig_update = false; 905 } 906 907 OSAL_DCBX_AEN(p_hwfn, type); 908 909 return rc; 910 } 911 912 enum _ecore_status_t ecore_dcbx_info_alloc(struct ecore_hwfn *p_hwfn) 913 { 914 p_hwfn->p_dcbx_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 915 sizeof(*p_hwfn->p_dcbx_info)); 916 if (!p_hwfn->p_dcbx_info) { 917 DP_NOTICE(p_hwfn, true, 918 "Failed to allocate `struct ecore_dcbx_info'"); 919 return ECORE_NOMEM; 920 } 921 922 p_hwfn->p_dcbx_info->iwarp_port = 923 p_hwfn->pf_params.rdma_pf_params.iwarp_port; 924 925 return ECORE_SUCCESS; 926 } 927 928 void ecore_dcbx_info_free(struct ecore_hwfn *p_hwfn) 929 { 930 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_dcbx_info); 931 } 932 933 static void ecore_dcbx_update_protocol_data(struct protocol_dcb_data *p_data, 934 struct ecore_dcbx_results *p_src, 935 enum dcbx_protocol_type type) 936 { 937 p_data->dcb_enable_flag = p_src->arr[type].enable; 938 p_data->dcb_priority = p_src->arr[type].priority; 939 p_data->dcb_tc = p_src->arr[type].tc; 940 p_data->dscp_enable_flag = p_src->arr[type].dscp_enable; 941 p_data->dscp_val = p_src->arr[type].dscp_val; 942 p_data->dcb_dont_add_vlan0 = p_src->arr[type].dont_add_vlan0; 943 } 944 945 /* Set pf update ramrod command params */ 946 void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src, 947 struct pf_update_ramrod_data *p_dest) 948 { 949 struct protocol_dcb_data *p_dcb_data; 950 u8 update_flag; 951 952 update_flag = p_src->arr[DCBX_PROTOCOL_ETH].update; 953 p_dest->update_eth_dcb_data_mode = update_flag; 954 update_flag = p_src->arr[DCBX_PROTOCOL_IWARP].update; 955 p_dest->update_iwarp_dcb_data_mode = update_flag; 956 957 p_dcb_data = &p_dest->eth_dcb_data; 958 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_ETH); 959 p_dcb_data = &p_dest->iwarp_dcb_data; 960 ecore_dcbx_update_protocol_data(p_dcb_data, p_src, DCBX_PROTOCOL_IWARP); 961 } 962 963 enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn, 964 struct ecore_dcbx_get *p_get, 965 enum ecore_mib_read_type type) 966 { 967 struct ecore_ptt *p_ptt; 968 enum _ecore_status_t rc; 969 970 if (IS_VF(p_hwfn->p_dev)) 971 return ECORE_INVAL; 972 973 p_ptt = ecore_ptt_acquire(p_hwfn); 974 if (!p_ptt) 975 return ECORE_TIMEOUT; 976 977 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type); 978 if (rc != ECORE_SUCCESS) 979 goto out; 980 981 ecore_dcbx_get_dscp_params(p_hwfn, p_get); 982 983 rc = ecore_dcbx_get_params(p_hwfn, p_get, type); 984 985 out: 986 ecore_ptt_release(p_hwfn, p_ptt); 987 return rc; 988 } 989 990 static void 991 ecore_dcbx_set_pfc_data(struct ecore_hwfn *p_hwfn, 992 u32 *pfc, struct ecore_dcbx_params *p_params) 993 { 994 u8 pfc_map = 0; 995 int i; 996 997 if (p_params->pfc.willing) 998 *pfc |= DCBX_PFC_WILLING_MASK; 999 else 1000 *pfc &= ~DCBX_PFC_WILLING_MASK; 1001 1002 if (p_params->pfc.enabled) 1003 *pfc |= DCBX_PFC_ENABLED_MASK; 1004 else 1005 *pfc &= ~DCBX_PFC_ENABLED_MASK; 1006 1007 *pfc &= ~DCBX_PFC_CAPS_MASK; 1008 *pfc |= (u32)p_params->pfc.max_tc << DCBX_PFC_CAPS_OFFSET; 1009 1010 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) 1011 if (p_params->pfc.prio[i]) 1012 pfc_map |= (1 << i); 1013 *pfc &= ~DCBX_PFC_PRI_EN_BITMAP_MASK; 1014 *pfc |= (pfc_map << DCBX_PFC_PRI_EN_BITMAP_OFFSET); 1015 1016 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "pfc = 0x%x\n", *pfc); 1017 } 1018 1019 static void 1020 ecore_dcbx_set_ets_data(struct ecore_hwfn *p_hwfn, 1021 struct dcbx_ets_feature *p_ets, 1022 struct ecore_dcbx_params *p_params) 1023 { 1024 u8 *bw_map, *tsa_map; 1025 u32 val; 1026 int i; 1027 1028 if (p_params->ets_willing) 1029 p_ets->flags |= DCBX_ETS_WILLING_MASK; 1030 else 1031 p_ets->flags &= ~DCBX_ETS_WILLING_MASK; 1032 1033 if (p_params->ets_cbs) 1034 p_ets->flags |= DCBX_ETS_CBS_MASK; 1035 else 1036 p_ets->flags &= ~DCBX_ETS_CBS_MASK; 1037 1038 if (p_params->ets_enabled) 1039 p_ets->flags |= DCBX_ETS_ENABLED_MASK; 1040 else 1041 p_ets->flags &= ~DCBX_ETS_ENABLED_MASK; 1042 1043 p_ets->flags &= ~DCBX_ETS_MAX_TCS_MASK; 1044 p_ets->flags |= (u32)p_params->max_ets_tc << DCBX_ETS_MAX_TCS_OFFSET; 1045 1046 bw_map = (u8 *)&p_ets->tc_bw_tbl[0]; 1047 tsa_map = (u8 *)&p_ets->tc_tsa_tbl[0]; 1048 p_ets->pri_tc_tbl[0] = 0; 1049 for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) { 1050 bw_map[i] = p_params->ets_tc_bw_tbl[i]; 1051 tsa_map[i] = p_params->ets_tc_tsa_tbl[i]; 1052 /* Copy the priority value to the corresponding 4 bits in the 1053 * traffic class table. 1054 */ 1055 val = (((u32)p_params->ets_pri_tc_tbl[i]) << ((7 - i) * 4)); 1056 p_ets->pri_tc_tbl[0] |= val; 1057 } 1058 for (i = 0; i < 2; i++) { 1059 p_ets->tc_bw_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_bw_tbl[i]); 1060 p_ets->tc_tsa_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_tsa_tbl[i]); 1061 } 1062 1063 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 1064 "flags = 0x%x pri_tc = 0x%x tc_bwl[] = {0x%x, 0x%x} tc_tsa = {0x%x, 0x%x}\n", 1065 p_ets->flags, p_ets->pri_tc_tbl[0], p_ets->tc_bw_tbl[0], 1066 p_ets->tc_bw_tbl[1], p_ets->tc_tsa_tbl[0], 1067 p_ets->tc_tsa_tbl[1]); 1068 } 1069 1070 static void 1071 ecore_dcbx_set_app_data(struct ecore_hwfn *p_hwfn, 1072 struct dcbx_app_priority_feature *p_app, 1073 struct ecore_dcbx_params *p_params, bool ieee) 1074 { 1075 u32 *entry; 1076 int i; 1077 1078 if (p_params->app_willing) 1079 p_app->flags |= DCBX_APP_WILLING_MASK; 1080 else 1081 p_app->flags &= ~DCBX_APP_WILLING_MASK; 1082 1083 if (p_params->app_valid) 1084 p_app->flags |= DCBX_APP_ENABLED_MASK; 1085 else 1086 p_app->flags &= ~DCBX_APP_ENABLED_MASK; 1087 1088 p_app->flags &= ~DCBX_APP_NUM_ENTRIES_MASK; 1089 p_app->flags |= (u32)p_params->num_app_entries << 1090 DCBX_APP_NUM_ENTRIES_OFFSET; 1091 1092 for (i = 0; i < p_params->num_app_entries; i++) { 1093 entry = &p_app->app_pri_tbl[i].entry; 1094 *entry = 0; 1095 if (ieee) { 1096 *entry &= ~(DCBX_APP_SF_IEEE_MASK | DCBX_APP_SF_MASK); 1097 switch (p_params->app_entry[i].sf_ieee) { 1098 case ECORE_DCBX_SF_IEEE_ETHTYPE: 1099 *entry |= ((u32)DCBX_APP_SF_IEEE_ETHTYPE << 1100 DCBX_APP_SF_IEEE_OFFSET); 1101 *entry |= ((u32)DCBX_APP_SF_ETHTYPE << 1102 DCBX_APP_SF_OFFSET); 1103 break; 1104 case ECORE_DCBX_SF_IEEE_TCP_PORT: 1105 *entry |= ((u32)DCBX_APP_SF_IEEE_TCP_PORT << 1106 DCBX_APP_SF_IEEE_OFFSET); 1107 *entry |= ((u32)DCBX_APP_SF_PORT << 1108 DCBX_APP_SF_OFFSET); 1109 break; 1110 case ECORE_DCBX_SF_IEEE_UDP_PORT: 1111 *entry |= ((u32)DCBX_APP_SF_IEEE_UDP_PORT << 1112 DCBX_APP_SF_IEEE_OFFSET); 1113 *entry |= ((u32)DCBX_APP_SF_PORT << 1114 DCBX_APP_SF_OFFSET); 1115 break; 1116 case ECORE_DCBX_SF_IEEE_TCP_UDP_PORT: 1117 *entry |= (u32)DCBX_APP_SF_IEEE_TCP_UDP_PORT << 1118 DCBX_APP_SF_IEEE_OFFSET; 1119 *entry |= ((u32)DCBX_APP_SF_PORT << 1120 DCBX_APP_SF_OFFSET); 1121 break; 1122 } 1123 } else { 1124 *entry &= ~DCBX_APP_SF_MASK; 1125 if (p_params->app_entry[i].ethtype) 1126 *entry |= ((u32)DCBX_APP_SF_ETHTYPE << 1127 DCBX_APP_SF_OFFSET); 1128 else 1129 *entry |= ((u32)DCBX_APP_SF_PORT << 1130 DCBX_APP_SF_OFFSET); 1131 } 1132 *entry &= ~DCBX_APP_PROTOCOL_ID_MASK; 1133 *entry |= ((u32)p_params->app_entry[i].proto_id << 1134 DCBX_APP_PROTOCOL_ID_OFFSET); 1135 *entry &= ~DCBX_APP_PRI_MAP_MASK; 1136 *entry |= ((u32)(p_params->app_entry[i].prio) << 1137 DCBX_APP_PRI_MAP_OFFSET); 1138 } 1139 1140 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_app->flags); 1141 } 1142 1143 static void 1144 ecore_dcbx_set_local_params(struct ecore_hwfn *p_hwfn, 1145 struct dcbx_local_params *local_admin, 1146 struct ecore_dcbx_set *params) 1147 { 1148 bool ieee = false; 1149 1150 local_admin->flags = 0; 1151 OSAL_MEMCPY(&local_admin->features, 1152 &p_hwfn->p_dcbx_info->operational.features, 1153 sizeof(local_admin->features)); 1154 1155 if (params->enabled) { 1156 local_admin->config = params->ver_num; 1157 ieee = !!(params->ver_num & DCBX_CONFIG_VERSION_IEEE); 1158 } else { 1159 local_admin->config = DCBX_CONFIG_VERSION_DISABLED; 1160 } 1161 1162 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Dcbx version = %d\n", 1163 local_admin->config); 1164 1165 if (params->override_flags & ECORE_DCBX_OVERRIDE_PFC_CFG) 1166 ecore_dcbx_set_pfc_data(p_hwfn, &local_admin->features.pfc, 1167 ¶ms->config.params); 1168 1169 if (params->override_flags & ECORE_DCBX_OVERRIDE_ETS_CFG) 1170 ecore_dcbx_set_ets_data(p_hwfn, &local_admin->features.ets, 1171 ¶ms->config.params); 1172 1173 if (params->override_flags & ECORE_DCBX_OVERRIDE_APP_CFG) 1174 ecore_dcbx_set_app_data(p_hwfn, &local_admin->features.app, 1175 ¶ms->config.params, ieee); 1176 } 1177 1178 static enum _ecore_status_t 1179 ecore_dcbx_set_dscp_params(struct ecore_hwfn *p_hwfn, 1180 struct dcb_dscp_map *p_dscp_map, 1181 struct ecore_dcbx_set *p_params) 1182 { 1183 int entry, i, j; 1184 u32 val; 1185 1186 OSAL_MEMCPY(p_dscp_map, &p_hwfn->p_dcbx_info->dscp_map, 1187 sizeof(*p_dscp_map)); 1188 1189 p_dscp_map->flags &= ~DCB_DSCP_ENABLE_MASK; 1190 if (p_params->dscp.enabled) 1191 p_dscp_map->flags |= DCB_DSCP_ENABLE_MASK; 1192 1193 for (i = 0, entry = 0; i < 8; i++) { 1194 val = 0; 1195 for (j = 0; j < 8; j++, entry++) 1196 val |= (((u32)p_params->dscp.dscp_pri_map[entry]) << 1197 (j * 4)); 1198 1199 p_dscp_map->dscp_pri_map[i] = OSAL_CPU_TO_BE32(val); 1200 } 1201 1202 p_hwfn->p_dcbx_info->dscp_nig_update = true; 1203 1204 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "flags = 0x%x\n", p_dscp_map->flags); 1205 DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, 1206 "pri_map[] = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 1207 p_dscp_map->dscp_pri_map[0], p_dscp_map->dscp_pri_map[1], 1208 p_dscp_map->dscp_pri_map[2], p_dscp_map->dscp_pri_map[3], 1209 p_dscp_map->dscp_pri_map[4], p_dscp_map->dscp_pri_map[5], 1210 p_dscp_map->dscp_pri_map[6], p_dscp_map->dscp_pri_map[7]); 1211 1212 return ECORE_SUCCESS; 1213 } 1214 1215 enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *p_hwfn, 1216 struct ecore_ptt *p_ptt, 1217 struct ecore_dcbx_set *params, 1218 bool hw_commit) 1219 { 1220 struct dcbx_local_params local_admin; 1221 struct ecore_dcbx_mib_meta_data data; 1222 struct dcb_dscp_map dscp_map; 1223 u32 resp = 0, param = 0; 1224 enum _ecore_status_t rc = ECORE_SUCCESS; 1225 1226 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set, params, 1227 sizeof(p_hwfn->p_dcbx_info->set)); 1228 if (!hw_commit) 1229 return ECORE_SUCCESS; 1230 1231 OSAL_MEMSET(&local_admin, 0, sizeof(local_admin)); 1232 ecore_dcbx_set_local_params(p_hwfn, &local_admin, params); 1233 1234 data.addr = p_hwfn->mcp_info->port_addr + 1235 offsetof(struct public_port, local_admin_dcbx_mib); 1236 data.local_admin = &local_admin; 1237 data.size = sizeof(struct dcbx_local_params); 1238 ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.local_admin, data.size); 1239 1240 if (params->override_flags & ECORE_DCBX_OVERRIDE_DSCP_CFG) { 1241 OSAL_MEMSET(&dscp_map, 0, sizeof(dscp_map)); 1242 ecore_dcbx_set_dscp_params(p_hwfn, &dscp_map, params); 1243 1244 data.addr = p_hwfn->mcp_info->port_addr + 1245 offsetof(struct public_port, dcb_dscp_map); 1246 data.dscp_map = &dscp_map; 1247 data.size = sizeof(struct dcb_dscp_map); 1248 ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.dscp_map, 1249 data.size); 1250 } 1251 1252 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_DCBX, 1253 1 << DRV_MB_PARAM_LLDP_SEND_OFFSET, &resp, ¶m); 1254 if (rc != ECORE_SUCCESS) 1255 DP_NOTICE(p_hwfn, false, 1256 "Failed to send DCBX update request\n"); 1257 1258 return rc; 1259 } 1260 1261 enum _ecore_status_t ecore_dcbx_get_config_params(struct ecore_hwfn *p_hwfn, 1262 struct ecore_dcbx_set *params) 1263 { 1264 struct ecore_dcbx_get *dcbx_info; 1265 int rc; 1266 1267 if (p_hwfn->p_dcbx_info->set.config.valid) { 1268 OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set, 1269 sizeof(struct ecore_dcbx_set)); 1270 return ECORE_SUCCESS; 1271 } 1272 1273 dcbx_info = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL, 1274 sizeof(*dcbx_info)); 1275 if (!dcbx_info) 1276 return ECORE_NOMEM; 1277 1278 OSAL_MEMSET(dcbx_info, 0, sizeof(*dcbx_info)); 1279 rc = ecore_dcbx_query_params(p_hwfn, dcbx_info, 1280 ECORE_DCBX_OPERATIONAL_MIB); 1281 if (rc) { 1282 OSAL_FREE(p_hwfn->p_dev, dcbx_info); 1283 return rc; 1284 } 1285 p_hwfn->p_dcbx_info->set.override_flags = 0; 1286 1287 p_hwfn->p_dcbx_info->set.ver_num = DCBX_CONFIG_VERSION_DISABLED; 1288 if (dcbx_info->operational.cee) 1289 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_CEE; 1290 if (dcbx_info->operational.ieee) 1291 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_IEEE; 1292 if (dcbx_info->operational.local) 1293 p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_STATIC; 1294 1295 p_hwfn->p_dcbx_info->set.enabled = dcbx_info->operational.enabled; 1296 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.dscp, 1297 &p_hwfn->p_dcbx_info->get.dscp, 1298 sizeof(struct ecore_dcbx_dscp_params)); 1299 OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.config.params, 1300 &dcbx_info->operational.params, 1301 sizeof(p_hwfn->p_dcbx_info->set.config.params)); 1302 p_hwfn->p_dcbx_info->set.config.valid = true; 1303 1304 OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set, 1305 sizeof(struct ecore_dcbx_set)); 1306 1307 OSAL_FREE(p_hwfn->p_dev, dcbx_info); 1308 1309 return ECORE_SUCCESS; 1310 } 1311 1312 enum _ecore_status_t ecore_lldp_register_tlv(struct ecore_hwfn *p_hwfn, 1313 struct ecore_ptt *p_ptt, 1314 enum ecore_lldp_agent agent, 1315 u8 tlv_type) 1316 { 1317 u32 mb_param = 0, mcp_resp = 0, mcp_param = 0, val = 0; 1318 enum _ecore_status_t rc = ECORE_SUCCESS; 1319 1320 switch (agent) { 1321 case ECORE_LLDP_NEAREST_BRIDGE: 1322 val = LLDP_NEAREST_BRIDGE; 1323 break; 1324 case ECORE_LLDP_NEAREST_NON_TPMR_BRIDGE: 1325 val = LLDP_NEAREST_NON_TPMR_BRIDGE; 1326 break; 1327 case ECORE_LLDP_NEAREST_CUSTOMER_BRIDGE: 1328 val = LLDP_NEAREST_CUSTOMER_BRIDGE; 1329 break; 1330 default: 1331 DP_ERR(p_hwfn, "Invalid agent type %d\n", agent); 1332 return ECORE_INVAL; 1333 } 1334 1335 SET_MFW_FIELD(mb_param, DRV_MB_PARAM_LLDP_AGENT, val); 1336 SET_MFW_FIELD(mb_param, DRV_MB_PARAM_LLDP_TLV_RX_TYPE, tlv_type); 1337 1338 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX, 1339 mb_param, &mcp_resp, &mcp_param); 1340 if (rc != ECORE_SUCCESS) 1341 DP_NOTICE(p_hwfn, false, "Failed to register TLV\n"); 1342 1343 return rc; 1344 } 1345 1346 enum _ecore_status_t 1347 ecore_lldp_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 1348 { 1349 struct ecore_dcbx_mib_meta_data data; 1350 enum _ecore_status_t rc = ECORE_SUCCESS; 1351 struct lldp_received_tlvs_s tlvs; 1352 int i; 1353 1354 for (i = 0; i < LLDP_MAX_LLDP_AGENTS; i++) { 1355 OSAL_MEM_ZERO(&data, sizeof(data)); 1356 data.addr = p_hwfn->mcp_info->port_addr + 1357 offsetof(struct public_port, lldp_received_tlvs[i]); 1358 data.lldp_tlvs = &tlvs; 1359 data.size = sizeof(tlvs); 1360 rc = ecore_dcbx_copy_mib(p_hwfn, p_ptt, &data, 1361 ECORE_DCBX_LLDP_TLVS); 1362 if (rc != ECORE_SUCCESS) { 1363 DP_NOTICE(p_hwfn, false, "Failed to read lldp TLVs\n"); 1364 return rc; 1365 } 1366 1367 if (!tlvs.length) 1368 continue; 1369 1370 for (i = 0; i < MAX_TLV_BUFFER; i++) 1371 tlvs.tlvs_buffer[i] = 1372 OSAL_CPU_TO_BE32(tlvs.tlvs_buffer[i]); 1373 1374 OSAL_LLDP_RX_TLVS(p_hwfn, tlvs.tlvs_buffer, tlvs.length); 1375 } 1376 1377 return rc; 1378 } 1379 1380 enum _ecore_status_t 1381 ecore_lldp_get_params(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1382 struct ecore_lldp_config_params *p_params) 1383 { 1384 struct lldp_config_params_s lldp_params; 1385 u32 addr, val; 1386 int i; 1387 1388 switch (p_params->agent) { 1389 case ECORE_LLDP_NEAREST_BRIDGE: 1390 val = LLDP_NEAREST_BRIDGE; 1391 break; 1392 case ECORE_LLDP_NEAREST_NON_TPMR_BRIDGE: 1393 val = LLDP_NEAREST_NON_TPMR_BRIDGE; 1394 break; 1395 case ECORE_LLDP_NEAREST_CUSTOMER_BRIDGE: 1396 val = LLDP_NEAREST_CUSTOMER_BRIDGE; 1397 break; 1398 default: 1399 DP_ERR(p_hwfn, "Invalid agent type %d\n", p_params->agent); 1400 return ECORE_INVAL; 1401 } 1402 1403 addr = p_hwfn->mcp_info->port_addr + 1404 offsetof(struct public_port, lldp_config_params[val]); 1405 1406 ecore_memcpy_from(p_hwfn, p_ptt, &lldp_params, addr, 1407 sizeof(lldp_params)); 1408 1409 p_params->tx_interval = GET_MFW_FIELD(lldp_params.config, 1410 LLDP_CONFIG_TX_INTERVAL); 1411 p_params->tx_hold = GET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_HOLD); 1412 p_params->tx_credit = GET_MFW_FIELD(lldp_params.config, 1413 LLDP_CONFIG_MAX_CREDIT); 1414 p_params->rx_enable = GET_MFW_FIELD(lldp_params.config, 1415 LLDP_CONFIG_ENABLE_RX); 1416 p_params->tx_enable = GET_MFW_FIELD(lldp_params.config, 1417 LLDP_CONFIG_ENABLE_TX); 1418 1419 OSAL_MEMCPY(p_params->chassis_id_tlv, lldp_params.local_chassis_id, 1420 sizeof(p_params->chassis_id_tlv)); 1421 for (i = 0; i < ECORE_LLDP_CHASSIS_ID_STAT_LEN; i++) 1422 p_params->chassis_id_tlv[i] = 1423 OSAL_BE32_TO_CPU(p_params->chassis_id_tlv[i]); 1424 1425 OSAL_MEMCPY(p_params->port_id_tlv, lldp_params.local_port_id, 1426 sizeof(p_params->port_id_tlv)); 1427 for (i = 0; i < ECORE_LLDP_PORT_ID_STAT_LEN; i++) 1428 p_params->port_id_tlv[i] = 1429 OSAL_BE32_TO_CPU(p_params->port_id_tlv[i]); 1430 1431 return ECORE_SUCCESS; 1432 } 1433 1434 enum _ecore_status_t 1435 ecore_lldp_set_params(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1436 struct ecore_lldp_config_params *p_params) 1437 { 1438 u32 mb_param = 0, mcp_resp = 0, mcp_param = 0; 1439 struct lldp_config_params_s lldp_params; 1440 enum _ecore_status_t rc = ECORE_SUCCESS; 1441 u32 addr, val; 1442 int i; 1443 1444 switch (p_params->agent) { 1445 case ECORE_LLDP_NEAREST_BRIDGE: 1446 val = LLDP_NEAREST_BRIDGE; 1447 break; 1448 case ECORE_LLDP_NEAREST_NON_TPMR_BRIDGE: 1449 val = LLDP_NEAREST_NON_TPMR_BRIDGE; 1450 break; 1451 case ECORE_LLDP_NEAREST_CUSTOMER_BRIDGE: 1452 val = LLDP_NEAREST_CUSTOMER_BRIDGE; 1453 break; 1454 default: 1455 DP_ERR(p_hwfn, "Invalid agent type %d\n", p_params->agent); 1456 return ECORE_INVAL; 1457 } 1458 1459 SET_MFW_FIELD(mb_param, DRV_MB_PARAM_LLDP_AGENT, val); 1460 addr = p_hwfn->mcp_info->port_addr + 1461 offsetof(struct public_port, lldp_config_params[val]); 1462 1463 OSAL_MEMSET(&lldp_params, 0, sizeof(lldp_params)); 1464 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_TX_INTERVAL, 1465 p_params->tx_interval); 1466 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_HOLD, p_params->tx_hold); 1467 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_MAX_CREDIT, 1468 p_params->tx_credit); 1469 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_ENABLE_RX, 1470 !!p_params->rx_enable); 1471 SET_MFW_FIELD(lldp_params.config, LLDP_CONFIG_ENABLE_TX, 1472 !!p_params->tx_enable); 1473 1474 for (i = 0; i < ECORE_LLDP_CHASSIS_ID_STAT_LEN; i++) 1475 p_params->chassis_id_tlv[i] = 1476 OSAL_CPU_TO_BE32(p_params->chassis_id_tlv[i]); 1477 OSAL_MEMCPY(lldp_params.local_chassis_id, p_params->chassis_id_tlv, 1478 sizeof(lldp_params.local_chassis_id)); 1479 1480 for (i = 0; i < ECORE_LLDP_PORT_ID_STAT_LEN; i++) 1481 p_params->port_id_tlv[i] = 1482 OSAL_CPU_TO_BE32(p_params->port_id_tlv[i]); 1483 OSAL_MEMCPY(lldp_params.local_port_id, p_params->port_id_tlv, 1484 sizeof(lldp_params.local_port_id)); 1485 1486 ecore_memcpy_to(p_hwfn, p_ptt, addr, &lldp_params, sizeof(lldp_params)); 1487 1488 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LLDP, 1489 mb_param, &mcp_resp, &mcp_param); 1490 if (rc != ECORE_SUCCESS) 1491 DP_NOTICE(p_hwfn, false, "SET_LLDP failed, error = %d\n", rc); 1492 1493 return rc; 1494 } 1495 1496 enum _ecore_status_t 1497 ecore_lldp_set_system_tlvs(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1498 struct ecore_lldp_sys_tlvs *p_params) 1499 { 1500 u32 mb_param = 0, mcp_resp = 0, mcp_param = 0; 1501 enum _ecore_status_t rc = ECORE_SUCCESS; 1502 struct lldp_system_tlvs_buffer_s lld_tlv_buf; 1503 u32 addr, *p_val; 1504 u8 len; 1505 int i; 1506 1507 p_val = (u32 *)p_params->buf; 1508 for (i = 0; i < ECORE_LLDP_SYS_TLV_SIZE / 4; i++) 1509 p_val[i] = OSAL_CPU_TO_BE32(p_val[i]); 1510 1511 OSAL_MEMSET(&lld_tlv_buf, 0, sizeof(lld_tlv_buf)); 1512 SET_MFW_FIELD(lld_tlv_buf.flags, LLDP_SYSTEM_TLV_VALID, 1); 1513 SET_MFW_FIELD(lld_tlv_buf.flags, LLDP_SYSTEM_TLV_MANDATORY, 1514 !!p_params->discard_mandatory_tlv); 1515 SET_MFW_FIELD(lld_tlv_buf.flags, LLDP_SYSTEM_TLV_LENGTH, 1516 p_params->buf_size); 1517 len = ECORE_LLDP_SYS_TLV_SIZE / 2; 1518 OSAL_MEMCPY(lld_tlv_buf.data, p_params->buf, len); 1519 1520 addr = p_hwfn->mcp_info->port_addr + 1521 offsetof(struct public_port, system_lldp_tlvs_buf); 1522 ecore_memcpy_to(p_hwfn, p_ptt, addr, &lld_tlv_buf, sizeof(lld_tlv_buf)); 1523 1524 if (p_params->buf_size > len) { 1525 addr = p_hwfn->mcp_info->port_addr + 1526 offsetof(struct public_port, system_lldp_tlvs_buf2); 1527 ecore_memcpy_to(p_hwfn, p_ptt, addr, &p_params->buf[len], 1528 ECORE_LLDP_SYS_TLV_SIZE / 2); 1529 } 1530 1531 rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LLDP, 1532 mb_param, &mcp_resp, &mcp_param); 1533 if (rc != ECORE_SUCCESS) 1534 DP_NOTICE(p_hwfn, false, "SET_LLDP failed, error = %d\n", rc); 1535 1536 return rc; 1537 } 1538