1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #ifndef __ECORE_H 8 #define __ECORE_H 9 10 /* @DPDK */ 11 #include <sys/stat.h> 12 #include <fcntl.h> 13 #include <unistd.h> 14 15 #define CONFIG_ECORE_BINARY_FW 16 #undef CONFIG_ECORE_ZIPPED_FW 17 18 #ifdef CONFIG_ECORE_ZIPPED_FW 19 #include <zlib.h> 20 #endif 21 22 #include "ecore_status.h" 23 #include "ecore_hsi_common.h" 24 #include "ecore_hsi_debug_tools.h" 25 #include "ecore_hsi_init_func.h" 26 #include "ecore_hsi_init_tool.h" 27 #include "ecore_proto_if.h" 28 #include "mcp_public.h" 29 30 #define ECORE_MAJOR_VERSION 8 31 #define ECORE_MINOR_VERSION 37 32 #define ECORE_REVISION_VERSION 20 33 #define ECORE_ENGINEERING_VERSION 0 34 35 #define ECORE_VERSION \ 36 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \ 37 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION) 38 39 #define STORM_FW_VERSION \ 40 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 41 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 42 43 #define IS_ECORE_PACING(p_hwfn) \ 44 (!!(p_hwfn->b_en_pacing)) 45 46 #define MAX_HWFNS_PER_DEVICE 2 47 #define NAME_SIZE 128 /* @DPDK */ 48 #define ECORE_WFQ_UNIT 100 49 #include "../qede_logs.h" /* @DPDK */ 50 51 #define ISCSI_BDQ_ID(_port_id) (_port_id) 52 #define FCOE_BDQ_ID(_port_id) (_port_id + 2) 53 /* Constants */ 54 #define ECORE_WID_SIZE (1024) 55 #define ECORE_MIN_WIDS (4) 56 57 /* Configurable */ 58 #define ECORE_PF_DEMS_SIZE (4) 59 60 /* cau states */ 61 enum ecore_coalescing_mode { 62 ECORE_COAL_MODE_DISABLE, 63 ECORE_COAL_MODE_ENABLE 64 }; 65 66 enum ecore_nvm_cmd { 67 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 68 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 69 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM, 70 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 71 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE, 72 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE, 73 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE, 74 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ, 75 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE, 76 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ, 77 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE, 78 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00 79 }; 80 81 #ifndef LINUX_REMOVE 82 #if !defined(CONFIG_ECORE_L2) 83 #define CONFIG_ECORE_L2 84 #define CONFIG_ECORE_SRIOV 85 #endif 86 #endif 87 88 /* helpers */ 89 #ifndef __EXTRACT__LINUX__ 90 #define MASK_FIELD(_name, _value) \ 91 ((_value) &= (_name##_MASK)) 92 93 #define FIELD_VALUE(_name, _value) \ 94 ((_value & _name##_MASK) << _name##_SHIFT) 95 96 #define SET_FIELD(value, name, flag) \ 97 do { \ 98 (value) &= ~(name##_MASK << name##_SHIFT); \ 99 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\ 100 } while (0) 101 102 #define GET_FIELD(value, name) \ 103 (((value) >> (name##_SHIFT)) & name##_MASK) 104 105 #define GET_MFW_FIELD(name, field) \ 106 (((name) & (field ## _MASK)) >> (field ## _OFFSET)) 107 108 #define SET_MFW_FIELD(name, field, value) \ 109 do { \ 110 (name) &= ~((field ## _MASK)); \ 111 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \ 112 } while (0) 113 #endif 114 115 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS) 116 { 117 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 118 (cid * ECORE_PF_DEMS_SIZE); 119 120 return db_addr; 121 } 122 123 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS) 124 { 125 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 126 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 127 128 return db_addr; 129 } 130 131 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 132 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \ 133 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1)) 134 135 #ifndef LINUX_REMOVE 136 #ifndef U64_HI 137 #define U64_HI(val) ((u32)(((u64)(val)) >> 32)) 138 #endif 139 140 #ifndef U64_LO 141 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff)) 142 #endif 143 #endif 144 145 #ifndef __EXTRACT__LINUX__ 146 enum DP_LEVEL { 147 ECORE_LEVEL_VERBOSE = 0x0, 148 ECORE_LEVEL_INFO = 0x1, 149 ECORE_LEVEL_NOTICE = 0x2, 150 ECORE_LEVEL_ERR = 0x3, 151 }; 152 153 #define ECORE_LOG_LEVEL_SHIFT (30) 154 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff) 155 #define ECORE_LOG_INFO_MASK (0x40000000) 156 #define ECORE_LOG_NOTICE_MASK (0x80000000) 157 158 enum DP_MODULE { 159 #ifndef LINUX_REMOVE 160 ECORE_MSG_DRV = 0x0001, 161 ECORE_MSG_PROBE = 0x0002, 162 ECORE_MSG_LINK = 0x0004, 163 ECORE_MSG_TIMER = 0x0008, 164 ECORE_MSG_IFDOWN = 0x0010, 165 ECORE_MSG_IFUP = 0x0020, 166 ECORE_MSG_RX_ERR = 0x0040, 167 ECORE_MSG_TX_ERR = 0x0080, 168 ECORE_MSG_TX_QUEUED = 0x0100, 169 ECORE_MSG_INTR = 0x0200, 170 ECORE_MSG_TX_DONE = 0x0400, 171 ECORE_MSG_RX_STATUS = 0x0800, 172 ECORE_MSG_PKTDATA = 0x1000, 173 ECORE_MSG_HW = 0x2000, 174 ECORE_MSG_WOL = 0x4000, 175 #endif 176 ECORE_MSG_SPQ = 0x10000, 177 ECORE_MSG_STATS = 0x20000, 178 ECORE_MSG_DCB = 0x40000, 179 ECORE_MSG_IOV = 0x80000, 180 ECORE_MSG_SP = 0x100000, 181 ECORE_MSG_STORAGE = 0x200000, 182 ECORE_MSG_OOO = 0x200000, 183 ECORE_MSG_CXT = 0x800000, 184 ECORE_MSG_LL2 = 0x1000000, 185 ECORE_MSG_ILT = 0x2000000, 186 ECORE_MSG_RDMA = 0x4000000, 187 ECORE_MSG_DEBUG = 0x8000000, 188 /* to be added...up to 0x8000000 */ 189 }; 190 #endif 191 192 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++) 193 194 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 195 (val == (cond1) ? true1 : \ 196 (val == (cond2) ? true2 : def)) 197 198 /* forward */ 199 struct ecore_ptt_pool; 200 struct ecore_spq; 201 struct ecore_sb_info; 202 struct ecore_sb_attn_info; 203 struct ecore_cxt_mngr; 204 struct ecore_dma_mem; 205 struct ecore_sb_sp_info; 206 struct ecore_ll2_info; 207 struct ecore_l2_info; 208 struct ecore_igu_info; 209 struct ecore_mcp_info; 210 struct ecore_dcbx_info; 211 struct ecore_llh_info; 212 213 struct ecore_rt_data { 214 u32 *init_val; 215 bool *b_valid; 216 }; 217 218 enum ecore_tunn_mode { 219 ECORE_MODE_L2GENEVE_TUNN, 220 ECORE_MODE_IPGENEVE_TUNN, 221 ECORE_MODE_L2GRE_TUNN, 222 ECORE_MODE_IPGRE_TUNN, 223 ECORE_MODE_VXLAN_TUNN, 224 }; 225 226 enum ecore_tunn_clss { 227 ECORE_TUNN_CLSS_MAC_VLAN, 228 ECORE_TUNN_CLSS_MAC_VNI, 229 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 230 ECORE_TUNN_CLSS_INNER_MAC_VNI, 231 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 232 MAX_ECORE_TUNN_CLSS, 233 }; 234 235 struct ecore_tunn_update_type { 236 bool b_update_mode; 237 bool b_mode_enabled; 238 enum ecore_tunn_clss tun_cls; 239 }; 240 241 struct ecore_tunn_update_udp_port { 242 bool b_update_port; 243 u16 port; 244 }; 245 246 struct ecore_tunnel_info { 247 struct ecore_tunn_update_type vxlan; 248 struct ecore_tunn_update_type l2_geneve; 249 struct ecore_tunn_update_type ip_geneve; 250 struct ecore_tunn_update_type l2_gre; 251 struct ecore_tunn_update_type ip_gre; 252 253 struct ecore_tunn_update_udp_port vxlan_port; 254 struct ecore_tunn_update_udp_port geneve_port; 255 256 bool b_update_rx_cls; 257 bool b_update_tx_cls; 258 }; 259 260 /* The PCI personality is not quite synonymous to protocol ID: 261 * 1. All personalities need CORE connections 262 * 2. The Ethernet personality may support also the RoCE/iWARP protocol 263 */ 264 enum ecore_pci_personality { 265 ECORE_PCI_ETH, 266 ECORE_PCI_FCOE, 267 ECORE_PCI_ISCSI, 268 ECORE_PCI_ETH_ROCE, 269 ECORE_PCI_ETH_IWARP, 270 ECORE_PCI_ETH_RDMA, 271 ECORE_PCI_DEFAULT /* default in shmem */ 272 }; 273 274 /* All VFs are symmetric, all counters are PF + all VFs */ 275 struct ecore_qm_iids { 276 u32 cids; 277 u32 vf_cids; 278 u32 tids; 279 }; 280 281 #define MAX_PF_PER_PORT 8 282 283 /* HW / FW resources, output of features supported below, most information 284 * is received from MFW. 285 */ 286 enum ecore_resources { 287 ECORE_L2_QUEUE, 288 ECORE_VPORT, 289 ECORE_RSS_ENG, 290 ECORE_PQ, 291 ECORE_RL, 292 ECORE_MAC, 293 ECORE_VLAN, 294 ECORE_RDMA_CNQ_RAM, 295 ECORE_ILT, 296 ECORE_LL2_QUEUE, 297 ECORE_CMDQS_CQS, 298 ECORE_RDMA_STATS_QUEUE, 299 ECORE_BDQ, 300 301 /* This is needed only internally for matching against the IGU. 302 * In case of legacy MFW, would be set to `0'. 303 */ 304 ECORE_SB, 305 306 ECORE_MAX_RESC, 307 }; 308 309 /* Features that require resources, given as input to the resource management 310 * algorithm, the output are the resources above 311 */ 312 enum ecore_feature { 313 ECORE_PF_L2_QUE, 314 ECORE_PF_TC, 315 ECORE_VF, 316 ECORE_EXTRA_VF_QUE, 317 ECORE_VMQ, 318 ECORE_RDMA_CNQ, 319 ECORE_ISCSI_CQ, 320 ECORE_FCOE_CQ, 321 ECORE_VF_L2_QUE, 322 ECORE_MAX_FEATURES, 323 }; 324 325 enum ecore_port_mode { 326 ECORE_PORT_MODE_DE_2X40G, 327 ECORE_PORT_MODE_DE_2X50G, 328 ECORE_PORT_MODE_DE_1X100G, 329 ECORE_PORT_MODE_DE_4X10G_F, 330 ECORE_PORT_MODE_DE_4X10G_E, 331 ECORE_PORT_MODE_DE_4X20G, 332 ECORE_PORT_MODE_DE_1X40G, 333 ECORE_PORT_MODE_DE_2X25G, 334 ECORE_PORT_MODE_DE_1X25G, 335 ECORE_PORT_MODE_DE_4X25G, 336 ECORE_PORT_MODE_DE_2X10G, 337 }; 338 339 enum ecore_dev_cap { 340 ECORE_DEV_CAP_ETH, 341 ECORE_DEV_CAP_FCOE, 342 ECORE_DEV_CAP_ISCSI, 343 ECORE_DEV_CAP_ROCE, 344 ECORE_DEV_CAP_IWARP 345 }; 346 347 #ifndef __EXTRACT__LINUX__ 348 enum ecore_hw_err_type { 349 ECORE_HW_ERR_FAN_FAIL, 350 ECORE_HW_ERR_MFW_RESP_FAIL, 351 ECORE_HW_ERR_HW_ATTN, 352 ECORE_HW_ERR_DMAE_FAIL, 353 ECORE_HW_ERR_RAMROD_FAIL, 354 ECORE_HW_ERR_FW_ASSERT, 355 }; 356 #endif 357 358 enum ecore_db_rec_exec { 359 DB_REC_DRY_RUN, 360 DB_REC_REAL_DEAL, 361 DB_REC_ONCE, 362 }; 363 364 struct ecore_hw_info { 365 /* PCI personality */ 366 enum ecore_pci_personality personality; 367 #define ECORE_IS_RDMA_PERSONALITY(dev) \ 368 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 369 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 370 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 371 #define ECORE_IS_ROCE_PERSONALITY(dev) \ 372 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 373 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 374 #define ECORE_IS_IWARP_PERSONALITY(dev) \ 375 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 376 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 377 #define ECORE_IS_L2_PERSONALITY(dev) \ 378 ((dev)->hw_info.personality == ECORE_PCI_ETH || \ 379 ECORE_IS_RDMA_PERSONALITY(dev)) 380 #define ECORE_IS_FCOE_PERSONALITY(dev) \ 381 ((dev)->hw_info.personality == ECORE_PCI_FCOE) 382 #define ECORE_IS_ISCSI_PERSONALITY(dev) \ 383 ((dev)->hw_info.personality == ECORE_PCI_ISCSI) 384 385 /* Resource Allocation scheme results */ 386 u32 resc_start[ECORE_MAX_RESC]; 387 u32 resc_num[ECORE_MAX_RESC]; 388 u32 feat_num[ECORE_MAX_FEATURES]; 389 390 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 391 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 392 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 393 RESC_NUM(_p_hwfn, resc)) 394 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 395 396 /* Amount of traffic classes HW supports */ 397 u8 num_hw_tc; 398 399 /* Amount of TCs which should be active according to DCBx or upper layer driver 400 * configuration 401 */ 402 403 u8 num_active_tc; 404 405 /* The traffic class used by PF for it's offloaded protocol */ 406 u8 offload_tc; 407 408 u32 concrete_fid; 409 u16 opaque_fid; 410 u16 ovlan; 411 u32 part_num[4]; 412 413 unsigned char hw_mac_addr[ETH_ALEN]; 414 u64 node_wwn; /* For FCoE only */ 415 u64 port_wwn; /* For FCoE only */ 416 417 u16 num_iscsi_conns; 418 u16 num_fcoe_conns; 419 420 struct ecore_igu_info *p_igu_info; 421 /* Sriov */ 422 u8 max_chains_per_vf; 423 424 u32 port_mode; 425 u32 hw_mode; 426 unsigned long device_capabilities; 427 428 /* Default DCBX mode */ 429 u8 dcbx_mode; 430 431 u16 mtu; 432 }; 433 434 /* maximun size of read/write commands (HW limit) */ 435 #define DMAE_MAX_RW_SIZE 0x2000 436 437 struct ecore_dmae_info { 438 /* Spinlock for synchronizing access to functions */ 439 osal_spinlock_t lock; 440 441 bool b_mem_ready; 442 443 u8 channel; 444 445 dma_addr_t completion_word_phys_addr; 446 447 /* The memory location where the DMAE writes the completion 448 * value when an operation is finished on this context. 449 */ 450 u32 *p_completion_word; 451 452 dma_addr_t intermediate_buffer_phys_addr; 453 454 /* An intermediate buffer for DMAE operations that use virtual 455 * addresses - data is DMA'd to/from this buffer and then 456 * memcpy'd to/from the virtual address 457 */ 458 u32 *p_intermediate_buffer; 459 460 dma_addr_t dmae_cmd_phys_addr; 461 struct dmae_cmd *p_dmae_cmd; 462 }; 463 464 struct ecore_wfq_data { 465 u32 default_min_speed; /* When wfq feature is not configured */ 466 u32 min_speed; /* when feature is configured for any 1 vport */ 467 bool configured; 468 }; 469 470 struct ecore_qm_info { 471 struct init_qm_pq_params *qm_pq_params; 472 struct init_qm_vport_params *qm_vport_params; 473 struct init_qm_port_params *qm_port_params; 474 u16 start_pq; 475 u8 start_vport; 476 u16 pure_lb_pq; 477 u16 offload_pq; 478 u16 pure_ack_pq; 479 u16 ooo_pq; 480 u16 first_vf_pq; 481 u16 first_mcos_pq; 482 u16 first_rl_pq; 483 u16 num_pqs; 484 u16 num_vf_pqs; 485 u8 num_vports; 486 u8 max_phys_tcs_per_port; 487 u8 ooo_tc; 488 bool pf_rl_en; 489 bool pf_wfq_en; 490 bool vport_rl_en; 491 bool vport_wfq_en; 492 u8 pf_wfq; 493 u32 pf_rl; 494 struct ecore_wfq_data *wfq_data; 495 u8 num_pf_rls; 496 }; 497 498 struct ecore_db_recovery_info { 499 osal_list_t list; 500 osal_spinlock_t lock; 501 u32 db_recovery_counter; 502 }; 503 504 struct storm_stats { 505 u32 address; 506 u32 len; 507 }; 508 509 struct ecore_fw_data { 510 #ifdef CONFIG_ECORE_BINARY_FW 511 struct fw_ver_info *fw_ver_info; 512 #endif 513 const u8 *modes_tree_buf; 514 union init_op *init_ops; 515 const u32 *arr_data; 516 u32 init_ops_size; 517 }; 518 519 enum ecore_mf_mode_bit { 520 /* Supports PF-classification based on tag */ 521 ECORE_MF_OVLAN_CLSS, 522 523 /* Supports PF-classification based on MAC */ 524 ECORE_MF_LLH_MAC_CLSS, 525 526 /* Supports PF-classification based on protocol type */ 527 ECORE_MF_LLH_PROTO_CLSS, 528 529 /* Requires a default PF to be set */ 530 ECORE_MF_NEED_DEF_PF, 531 532 /* Allow LL2 to multicast/broadcast */ 533 ECORE_MF_LL2_NON_UNICAST, 534 535 /* Allow Cross-PF [& child VFs] Tx-switching */ 536 ECORE_MF_INTER_PF_SWITCH, 537 538 /* TODO - if we ever re-utilize any of this logic, we can rename */ 539 ECORE_MF_UFP_SPECIFIC, 540 541 ECORE_MF_DISABLE_ARFS, 542 543 /* Use vlan for steering */ 544 ECORE_MF_8021Q_TAGGING, 545 546 /* Use stag for steering */ 547 ECORE_MF_8021AD_TAGGING, 548 549 /* Allow FIP discovery fallback */ 550 ECORE_MF_FIP_SPECIAL, 551 }; 552 553 enum ecore_ufp_mode { 554 ECORE_UFP_MODE_ETS, 555 ECORE_UFP_MODE_VNIC_BW, 556 }; 557 558 enum ecore_ufp_pri_type { 559 ECORE_UFP_PRI_OS, 560 ECORE_UFP_PRI_VNIC 561 }; 562 563 struct ecore_ufp_info { 564 enum ecore_ufp_pri_type pri_type; 565 enum ecore_ufp_mode mode; 566 u8 tc; 567 }; 568 569 enum BAR_ID { 570 BAR_ID_0, /* used for GRC */ 571 BAR_ID_1 /* Used for doorbells */ 572 }; 573 574 struct ecore_hwfn { 575 struct ecore_dev *p_dev; 576 u8 my_id; /* ID inside the PF */ 577 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 578 u8 rel_pf_id; /* Relative to engine*/ 579 u8 abs_pf_id; 580 #define ECORE_PATH_ID(_p_hwfn) \ 581 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0) 582 u8 port_id; 583 bool b_active; 584 585 u32 dp_module; 586 u8 dp_level; 587 char name[NAME_SIZE]; 588 void *dp_ctx; 589 590 bool first_on_engine; 591 bool hw_init_done; 592 593 u8 num_funcs_on_engine; 594 u8 enabled_func_idx; 595 596 /* BAR access */ 597 void OSAL_IOMEM *regview; 598 void OSAL_IOMEM *doorbells; 599 u64 db_phys_addr; 600 unsigned long db_size; 601 602 /* PTT pool */ 603 struct ecore_ptt_pool *p_ptt_pool; 604 605 /* HW info */ 606 struct ecore_hw_info hw_info; 607 608 /* rt_array (for init-tool) */ 609 struct ecore_rt_data rt_data; 610 611 /* SPQ */ 612 struct ecore_spq *p_spq; 613 614 /* EQ */ 615 struct ecore_eq *p_eq; 616 617 /* Consolidate Q*/ 618 struct ecore_consq *p_consq; 619 620 /* Slow-Path definitions */ 621 osal_dpc_t sp_dpc; 622 bool b_sp_dpc_enabled; 623 624 struct ecore_ptt *p_main_ptt; 625 struct ecore_ptt *p_dpc_ptt; 626 627 struct ecore_sb_sp_info *p_sp_sb; 628 struct ecore_sb_attn_info *p_sb_attn; 629 630 /* Protocol related */ 631 bool using_ll2; 632 struct ecore_ll2_info *p_ll2_info; 633 struct ecore_ooo_info *p_ooo_info; 634 struct ecore_iscsi_info *p_iscsi_info; 635 struct ecore_fcoe_info *p_fcoe_info; 636 struct ecore_rdma_info *p_rdma_info; 637 struct ecore_pf_params pf_params; 638 639 bool b_rdma_enabled_in_prs; 640 u32 rdma_prs_search_reg; 641 642 struct ecore_cxt_mngr *p_cxt_mngr; 643 644 /* Flag indicating whether interrupts are enabled or not*/ 645 bool b_int_enabled; 646 bool b_int_requested; 647 648 /* True if the driver requests for the link */ 649 bool b_drv_link_init; 650 651 struct ecore_vf_iov *vf_iov_info; 652 struct ecore_pf_iov *pf_iov_info; 653 struct ecore_mcp_info *mcp_info; 654 struct ecore_dcbx_info *p_dcbx_info; 655 struct ecore_ufp_info ufp_info; 656 657 struct ecore_dmae_info dmae_info; 658 659 /* QM init */ 660 struct ecore_qm_info qm_info; 661 662 #ifdef CONFIG_ECORE_ZIPPED_FW 663 /* Buffer for unzipping firmware data */ 664 void *unzip_buf; 665 #endif 666 667 struct dbg_tools_data dbg_info; 668 void *dbg_user_info; 669 670 struct z_stream_s *stream; 671 672 /* PWM region specific data */ 673 u32 dpi_size; 674 u32 dpi_count; 675 u32 dpi_start_offset; /* this is used to 676 * calculate th 677 * doorbell address 678 */ 679 680 /* If one of the following is set then EDPM shouldn't be used */ 681 u8 dcbx_no_edpm; 682 u8 db_bar_no_edpm; 683 684 /* L2-related */ 685 struct ecore_l2_info *p_l2_info; 686 687 /* Mechanism for recovering from doorbell drop */ 688 struct ecore_db_recovery_info db_recovery_info; 689 690 /* Enable/disable pacing, if request to enable then 691 * IOV and mcos configuration will be skipped. 692 * this actually reflects the value requested in 693 * struct ecore_hw_prepare_params by ecore client. 694 */ 695 bool b_en_pacing; 696 697 /* @DPDK */ 698 struct ecore_ptt *p_arfs_ptt; 699 }; 700 701 enum ecore_mf_mode { 702 ECORE_MF_DEFAULT, 703 ECORE_MF_OVLAN, 704 ECORE_MF_NPAR, 705 ECORE_MF_UFP, 706 }; 707 708 /* @DPDK */ 709 struct ecore_dbg_feature { 710 u8 *dump_buf; 711 u32 buf_size; 712 u32 dumped_dwords; 713 }; 714 715 enum qed_dbg_features { 716 DBG_FEATURE_BUS, 717 DBG_FEATURE_GRC, 718 DBG_FEATURE_IDLE_CHK, 719 DBG_FEATURE_MCP_TRACE, 720 DBG_FEATURE_REG_FIFO, 721 DBG_FEATURE_PROTECTION_OVERRIDE, 722 DBG_FEATURE_NUM 723 }; 724 725 enum ecore_dev_type { 726 ECORE_DEV_TYPE_BB, 727 ECORE_DEV_TYPE_AH, 728 }; 729 730 struct ecore_dev { 731 u32 dp_module; 732 u8 dp_level; 733 char name[NAME_SIZE]; 734 void *dp_ctx; 735 736 enum ecore_dev_type type; 737 /* Translate type/revision combo into the proper conditions */ 738 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB) 739 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev)) 740 #ifndef ASIC_ONLY 741 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \ 742 (CHIP_REV_IS_TEDIBEAR(dev))) 743 #else 744 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) 745 #endif 746 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH) 747 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev) 748 #define ECORE_IS_E4(dev) (ECORE_IS_BB(dev) || ECORE_IS_AH(dev)) 749 750 u16 vendor_id; 751 u16 device_id; 752 #define ECORE_DEV_ID_MASK 0xff00 753 #define ECORE_DEV_ID_MASK_BB 0x1600 754 #define ECORE_DEV_ID_MASK_AH 0x8000 755 756 u16 chip_num; 757 #define CHIP_NUM_MASK 0xffff 758 #define CHIP_NUM_SHIFT 0 759 760 u8 chip_rev; 761 #define CHIP_REV_MASK 0xf 762 #define CHIP_REV_SHIFT 0 763 #ifndef ASIC_ONLY 764 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) 765 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) 766 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) 767 #define CHIP_REV_IS_EMUL(_p_dev) \ 768 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev)) 769 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) 770 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) 771 #define CHIP_REV_IS_FPGA(_p_dev) \ 772 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev)) 773 #define CHIP_REV_IS_SLOW(_p_dev) \ 774 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) 775 #define CHIP_REV_IS_A0(_p_dev) \ 776 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \ 777 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)) 778 #define CHIP_REV_IS_B0(_p_dev) \ 779 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \ 780 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)) 781 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) 782 #else 783 #define CHIP_REV_IS_A0(_p_dev) \ 784 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal) 785 #define CHIP_REV_IS_B0(_p_dev) \ 786 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal) 787 #endif 788 789 u8 chip_metal; 790 #define CHIP_METAL_MASK 0xff 791 #define CHIP_METAL_SHIFT 0 792 793 u8 chip_bond_id; 794 #define CHIP_BOND_ID_MASK 0xff 795 #define CHIP_BOND_ID_SHIFT 0 796 797 u8 num_engines; 798 u8 num_ports; 799 u8 num_ports_in_engine; 800 u8 num_funcs_in_port; 801 802 u8 path_id; 803 804 unsigned long mf_bits; 805 enum ecore_mf_mode mf_mode; 806 #define IS_MF_DEFAULT(_p_hwfn) \ 807 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) 808 #define IS_MF_SI(_p_hwfn) \ 809 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) 810 #define IS_MF_SD(_p_hwfn) \ 811 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) 812 813 int pcie_width; 814 int pcie_speed; 815 816 /* Add MF related configuration */ 817 u8 mcp_rev; 818 u8 boot_mode; 819 820 u8 wol; 821 822 u32 int_mode; 823 enum ecore_coalescing_mode int_coalescing_mode; 824 u16 rx_coalesce_usecs; 825 u16 tx_coalesce_usecs; 826 827 /* Start Bar offset of first hwfn */ 828 void OSAL_IOMEM *regview; 829 void OSAL_IOMEM *doorbells; 830 u64 db_phys_addr; 831 unsigned long db_size; 832 833 /* PCI */ 834 u8 cache_shift; 835 836 /* Init */ 837 const struct iro *iro_arr; 838 #define IRO (p_hwfn->p_dev->iro_arr) 839 840 /* HW functions */ 841 u8 num_hwfns; 842 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 843 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) 844 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1) 845 846 /* Engine affinity */ 847 u8 l2_affin_hint; 848 u8 fir_affin; 849 u8 iwarp_affin; 850 /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */ 851 #define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin]) 852 /* Macro for getting the engine-affinitized hwfn for iWARP */ 853 #define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin]) 854 /* Generic macro for getting the engine-affinitized hwfn */ 855 #define ECORE_AFFIN_HWFN(dev) \ 856 (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \ 857 ECORE_IWARP_AFFIN_HWFN(dev) : \ 858 ECORE_FIR_AFFIN_HWFN(dev)) 859 /* Macro for getting the index (0/1) of the engine-affinitized hwfn */ 860 #define ECORE_AFFIN_HWFN_IDX(dev) \ 861 (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1) 862 863 /* SRIOV */ 864 struct ecore_hw_sriov_info *p_iov_info; 865 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info) 866 struct ecore_tunnel_info tunnel; 867 bool b_is_vf; 868 bool b_dont_override_vf_msix; 869 870 u32 drv_type; 871 872 u32 rdma_max_sge; 873 u32 rdma_max_inline; 874 u32 rdma_max_srq_sge; 875 876 struct ecore_eth_stats *reset_stats; 877 struct ecore_fw_data *fw_data; 878 879 u32 mcp_nvm_resp; 880 881 /* Recovery */ 882 bool recov_in_prog; 883 884 /* Indicates whether should prevent attentions from being reasserted */ 885 886 bool attn_clr_en; 887 888 /* Indicates whether allowing the MFW to collect a crash dump */ 889 bool allow_mdump; 890 891 /* Indicates if the reg_fifo is checked after any register access */ 892 bool chk_reg_fifo; 893 894 #ifndef ASIC_ONLY 895 bool b_is_emul_full; 896 #endif 897 /* LLH info */ 898 u8 ppfid_bitmap; 899 struct ecore_llh_info *p_llh_info; 900 901 /* Indicates whether this PF serves a storage target */ 902 bool b_is_target; 903 904 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */ 905 void *firmware; 906 u64 fw_len; 907 #endif 908 909 /* @DPDK */ 910 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM]; 911 u8 engine_for_debug; 912 }; 913 914 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \ 915 : MAX_NUM_VFS_K2) 916 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 917 : MAX_NUM_L2_QUEUES_K2) 918 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 919 : MAX_NUM_PORTS_K2) 920 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 921 : MAX_SB_PER_PATH_K2) 922 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \ 923 : MAX_NUM_PFS_K2) 924 925 #define CRC8_TABLE_SIZE 256 926 927 /** 928 * @brief ecore_concrete_to_sw_fid - get the sw function id from 929 * the concrete value. 930 * 931 * @param concrete_fid 932 * 933 * @return OSAL_INLINE u8 934 */ 935 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid) 936 { 937 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 938 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 939 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID); 940 u8 sw_fid; 941 942 if (vf_valid) 943 sw_fid = vfid + MAX_NUM_PFS; 944 else 945 sw_fid = pfid; 946 947 return sw_fid; 948 } 949 950 #define PKT_LB_TC 9 951 #define MAX_NUM_VOQS_E4 20 952 953 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate); 954 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 955 struct ecore_ptt *p_ptt, 956 u32 min_pf_rate); 957 958 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw); 959 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw); 960 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); 961 int ecore_device_num_engines(struct ecore_dev *p_dev); 962 int ecore_device_num_ports(struct ecore_dev *p_dev); 963 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb, 964 u8 *mac); 965 966 /* Flags for indication of required queues */ 967 #define PQ_FLAGS_RLS (1 << 0) 968 #define PQ_FLAGS_MCOS (1 << 1) 969 #define PQ_FLAGS_LB (1 << 2) 970 #define PQ_FLAGS_OOO (1 << 3) 971 #define PQ_FLAGS_ACK (1 << 4) 972 #define PQ_FLAGS_OFLD (1 << 5) 973 #define PQ_FLAGS_VFS (1 << 6) 974 #define PQ_FLAGS_LLT (1 << 7) 975 976 /* physical queue index for cm context intialization */ 977 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags); 978 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc); 979 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf); 980 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl); 981 982 /* qm vport for rate limit configuration */ 983 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl); 984 985 const char *ecore_hw_get_resc_name(enum ecore_resources res_id); 986 987 /* doorbell recovery mechanism */ 988 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn); 989 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, 990 enum ecore_db_rec_exec); 991 992 bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn); 993 994 /* amount of resources used in qm init */ 995 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn); 996 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn); 997 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn); 998 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn); 999 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn); 1000 1001 #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ 1002 ecore_device_num_ports((_p_hwfn)->p_dev)) 1003 1004 /* The PFID<->PPFID calculation is based on the relative index of a PF on its 1005 * port. In BB there is a bug in the LLH in which the PPFID is actually engine 1006 * based, and thus it equals the PFID. 1007 */ 1008 #define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \ 1009 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \ 1010 (abs_ppfid) : \ 1011 (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \ 1012 MFW_PORT(_p_hwfn)) 1013 #define ECORE_PPFID_BY_PFID(_p_hwfn) \ 1014 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \ 1015 (_p_hwfn)->rel_pf_id : \ 1016 (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine) 1017 1018 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn, 1019 struct ecore_ptt *p_ptt, u32 addr, 1020 u32 val); 1021 1022 /* Utility functions for dumping the content of the NIG LLH filters */ 1023 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid); 1024 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev); 1025 1026 #endif /* __ECORE_H */ 1027