1 /* 2 * Copyright (c) 2016 QLogic Corporation. 3 * All rights reserved. 4 * www.qlogic.com 5 * 6 * See LICENSE.qede_pmd for copyright and licensing details. 7 */ 8 9 #ifndef __ECORE_H 10 #define __ECORE_H 11 12 /* @DPDK */ 13 #include <sys/stat.h> 14 #include <fcntl.h> 15 #include <unistd.h> 16 17 #define CONFIG_ECORE_BINARY_FW 18 #undef CONFIG_ECORE_ZIPPED_FW 19 20 #ifdef CONFIG_ECORE_ZIPPED_FW 21 #include <zlib.h> 22 #endif 23 24 #include "ecore_hsi_common.h" 25 #include "ecore_hsi_debug_tools.h" 26 #include "ecore_hsi_init_func.h" 27 #include "ecore_hsi_init_tool.h" 28 #include "ecore_proto_if.h" 29 #include "mcp_public.h" 30 31 #define ECORE_MAJOR_VERSION 8 32 #define ECORE_MINOR_VERSION 30 33 #define ECORE_REVISION_VERSION 8 34 #define ECORE_ENGINEERING_VERSION 0 35 36 #define ECORE_VERSION \ 37 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \ 38 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION) 39 40 #define STORM_FW_VERSION \ 41 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 42 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 43 44 #define MAX_HWFNS_PER_DEVICE 2 45 #define NAME_SIZE 128 /* @DPDK */ 46 #define ECORE_WFQ_UNIT 100 47 #include "../qede_logs.h" /* @DPDK */ 48 49 #define ISCSI_BDQ_ID(_port_id) (_port_id) 50 #define FCOE_BDQ_ID(_port_id) (_port_id + 2) 51 /* Constants */ 52 #define ECORE_WID_SIZE (1024) 53 #define ECORE_MIN_WIDS (4) 54 55 /* Configurable */ 56 #define ECORE_PF_DEMS_SIZE (4) 57 58 /* cau states */ 59 enum ecore_coalescing_mode { 60 ECORE_COAL_MODE_DISABLE, 61 ECORE_COAL_MODE_ENABLE 62 }; 63 64 enum ecore_nvm_cmd { 65 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 66 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 67 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM, 68 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 69 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE, 70 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE, 71 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE, 72 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ, 73 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE, 74 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ, 75 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE, 76 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00 77 }; 78 79 #ifndef LINUX_REMOVE 80 #if !defined(CONFIG_ECORE_L2) 81 #define CONFIG_ECORE_L2 82 #define CONFIG_ECORE_SRIOV 83 #endif 84 #endif 85 86 /* helpers */ 87 #ifndef __EXTRACT__LINUX__ 88 #define MASK_FIELD(_name, _value) \ 89 ((_value) &= (_name##_MASK)) 90 91 #define FIELD_VALUE(_name, _value) \ 92 ((_value & _name##_MASK) << _name##_SHIFT) 93 94 #define SET_FIELD(value, name, flag) \ 95 do { \ 96 (value) &= ~(name##_MASK << name##_SHIFT); \ 97 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\ 98 } while (0) 99 100 #define GET_FIELD(value, name) \ 101 (((value) >> (name##_SHIFT)) & name##_MASK) 102 103 #define GET_MFW_FIELD(name, field) \ 104 (((name) & (field ## _MASK)) >> (field ## _OFFSET)) 105 106 #define SET_MFW_FIELD(name, field, value) \ 107 do { \ 108 (name) &= ~((field ## _MASK)); \ 109 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \ 110 } while (0) 111 #endif 112 113 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS) 114 { 115 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 116 (cid * ECORE_PF_DEMS_SIZE); 117 118 return db_addr; 119 } 120 121 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS) 122 { 123 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 124 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 125 126 return db_addr; 127 } 128 129 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 130 ((sizeof(type_name) + (u32)(1 << (p_hwfn->p_dev->cache_shift)) - 1) & \ 131 ~((1 << (p_hwfn->p_dev->cache_shift)) - 1)) 132 133 #ifndef LINUX_REMOVE 134 #ifndef U64_HI 135 #define U64_HI(val) ((u32)(((u64)(val)) >> 32)) 136 #endif 137 138 #ifndef U64_LO 139 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff)) 140 #endif 141 #endif 142 143 #ifndef __EXTRACT__LINUX__ 144 enum DP_LEVEL { 145 ECORE_LEVEL_VERBOSE = 0x0, 146 ECORE_LEVEL_INFO = 0x1, 147 ECORE_LEVEL_NOTICE = 0x2, 148 ECORE_LEVEL_ERR = 0x3, 149 }; 150 151 #define ECORE_LOG_LEVEL_SHIFT (30) 152 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff) 153 #define ECORE_LOG_INFO_MASK (0x40000000) 154 #define ECORE_LOG_NOTICE_MASK (0x80000000) 155 156 enum DP_MODULE { 157 #ifndef LINUX_REMOVE 158 ECORE_MSG_DRV = 0x0001, 159 ECORE_MSG_PROBE = 0x0002, 160 ECORE_MSG_LINK = 0x0004, 161 ECORE_MSG_TIMER = 0x0008, 162 ECORE_MSG_IFDOWN = 0x0010, 163 ECORE_MSG_IFUP = 0x0020, 164 ECORE_MSG_RX_ERR = 0x0040, 165 ECORE_MSG_TX_ERR = 0x0080, 166 ECORE_MSG_TX_QUEUED = 0x0100, 167 ECORE_MSG_INTR = 0x0200, 168 ECORE_MSG_TX_DONE = 0x0400, 169 ECORE_MSG_RX_STATUS = 0x0800, 170 ECORE_MSG_PKTDATA = 0x1000, 171 ECORE_MSG_HW = 0x2000, 172 ECORE_MSG_WOL = 0x4000, 173 #endif 174 ECORE_MSG_SPQ = 0x10000, 175 ECORE_MSG_STATS = 0x20000, 176 ECORE_MSG_DCB = 0x40000, 177 ECORE_MSG_IOV = 0x80000, 178 ECORE_MSG_SP = 0x100000, 179 ECORE_MSG_STORAGE = 0x200000, 180 ECORE_MSG_OOO = 0x200000, 181 ECORE_MSG_CXT = 0x800000, 182 ECORE_MSG_LL2 = 0x1000000, 183 ECORE_MSG_ILT = 0x2000000, 184 ECORE_MSG_RDMA = 0x4000000, 185 ECORE_MSG_DEBUG = 0x8000000, 186 /* to be added...up to 0x8000000 */ 187 }; 188 #endif 189 190 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++) 191 192 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 193 (val == (cond1) ? true1 : \ 194 (val == (cond2) ? true2 : def)) 195 196 /* forward */ 197 struct ecore_ptt_pool; 198 struct ecore_spq; 199 struct ecore_sb_info; 200 struct ecore_sb_attn_info; 201 struct ecore_cxt_mngr; 202 struct ecore_dma_mem; 203 struct ecore_sb_sp_info; 204 struct ecore_ll2_info; 205 struct ecore_l2_info; 206 struct ecore_igu_info; 207 struct ecore_mcp_info; 208 struct ecore_dcbx_info; 209 210 struct ecore_rt_data { 211 u32 *init_val; 212 bool *b_valid; 213 }; 214 215 enum ecore_tunn_mode { 216 ECORE_MODE_L2GENEVE_TUNN, 217 ECORE_MODE_IPGENEVE_TUNN, 218 ECORE_MODE_L2GRE_TUNN, 219 ECORE_MODE_IPGRE_TUNN, 220 ECORE_MODE_VXLAN_TUNN, 221 }; 222 223 enum ecore_tunn_clss { 224 ECORE_TUNN_CLSS_MAC_VLAN, 225 ECORE_TUNN_CLSS_MAC_VNI, 226 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 227 ECORE_TUNN_CLSS_INNER_MAC_VNI, 228 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 229 MAX_ECORE_TUNN_CLSS, 230 }; 231 232 struct ecore_tunn_update_type { 233 bool b_update_mode; 234 bool b_mode_enabled; 235 enum ecore_tunn_clss tun_cls; 236 }; 237 238 struct ecore_tunn_update_udp_port { 239 bool b_update_port; 240 u16 port; 241 }; 242 243 struct ecore_tunnel_info { 244 struct ecore_tunn_update_type vxlan; 245 struct ecore_tunn_update_type l2_geneve; 246 struct ecore_tunn_update_type ip_geneve; 247 struct ecore_tunn_update_type l2_gre; 248 struct ecore_tunn_update_type ip_gre; 249 250 struct ecore_tunn_update_udp_port vxlan_port; 251 struct ecore_tunn_update_udp_port geneve_port; 252 253 bool b_update_rx_cls; 254 bool b_update_tx_cls; 255 }; 256 257 /* The PCI personality is not quite synonymous to protocol ID: 258 * 1. All personalities need CORE connections 259 * 2. The Ethernet personality may support also the RoCE/iWARP protocol 260 */ 261 enum ecore_pci_personality { 262 ECORE_PCI_ETH, 263 ECORE_PCI_FCOE, 264 ECORE_PCI_ISCSI, 265 ECORE_PCI_ETH_ROCE, 266 ECORE_PCI_ETH_IWARP, 267 ECORE_PCI_ETH_RDMA, 268 ECORE_PCI_DEFAULT /* default in shmem */ 269 }; 270 271 /* All VFs are symmetric, all counters are PF + all VFs */ 272 struct ecore_qm_iids { 273 u32 cids; 274 u32 vf_cids; 275 u32 tids; 276 }; 277 278 #define MAX_PF_PER_PORT 8 279 280 /* HW / FW resources, output of features supported below, most information 281 * is received from MFW. 282 */ 283 enum ecore_resources { 284 ECORE_L2_QUEUE, 285 ECORE_VPORT, 286 ECORE_RSS_ENG, 287 ECORE_PQ, 288 ECORE_RL, 289 ECORE_MAC, 290 ECORE_VLAN, 291 ECORE_RDMA_CNQ_RAM, 292 ECORE_ILT, 293 ECORE_LL2_QUEUE, 294 ECORE_CMDQS_CQS, 295 ECORE_RDMA_STATS_QUEUE, 296 ECORE_BDQ, 297 298 /* This is needed only internally for matching against the IGU. 299 * In case of legacy MFW, would be set to `0'. 300 */ 301 ECORE_SB, 302 303 ECORE_MAX_RESC, 304 }; 305 306 /* Features that require resources, given as input to the resource management 307 * algorithm, the output are the resources above 308 */ 309 enum ecore_feature { 310 ECORE_PF_L2_QUE, 311 ECORE_PF_TC, 312 ECORE_VF, 313 ECORE_EXTRA_VF_QUE, 314 ECORE_VMQ, 315 ECORE_RDMA_CNQ, 316 ECORE_ISCSI_CQ, 317 ECORE_FCOE_CQ, 318 ECORE_VF_L2_QUE, 319 ECORE_MAX_FEATURES, 320 }; 321 322 enum ecore_port_mode { 323 ECORE_PORT_MODE_DE_2X40G, 324 ECORE_PORT_MODE_DE_2X50G, 325 ECORE_PORT_MODE_DE_1X100G, 326 ECORE_PORT_MODE_DE_4X10G_F, 327 ECORE_PORT_MODE_DE_4X10G_E, 328 ECORE_PORT_MODE_DE_4X20G, 329 ECORE_PORT_MODE_DE_1X40G, 330 ECORE_PORT_MODE_DE_2X25G, 331 ECORE_PORT_MODE_DE_1X25G, 332 ECORE_PORT_MODE_DE_4X25G, 333 ECORE_PORT_MODE_DE_2X10G, 334 }; 335 336 enum ecore_dev_cap { 337 ECORE_DEV_CAP_ETH, 338 ECORE_DEV_CAP_FCOE, 339 ECORE_DEV_CAP_ISCSI, 340 ECORE_DEV_CAP_ROCE, 341 ECORE_DEV_CAP_IWARP 342 }; 343 344 #ifndef __EXTRACT__LINUX__ 345 enum ecore_hw_err_type { 346 ECORE_HW_ERR_FAN_FAIL, 347 ECORE_HW_ERR_MFW_RESP_FAIL, 348 ECORE_HW_ERR_HW_ATTN, 349 ECORE_HW_ERR_DMAE_FAIL, 350 ECORE_HW_ERR_RAMROD_FAIL, 351 ECORE_HW_ERR_FW_ASSERT, 352 }; 353 #endif 354 355 enum ecore_db_rec_exec { 356 DB_REC_DRY_RUN, 357 DB_REC_REAL_DEAL, 358 DB_REC_ONCE, 359 }; 360 361 struct ecore_hw_info { 362 /* PCI personality */ 363 enum ecore_pci_personality personality; 364 #define ECORE_IS_RDMA_PERSONALITY(dev) \ 365 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 366 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 367 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 368 #define ECORE_IS_ROCE_PERSONALITY(dev) \ 369 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 370 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 371 #define ECORE_IS_IWARP_PERSONALITY(dev) \ 372 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 373 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 374 #define ECORE_IS_L2_PERSONALITY(dev) \ 375 ((dev)->hw_info.personality == ECORE_PCI_ETH || \ 376 ECORE_IS_RDMA_PERSONALITY(dev)) 377 #define ECORE_IS_FCOE_PERSONALITY(dev) \ 378 ((dev)->hw_info.personality == ECORE_PCI_FCOE) 379 #define ECORE_IS_ISCSI_PERSONALITY(dev) \ 380 ((dev)->hw_info.personality == ECORE_PCI_ISCSI) 381 382 /* Resource Allocation scheme results */ 383 u32 resc_start[ECORE_MAX_RESC]; 384 u32 resc_num[ECORE_MAX_RESC]; 385 u32 feat_num[ECORE_MAX_FEATURES]; 386 387 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 388 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 389 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 390 RESC_NUM(_p_hwfn, resc)) 391 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 392 393 /* Amount of traffic classes HW supports */ 394 u8 num_hw_tc; 395 396 /* Amount of TCs which should be active according to DCBx or upper layer driver 397 * configuration 398 */ 399 400 u8 num_active_tc; 401 402 /* The traffic class used by PF for it's offloaded protocol */ 403 u8 offload_tc; 404 405 u32 concrete_fid; 406 u16 opaque_fid; 407 u16 ovlan; 408 u32 part_num[4]; 409 410 unsigned char hw_mac_addr[ETH_ALEN]; 411 u64 node_wwn; /* For FCoE only */ 412 u64 port_wwn; /* For FCoE only */ 413 414 u16 num_iscsi_conns; 415 u16 num_fcoe_conns; 416 417 struct ecore_igu_info *p_igu_info; 418 /* Sriov */ 419 u8 max_chains_per_vf; 420 421 u32 port_mode; 422 u32 hw_mode; 423 unsigned long device_capabilities; 424 425 /* Default DCBX mode */ 426 u8 dcbx_mode; 427 428 u16 mtu; 429 }; 430 431 /* maximun size of read/write commands (HW limit) */ 432 #define DMAE_MAX_RW_SIZE 0x2000 433 434 struct ecore_dmae_info { 435 /* Mutex for synchronizing access to functions */ 436 osal_mutex_t mutex; 437 438 u8 channel; 439 440 dma_addr_t completion_word_phys_addr; 441 442 /* The memory location where the DMAE writes the completion 443 * value when an operation is finished on this context. 444 */ 445 u32 *p_completion_word; 446 447 dma_addr_t intermediate_buffer_phys_addr; 448 449 /* An intermediate buffer for DMAE operations that use virtual 450 * addresses - data is DMA'd to/from this buffer and then 451 * memcpy'd to/from the virtual address 452 */ 453 u32 *p_intermediate_buffer; 454 455 dma_addr_t dmae_cmd_phys_addr; 456 struct dmae_cmd *p_dmae_cmd; 457 }; 458 459 struct ecore_wfq_data { 460 u32 default_min_speed; /* When wfq feature is not configured */ 461 u32 min_speed; /* when feature is configured for any 1 vport */ 462 bool configured; 463 }; 464 465 struct ecore_qm_info { 466 struct init_qm_pq_params *qm_pq_params; 467 struct init_qm_vport_params *qm_vport_params; 468 struct init_qm_port_params *qm_port_params; 469 u16 start_pq; 470 u8 start_vport; 471 u16 pure_lb_pq; 472 u16 offload_pq; 473 u16 pure_ack_pq; 474 u16 ooo_pq; 475 u16 first_vf_pq; 476 u16 first_mcos_pq; 477 u16 first_rl_pq; 478 u16 num_pqs; 479 u16 num_vf_pqs; 480 u8 num_vports; 481 u8 max_phys_tcs_per_port; 482 u8 ooo_tc; 483 bool pf_rl_en; 484 bool pf_wfq_en; 485 bool vport_rl_en; 486 bool vport_wfq_en; 487 u8 pf_wfq; 488 u32 pf_rl; 489 struct ecore_wfq_data *wfq_data; 490 u8 num_pf_rls; 491 }; 492 493 struct ecore_db_recovery_info { 494 osal_list_t list; 495 osal_spinlock_t lock; 496 u32 db_recovery_counter; 497 }; 498 499 struct storm_stats { 500 u32 address; 501 u32 len; 502 }; 503 504 struct ecore_fw_data { 505 #ifdef CONFIG_ECORE_BINARY_FW 506 struct fw_ver_info *fw_ver_info; 507 #endif 508 const u8 *modes_tree_buf; 509 union init_op *init_ops; 510 const u32 *arr_data; 511 u32 init_ops_size; 512 }; 513 514 enum ecore_mf_mode_bit { 515 /* Supports PF-classification based on tag */ 516 ECORE_MF_OVLAN_CLSS, 517 518 /* Supports PF-classification based on MAC */ 519 ECORE_MF_LLH_MAC_CLSS, 520 521 /* Supports PF-classification based on protocol type */ 522 ECORE_MF_LLH_PROTO_CLSS, 523 524 /* Requires a default PF to be set */ 525 ECORE_MF_NEED_DEF_PF, 526 527 /* Allow LL2 to multicast/broadcast */ 528 ECORE_MF_LL2_NON_UNICAST, 529 530 /* Allow Cross-PF [& child VFs] Tx-switching */ 531 ECORE_MF_INTER_PF_SWITCH, 532 533 /* TODO - if we ever re-utilize any of this logic, we can rename */ 534 ECORE_MF_UFP_SPECIFIC, 535 536 ECORE_MF_DISABLE_ARFS, 537 538 /* Use vlan for steering */ 539 ECORE_MF_8021Q_TAGGING, 540 541 /* Use stag for steering */ 542 ECORE_MF_8021AD_TAGGING, 543 }; 544 545 enum ecore_ufp_mode { 546 ECORE_UFP_MODE_ETS, 547 ECORE_UFP_MODE_VNIC_BW, 548 }; 549 550 enum ecore_ufp_pri_type { 551 ECORE_UFP_PRI_OS, 552 ECORE_UFP_PRI_VNIC 553 }; 554 555 struct ecore_ufp_info { 556 enum ecore_ufp_pri_type pri_type; 557 enum ecore_ufp_mode mode; 558 u8 tc; 559 }; 560 561 enum BAR_ID { 562 BAR_ID_0, /* used for GRC */ 563 BAR_ID_1 /* Used for doorbells */ 564 }; 565 566 struct ecore_hwfn { 567 struct ecore_dev *p_dev; 568 u8 my_id; /* ID inside the PF */ 569 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 570 u8 rel_pf_id; /* Relative to engine*/ 571 u8 abs_pf_id; 572 #define ECORE_PATH_ID(_p_hwfn) \ 573 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0) 574 u8 port_id; 575 bool b_active; 576 577 u32 dp_module; 578 u8 dp_level; 579 char name[NAME_SIZE]; 580 void *dp_ctx; 581 582 bool first_on_engine; 583 bool hw_init_done; 584 585 u8 num_funcs_on_engine; 586 u8 enabled_func_idx; 587 588 /* BAR access */ 589 void OSAL_IOMEM *regview; 590 void OSAL_IOMEM *doorbells; 591 u64 db_phys_addr; 592 unsigned long db_size; 593 594 /* PTT pool */ 595 struct ecore_ptt_pool *p_ptt_pool; 596 597 /* HW info */ 598 struct ecore_hw_info hw_info; 599 600 /* rt_array (for init-tool) */ 601 struct ecore_rt_data rt_data; 602 603 /* SPQ */ 604 struct ecore_spq *p_spq; 605 606 /* EQ */ 607 struct ecore_eq *p_eq; 608 609 /* Consolidate Q*/ 610 struct ecore_consq *p_consq; 611 612 /* Slow-Path definitions */ 613 osal_dpc_t sp_dpc; 614 bool b_sp_dpc_enabled; 615 616 struct ecore_ptt *p_main_ptt; 617 struct ecore_ptt *p_dpc_ptt; 618 619 struct ecore_sb_sp_info *p_sp_sb; 620 struct ecore_sb_attn_info *p_sb_attn; 621 622 /* Protocol related */ 623 bool using_ll2; 624 struct ecore_ll2_info *p_ll2_info; 625 struct ecore_ooo_info *p_ooo_info; 626 struct ecore_iscsi_info *p_iscsi_info; 627 struct ecore_fcoe_info *p_fcoe_info; 628 struct ecore_rdma_info *p_rdma_info; 629 struct ecore_pf_params pf_params; 630 631 bool b_rdma_enabled_in_prs; 632 u32 rdma_prs_search_reg; 633 634 struct ecore_cxt_mngr *p_cxt_mngr; 635 636 /* Flag indicating whether interrupts are enabled or not*/ 637 bool b_int_enabled; 638 bool b_int_requested; 639 640 /* True if the driver requests for the link */ 641 bool b_drv_link_init; 642 643 struct ecore_vf_iov *vf_iov_info; 644 struct ecore_pf_iov *pf_iov_info; 645 struct ecore_mcp_info *mcp_info; 646 struct ecore_dcbx_info *p_dcbx_info; 647 struct ecore_ufp_info ufp_info; 648 649 struct ecore_dmae_info dmae_info; 650 651 /* QM init */ 652 struct ecore_qm_info qm_info; 653 654 #ifdef CONFIG_ECORE_ZIPPED_FW 655 /* Buffer for unzipping firmware data */ 656 void *unzip_buf; 657 #endif 658 659 struct dbg_tools_data dbg_info; 660 661 struct z_stream_s *stream; 662 663 /* PWM region specific data */ 664 u32 dpi_size; 665 u32 dpi_count; 666 u32 dpi_start_offset; /* this is used to 667 * calculate th 668 * doorbell address 669 */ 670 671 /* If one of the following is set then EDPM shouldn't be used */ 672 u8 dcbx_no_edpm; 673 u8 db_bar_no_edpm; 674 675 /* L2-related */ 676 struct ecore_l2_info *p_l2_info; 677 678 /* Mechanism for recovering from doorbell drop */ 679 struct ecore_db_recovery_info db_recovery_info; 680 681 /* @DPDK */ 682 struct ecore_ptt *p_arfs_ptt; 683 }; 684 685 enum ecore_mf_mode { 686 ECORE_MF_DEFAULT, 687 ECORE_MF_OVLAN, 688 ECORE_MF_NPAR, 689 ECORE_MF_UFP, 690 }; 691 692 /* @DPDK */ 693 struct ecore_dbg_feature { 694 u8 *dump_buf; 695 u32 buf_size; 696 u32 dumped_dwords; 697 }; 698 699 enum qed_dbg_features { 700 DBG_FEATURE_BUS, 701 DBG_FEATURE_GRC, 702 DBG_FEATURE_IDLE_CHK, 703 DBG_FEATURE_MCP_TRACE, 704 DBG_FEATURE_REG_FIFO, 705 DBG_FEATURE_PROTECTION_OVERRIDE, 706 DBG_FEATURE_NUM 707 }; 708 709 enum ecore_dev_type { 710 ECORE_DEV_TYPE_BB, 711 ECORE_DEV_TYPE_AH, 712 }; 713 714 struct ecore_dev { 715 u32 dp_module; 716 u8 dp_level; 717 char name[NAME_SIZE]; 718 void *dp_ctx; 719 720 enum ecore_dev_type type; 721 /* Translate type/revision combo into the proper conditions */ 722 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB) 723 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev)) 724 #ifndef ASIC_ONLY 725 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \ 726 (CHIP_REV_IS_TEDIBEAR(dev))) 727 #else 728 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) 729 #endif 730 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH) 731 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev) 732 733 u16 vendor_id; 734 u16 device_id; 735 #define ECORE_DEV_ID_MASK 0xff00 736 #define ECORE_DEV_ID_MASK_BB 0x1600 737 #define ECORE_DEV_ID_MASK_AH 0x8000 738 739 u16 chip_num; 740 #define CHIP_NUM_MASK 0xffff 741 #define CHIP_NUM_SHIFT 0 742 743 u8 chip_rev; 744 #define CHIP_REV_MASK 0xf 745 #define CHIP_REV_SHIFT 0 746 #ifndef ASIC_ONLY 747 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) 748 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) 749 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) 750 #define CHIP_REV_IS_EMUL(_p_dev) \ 751 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev)) 752 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) 753 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) 754 #define CHIP_REV_IS_FPGA(_p_dev) \ 755 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev)) 756 #define CHIP_REV_IS_SLOW(_p_dev) \ 757 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) 758 #define CHIP_REV_IS_A0(_p_dev) \ 759 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \ 760 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)) 761 #define CHIP_REV_IS_B0(_p_dev) \ 762 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \ 763 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)) 764 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) 765 #else 766 #define CHIP_REV_IS_A0(_p_dev) \ 767 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal) 768 #define CHIP_REV_IS_B0(_p_dev) \ 769 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal) 770 #endif 771 772 u8 chip_metal; 773 #define CHIP_METAL_MASK 0xff 774 #define CHIP_METAL_SHIFT 0 775 776 u8 chip_bond_id; 777 #define CHIP_BOND_ID_MASK 0xff 778 #define CHIP_BOND_ID_SHIFT 0 779 780 u8 num_engines; 781 u8 num_ports; 782 u8 num_ports_in_engine; 783 u8 num_funcs_in_port; 784 785 u8 path_id; 786 787 unsigned long mf_bits; 788 enum ecore_mf_mode mf_mode; 789 #define IS_MF_DEFAULT(_p_hwfn) \ 790 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) 791 #define IS_MF_SI(_p_hwfn) \ 792 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) 793 #define IS_MF_SD(_p_hwfn) \ 794 (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) 795 796 int pcie_width; 797 int pcie_speed; 798 799 /* Add MF related configuration */ 800 u8 mcp_rev; 801 u8 boot_mode; 802 803 u8 wol; 804 805 u32 int_mode; 806 enum ecore_coalescing_mode int_coalescing_mode; 807 u16 rx_coalesce_usecs; 808 u16 tx_coalesce_usecs; 809 810 /* Start Bar offset of first hwfn */ 811 void OSAL_IOMEM *regview; 812 void OSAL_IOMEM *doorbells; 813 u64 db_phys_addr; 814 unsigned long db_size; 815 816 /* PCI */ 817 u8 cache_shift; 818 819 /* Init */ 820 const struct iro *iro_arr; 821 #define IRO (p_hwfn->p_dev->iro_arr) 822 823 /* HW functions */ 824 u8 num_hwfns; 825 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 826 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1) 827 828 /* SRIOV */ 829 struct ecore_hw_sriov_info *p_iov_info; 830 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info) 831 struct ecore_tunnel_info tunnel; 832 bool b_is_vf; 833 bool b_dont_override_vf_msix; 834 835 u32 drv_type; 836 837 u32 rdma_max_sge; 838 u32 rdma_max_inline; 839 u32 rdma_max_srq_sge; 840 841 struct ecore_eth_stats *reset_stats; 842 struct ecore_fw_data *fw_data; 843 844 u32 mcp_nvm_resp; 845 846 /* Recovery */ 847 bool recov_in_prog; 848 849 /* Indicates whether should prevent attentions from being reasserted */ 850 851 bool attn_clr_en; 852 853 /* Indicates whether allowing the MFW to collect a crash dump */ 854 bool allow_mdump; 855 856 /* Indicates if the reg_fifo is checked after any register access */ 857 bool chk_reg_fifo; 858 859 #ifndef ASIC_ONLY 860 bool b_is_emul_full; 861 #endif 862 863 #ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */ 864 void *firmware; 865 u64 fw_len; 866 #endif 867 868 /* @DPDK */ 869 struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM]; 870 u8 engine_for_debug; 871 }; 872 873 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \ 874 : MAX_NUM_VFS_K2) 875 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 876 : MAX_NUM_L2_QUEUES_K2) 877 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 878 : MAX_NUM_PORTS_K2) 879 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 880 : MAX_SB_PER_PATH_K2) 881 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \ 882 : MAX_NUM_PFS_K2) 883 884 #define CRC8_TABLE_SIZE 256 885 886 /** 887 * @brief ecore_concrete_to_sw_fid - get the sw function id from 888 * the concrete value. 889 * 890 * @param concrete_fid 891 * 892 * @return OSAL_INLINE u8 893 */ 894 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid) 895 { 896 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 897 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 898 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID); 899 u8 sw_fid; 900 901 if (vf_valid) 902 sw_fid = vfid + MAX_NUM_PFS; 903 else 904 sw_fid = pfid; 905 906 return sw_fid; 907 } 908 909 #define PKT_LB_TC 9 910 #define MAX_NUM_VOQS_E4 20 911 912 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate); 913 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 914 struct ecore_ptt *p_ptt, 915 u32 min_pf_rate); 916 917 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw); 918 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw); 919 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); 920 int ecore_device_num_engines(struct ecore_dev *p_dev); 921 int ecore_device_num_ports(struct ecore_dev *p_dev); 922 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb, 923 u8 *mac); 924 925 /* Flags for indication of required queues */ 926 #define PQ_FLAGS_RLS (1 << 0) 927 #define PQ_FLAGS_MCOS (1 << 1) 928 #define PQ_FLAGS_LB (1 << 2) 929 #define PQ_FLAGS_OOO (1 << 3) 930 #define PQ_FLAGS_ACK (1 << 4) 931 #define PQ_FLAGS_OFLD (1 << 5) 932 #define PQ_FLAGS_VFS (1 << 6) 933 934 /* physical queue index for cm context intialization */ 935 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags); 936 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc); 937 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf); 938 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid); 939 940 const char *ecore_hw_get_resc_name(enum ecore_resources res_id); 941 942 /* doorbell recovery mechanism */ 943 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn); 944 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, 945 enum ecore_db_rec_exec); 946 947 /* amount of resources used in qm init */ 948 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn); 949 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn); 950 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn); 951 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn); 952 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn); 953 954 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) 955 956 #endif /* __ECORE_H */ 957