1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2016 - 2018 Cavium Inc. 3 * All rights reserved. 4 * www.cavium.com 5 */ 6 7 #ifndef __COMMON_HSI__ 8 #define __COMMON_HSI__ 9 /********************************/ 10 /* PROTOCOL COMMON FW CONSTANTS */ 11 /********************************/ 12 13 /* Temporarily here should be added to HSI automatically by resource allocation 14 * tool. 15 */ 16 #define T_TEST_AGG_INT_TEMP 6 17 #define M_TEST_AGG_INT_TEMP 8 18 #define U_TEST_AGG_INT_TEMP 6 19 #define X_TEST_AGG_INT_TEMP 14 20 #define Y_TEST_AGG_INT_TEMP 4 21 #define P_TEST_AGG_INT_TEMP 4 22 23 #define X_FINAL_CLEANUP_AGG_INT 1 24 25 #define EVENT_RING_PAGE_SIZE_BYTES 4096 26 27 #define NUM_OF_GLOBAL_QUEUES 128 28 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 29 30 #define ISCSI_CDU_TASK_SEG_TYPE 0 31 #define FCOE_CDU_TASK_SEG_TYPE 0 32 #define RDMA_CDU_TASK_SEG_TYPE 1 33 34 #define FW_ASSERT_GENERAL_ATTN_IDX 32 35 36 #define MAX_PINNED_CCFC 32 37 38 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 39 40 /* Queue Zone sizes in bytes */ 41 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ 42 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX 43 *producer of VFs in backward compatibility 44 *mode. 45 */ 46 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ 47 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 48 #define YSTORM_QZONE_SIZE 0 49 #define PSTORM_QZONE_SIZE 0 50 51 /*Log of mstorm default VF zone size.*/ 52 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 53 /*Maximum number of RX queues that can be allocated to VF by default*/ 54 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 55 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone 56 * size. Up to 96 VF supported in this mode 57 */ 58 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 59 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. 60 * Up to 48 VF supported in this mode 61 */ 62 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 63 64 65 /********************************/ 66 /* CORE (LIGHT L2) FW CONSTANTS */ 67 /********************************/ 68 69 #define CORE_LL2_MAX_RAMROD_PER_CON 8 70 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 71 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 72 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 73 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 74 75 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 76 77 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 78 79 /* 80 * Usually LL2 queues are opened in pairs TX-RX. 81 * There is a hard restriction on number of RX queues (limited by Tstorm RAM) 82 * and TX counters (Pstorm RAM). 83 * Number of TX queues is almost unlimited. 84 * The constants are different so as to allow asymmetric LL2 connections 85 */ 86 87 #define MAX_NUM_LL2_RX_QUEUES 48 88 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 89 90 91 /****************************************************************************/ 92 /* Include firmware version number only- do not add constants here to avoid */ 93 /* redundunt compilations */ 94 /****************************************************************************/ 95 96 97 #define FW_MAJOR_VERSION 8 98 #define FW_MINOR_VERSION 37 99 #define FW_REVISION_VERSION 7 100 #define FW_ENGINEERING_VERSION 0 101 102 /***********************/ 103 /* COMMON HW CONSTANTS */ 104 /***********************/ 105 106 /* PCI functions */ 107 #define MAX_NUM_PORTS_BB (2) 108 #define MAX_NUM_PORTS_K2 (4) 109 #define MAX_NUM_PORTS_E5 (4) 110 #define MAX_NUM_PORTS (MAX_NUM_PORTS_E5) 111 112 #define MAX_NUM_PFS_BB (8) 113 #define MAX_NUM_PFS_K2 (16) 114 #define MAX_NUM_PFS_E5 (16) 115 #define MAX_NUM_PFS (MAX_NUM_PFS_E5) 116 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 117 118 #define MAX_NUM_VFS_BB (120) 119 #define MAX_NUM_VFS_K2 (192) 120 #define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2) 121 #define MAX_NUM_VFS_E5 (240) 122 #define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5) 123 124 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 125 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 126 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4) 127 128 /* in both BB and K2, the VF number starts from 16. so for arrays containing all 129 * possible PFs and VFs - we need a constant for this size 130 */ 131 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 132 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 133 #define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4) 134 #define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5) 135 #define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5) 136 137 #define MAX_NUM_VPORTS_K2 (208) 138 #define MAX_NUM_VPORTS_BB (160) 139 #define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2) 140 #define MAX_NUM_VPORTS_E5 (256) 141 #define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5) 142 143 #define MAX_NUM_L2_QUEUES_BB (256) 144 #define MAX_NUM_L2_QUEUES_K2 (320) 145 #define MAX_NUM_L2_QUEUES_E5 (320) /* TODO_E5_VITALY - fix to 512 */ 146 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_E5) 147 148 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 149 #define NUM_PHYS_TCS_4PORT_K2 4 150 #define NUM_PHYS_TCS_4PORT_TX_E5 6 151 #define NUM_PHYS_TCS_4PORT_RX_E5 4 152 #define NUM_OF_PHYS_TCS 8 153 #define PURE_LB_TC NUM_OF_PHYS_TCS 154 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 155 #define NUM_TCS_4PORT_TX_E5 (NUM_PHYS_TCS_4PORT_TX_E5 + 1) 156 #define NUM_TCS_4PORT_RX_E5 (NUM_PHYS_TCS_4PORT_RX_E5 + 1) 157 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 158 159 /* CIDs */ 160 #define NUM_OF_CONNECTION_TYPES_E4 (8) 161 #define NUM_OF_CONNECTION_TYPES_E5 (16) 162 #define NUM_OF_TASK_TYPES (8) 163 #define NUM_OF_LCIDS (320) 164 #define NUM_OF_LTIDS (320) 165 166 /* Global PXP windows (GTT) */ 167 #define NUM_OF_GTT 19 168 #define GTT_DWORD_SIZE_BITS 10 169 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 170 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 171 172 /* Tools Version */ 173 #define TOOLS_VERSION 10 174 /*****************/ 175 /* CDU CONSTANTS */ 176 /*****************/ 177 178 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 179 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 180 181 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 182 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 183 184 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 185 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 186 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 187 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 188 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 189 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 190 191 192 /*****************/ 193 /* DQ CONSTANTS */ 194 /*****************/ 195 196 /* DEMS */ 197 #define DQ_DEMS_LEGACY 0 198 #define DQ_DEMS_TOE_MORE_TO_SEND 3 199 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 200 #define DQ_DEMS_ROCE_CQ_CONS 7 201 202 /* XCM agg val selection (HW) */ 203 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 204 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 205 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 206 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 207 #define DQ_XCM_AGG_VAL_SEL_REG3 4 208 #define DQ_XCM_AGG_VAL_SEL_REG4 5 209 #define DQ_XCM_AGG_VAL_SEL_REG5 6 210 #define DQ_XCM_AGG_VAL_SEL_REG6 7 211 212 /* XCM agg val selection (FW) */ 213 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \ 214 DQ_XCM_AGG_VAL_SEL_WORD2 215 #define DQ_XCM_ETH_TX_BD_CONS_CMD \ 216 DQ_XCM_AGG_VAL_SEL_WORD3 217 #define DQ_XCM_CORE_TX_BD_CONS_CMD \ 218 DQ_XCM_AGG_VAL_SEL_WORD3 219 #define DQ_XCM_ETH_TX_BD_PROD_CMD \ 220 DQ_XCM_AGG_VAL_SEL_WORD4 221 #define DQ_XCM_CORE_TX_BD_PROD_CMD \ 222 DQ_XCM_AGG_VAL_SEL_WORD4 223 #define DQ_XCM_CORE_SPQ_PROD_CMD \ 224 DQ_XCM_AGG_VAL_SEL_WORD4 225 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 226 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 227 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 228 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 229 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 230 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 231 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 232 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 233 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 234 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 235 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 236 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 237 238 /* UCM agg val selection (HW) */ 239 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 240 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 241 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 242 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 243 #define DQ_UCM_AGG_VAL_SEL_REG0 4 244 #define DQ_UCM_AGG_VAL_SEL_REG1 5 245 #define DQ_UCM_AGG_VAL_SEL_REG2 6 246 #define DQ_UCM_AGG_VAL_SEL_REG3 7 247 248 /* UCM agg val selection (FW) */ 249 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 250 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 251 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 252 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 253 254 /* TCM agg val selection (HW) */ 255 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 256 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 257 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 258 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 259 #define DQ_TCM_AGG_VAL_SEL_REG1 4 260 #define DQ_TCM_AGG_VAL_SEL_REG2 5 261 #define DQ_TCM_AGG_VAL_SEL_REG6 6 262 #define DQ_TCM_AGG_VAL_SEL_REG9 7 263 264 /* TCM agg val selection (FW) */ 265 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 266 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 267 268 /* XCM agg counter flag selection (HW) */ 269 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 270 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 271 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 272 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 273 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 274 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 275 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 276 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 277 278 /* XCM agg counter flag selection (FW) */ 279 #define DQ_XCM_ETH_DQ_CF_CMD (1 << \ 280 DQ_XCM_AGG_FLG_SHIFT_CF18) 281 #define DQ_XCM_CORE_DQ_CF_CMD (1 << \ 282 DQ_XCM_AGG_FLG_SHIFT_CF18) 283 #define DQ_XCM_ETH_TERMINATE_CMD (1 << \ 284 DQ_XCM_AGG_FLG_SHIFT_CF19) 285 #define DQ_XCM_CORE_TERMINATE_CMD (1 << \ 286 DQ_XCM_AGG_FLG_SHIFT_CF19) 287 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \ 288 DQ_XCM_AGG_FLG_SHIFT_CF22) 289 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \ 290 DQ_XCM_AGG_FLG_SHIFT_CF22) 291 #define DQ_XCM_ETH_TPH_EN_CMD (1 << \ 292 DQ_XCM_AGG_FLG_SHIFT_CF23) 293 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 294 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 295 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 296 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 297 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 298 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 299 300 /* UCM agg counter flag selection (HW) */ 301 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 302 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 303 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 304 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 305 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 306 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 307 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 308 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 309 310 /* UCM agg counter flag selection (FW) */ 311 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 312 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 313 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 314 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 315 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 316 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 317 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 318 319 /* TCM agg counter flag selection (HW) */ 320 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 321 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 322 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 323 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 324 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 325 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 326 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 327 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 328 329 /* TCM agg counter flag selection (FW) */ 330 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 331 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 332 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 333 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 334 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 335 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 336 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 337 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 338 339 /* PWM address mapping */ 340 #define DQ_PWM_OFFSET_DPM_BASE 0x0 341 #define DQ_PWM_OFFSET_DPM_END 0x27 342 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 343 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 344 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 345 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 346 #define DQ_PWM_OFFSET_UCM16_4 0x50 347 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 348 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 349 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 350 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 351 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 352 353 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 354 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 355 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 356 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 357 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 358 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 359 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 360 361 #define DQ_REGION_SHIFT (12) 362 363 /* DPM */ 364 #define DQ_DPM_WQE_BUFF_SIZE (320) 365 366 /* Conn type ranges */ 367 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 368 369 /*****************/ 370 /* QM CONSTANTS */ 371 /*****************/ 372 373 /* number of TX queues in the QM */ 374 #define MAX_QM_TX_QUEUES_K2 512 375 #define MAX_QM_TX_QUEUES_BB 448 376 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 377 378 /* number of Other queues in the QM */ 379 #define MAX_QM_OTHER_QUEUES_BB 64 380 #define MAX_QM_OTHER_QUEUES_K2 128 381 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 382 383 /* number of queues in a PF queue group */ 384 #define QM_PF_QUEUE_GROUP_SIZE 8 385 386 /* the size of a single queue element in bytes */ 387 #define QM_PQ_ELEMENT_SIZE 4 388 389 /* base number of Tx PQs in the CM PQ representation. 390 * should be used when storing PQ IDs in CM PQ registers and context 391 */ 392 #define CM_TX_PQ_BASE 0x200 393 394 /* number of global Vport/QCN rate limiters */ 395 #define MAX_QM_GLOBAL_RLS 256 396 397 /* QM registers data */ 398 #define QM_LINE_CRD_REG_WIDTH 16 399 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 400 #define QM_BYTE_CRD_REG_WIDTH 24 401 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 402 #define QM_WFQ_CRD_REG_WIDTH 32 403 #define QM_WFQ_CRD_REG_SIGN_BIT (1U << (QM_WFQ_CRD_REG_WIDTH - 1)) 404 #define QM_RL_CRD_REG_WIDTH 32 405 #define QM_RL_CRD_REG_SIGN_BIT (1U << (QM_RL_CRD_REG_WIDTH - 1)) 406 407 /*****************/ 408 /* CAU CONSTANTS */ 409 /*****************/ 410 411 #define CAU_FSM_ETH_RX 0 412 #define CAU_FSM_ETH_TX 1 413 414 /* Number of Protocol Indices per Status Block */ 415 #define PIS_PER_SB_E4 12 416 #define PIS_PER_SB_E5 8 417 #define MAX_PIS_PER_SB_E4 OSAL_MAX_T(PIS_PER_SB_E4, PIS_PER_SB_E5) 418 419 /* fsm is stopped or not valid for this sb */ 420 #define CAU_HC_STOPPED_STATE 3 421 /* fsm is working without interrupt coalescing for this sb*/ 422 #define CAU_HC_DISABLE_STATE 4 423 /* fsm is working with interrupt coalescing for this sb*/ 424 #define CAU_HC_ENABLE_STATE 0 425 426 427 /*****************/ 428 /* IGU CONSTANTS */ 429 /*****************/ 430 431 #define MAX_SB_PER_PATH_K2 (368) 432 #define MAX_SB_PER_PATH_BB (288) 433 #define MAX_SB_PER_PATH_E5 (512) 434 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_E5 435 436 #define MAX_SB_PER_PF_MIMD 129 437 #define MAX_SB_PER_PF_SIMD 64 438 #define MAX_SB_PER_VF 64 439 440 /* Memory addresses on the BAR for the IGU Sub Block */ 441 #define IGU_MEM_BASE 0x0000 442 443 #define IGU_MEM_MSIX_BASE 0x0000 444 #define IGU_MEM_MSIX_UPPER 0x0101 445 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 446 447 #define IGU_MEM_PBA_MSIX_BASE 0x0200 448 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 449 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 450 451 #define IGU_CMD_INT_ACK_BASE 0x0400 452 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \ 453 MAX_TOT_SB_PER_PATH - \ 454 1) 455 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 456 457 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 458 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 459 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 460 461 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 462 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 463 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 464 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 465 466 #define IGU_CMD_PROD_UPD_BASE 0x0600 467 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + \ 468 MAX_TOT_SB_PER_PATH - \ 469 1) 470 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 471 472 /*****************/ 473 /* PXP CONSTANTS */ 474 /*****************/ 475 476 /* Bars for Blocks */ 477 #define PXP_BAR_GRC 0 478 #define PXP_BAR_TSDM 0 479 #define PXP_BAR_USDM 0 480 #define PXP_BAR_XSDM 0 481 #define PXP_BAR_MSDM 0 482 #define PXP_BAR_YSDM 0 483 #define PXP_BAR_PSDM 0 484 #define PXP_BAR_IGU 0 485 #define PXP_BAR_DQ 1 486 487 /* PTT and GTT */ 488 #define PXP_PER_PF_ENTRY_SIZE 8 489 #define PXP_NUM_GLOBAL_WINDOWS 243 490 #define PXP_GLOBAL_ENTRY_SIZE 4 491 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 492 #define PXP_PF_WINDOW_ADMIN_START 0 493 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 494 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \ 495 PXP_PF_WINDOW_ADMIN_LENGTH - 1) 496 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 497 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \ 498 PXP_PER_PF_ENTRY_SIZE) 499 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \ 500 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 501 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 502 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \ 503 PXP_GLOBAL_ENTRY_SIZE) 504 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \ 505 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \ 506 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 507 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 508 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 509 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 510 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 511 512 #define PXP_NUM_PF_WINDOWS 12 513 514 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 515 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 516 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 517 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \ 518 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \ 519 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 520 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \ 521 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \ 522 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 523 524 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \ 525 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 526 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 527 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 528 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \ 529 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \ 530 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 531 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \ 532 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \ 533 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 534 535 /* PF BAR */ 536 #define PXP_BAR0_START_GRC 0x0000 537 #define PXP_BAR0_GRC_LENGTH 0x1C00000 538 #define PXP_BAR0_END_GRC \ 539 (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 540 541 #define PXP_BAR0_START_IGU 0x1C00000 542 #define PXP_BAR0_IGU_LENGTH 0x10000 543 #define PXP_BAR0_END_IGU \ 544 (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 545 546 #define PXP_BAR0_START_TSDM 0x1C80000 547 #define PXP_BAR0_SDM_LENGTH 0x40000 548 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 549 #define PXP_BAR0_END_TSDM \ 550 (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 551 552 #define PXP_BAR0_START_MSDM 0x1D00000 553 #define PXP_BAR0_END_MSDM \ 554 (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 555 556 #define PXP_BAR0_START_USDM 0x1D80000 557 #define PXP_BAR0_END_USDM \ 558 (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 559 560 #define PXP_BAR0_START_XSDM 0x1E00000 561 #define PXP_BAR0_END_XSDM \ 562 (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 563 564 #define PXP_BAR0_START_YSDM 0x1E80000 565 #define PXP_BAR0_END_YSDM \ 566 (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 567 568 #define PXP_BAR0_START_PSDM 0x1F00000 569 #define PXP_BAR0_END_PSDM \ 570 (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 571 572 #define PXP_BAR0_FIRST_INVALID_ADDRESS \ 573 (PXP_BAR0_END_PSDM + 1) 574 575 /* VF BAR */ 576 #define PXP_VF_BAR0 0 577 578 #define PXP_VF_BAR0_START_IGU 0 579 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 580 #define PXP_VF_BAR0_END_IGU \ 581 (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 582 583 #define PXP_VF_BAR0_START_DQ 0x3000 584 #define PXP_VF_BAR0_DQ_LENGTH 0x200 585 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 586 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS \ 587 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 588 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS \ 589 (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 590 #define PXP_VF_BAR0_END_DQ \ 591 (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 592 593 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 594 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 595 #define PXP_VF_BAR0_END_TSDM_ZONE_B \ 596 (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 597 598 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 599 #define PXP_VF_BAR0_END_MSDM_ZONE_B \ 600 (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 601 602 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 603 #define PXP_VF_BAR0_END_USDM_ZONE_B \ 604 (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 605 606 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 607 #define PXP_VF_BAR0_END_XSDM_ZONE_B \ 608 (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 609 610 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 611 #define PXP_VF_BAR0_END_YSDM_ZONE_B \ 612 (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 613 614 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 615 #define PXP_VF_BAR0_END_PSDM_ZONE_B \ 616 (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 617 618 #define PXP_VF_BAR0_START_GRC 0x3E00 619 #define PXP_VF_BAR0_GRC_LENGTH 0x200 620 #define PXP_VF_BAR0_END_GRC \ 621 (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 622 623 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 624 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 625 626 #define PXP_VF_BAR0_START_IGU2 0x10000 627 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000 628 #define PXP_VF_BAR0_END_IGU2 \ 629 (PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1) 630 631 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 632 633 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 634 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 635 636 // ILT Records 637 #define PXP_NUM_ILT_RECORDS_BB 7600 638 #define PXP_NUM_ILT_RECORDS_K2 11000 639 #define MAX_NUM_ILT_RECORDS \ 640 OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2) 641 642 #define PXP_NUM_ILT_RECORDS_E5 13664 643 644 645 // Host Interface 646 #define PXP_QUEUES_ZONE_MAX_NUM_E4 320 647 #define PXP_QUEUES_ZONE_MAX_NUM_E5 512 648 649 650 /*****************/ 651 /* PRM CONSTANTS */ 652 /*****************/ 653 #define PRM_DMA_PAD_BYTES_NUM 2 654 /*****************/ 655 /* SDMs CONSTANTS */ 656 /*****************/ 657 658 659 #define SDM_OP_GEN_TRIG_NONE 0 660 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 661 #define SDM_OP_GEN_TRIG_AGG_INT 2 662 #define SDM_OP_GEN_TRIG_LOADER 4 663 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 664 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 665 666 /***********************************************************/ 667 /* Completion types */ 668 /***********************************************************/ 669 670 #define SDM_COMP_TYPE_NONE 0 671 #define SDM_COMP_TYPE_WAKE_THREAD 1 672 #define SDM_COMP_TYPE_AGG_INT 2 673 /* Send direct message to local CM and/or remote CMs. Destinations are defined 674 * by vector in CompParams. 675 */ 676 #define SDM_COMP_TYPE_CM 3 677 #define SDM_COMP_TYPE_LOADER 4 678 /* Send direct message to PXP (like "internal write" command) to write to remote 679 * Storm RAM via remote SDM 680 */ 681 #define SDM_COMP_TYPE_PXP 5 682 /* Indicate error per thread */ 683 #define SDM_COMP_TYPE_INDICATE_ERROR 6 684 #define SDM_COMP_TYPE_RELEASE_THREAD 7 685 /* Write to local RAM as a completion */ 686 #define SDM_COMP_TYPE_RAM 8 687 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 /* Applicable only for E4 */ 688 689 690 /******************/ 691 /* PBF CONSTANTS */ 692 /******************/ 693 694 /* Number of PBF command queue lines. Each line is 32B. */ 695 #define PBF_MAX_CMD_LINES_E4 3328 696 #define PBF_MAX_CMD_LINES_E5 5280 697 698 /* Number of BTB blocks. Each block is 256B. */ 699 #define BTB_MAX_BLOCKS 1440 700 701 /*****************/ 702 /* PRS CONSTANTS */ 703 /*****************/ 704 705 #define PRS_GFT_CAM_LINES_NO_MATCH 31 706 707 /* 708 * Interrupt coalescing TimeSet 709 */ 710 struct coalescing_timeset { 711 u8 value; 712 /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 713 #define COALESCING_TIMESET_TIMESET_MASK 0x7F 714 #define COALESCING_TIMESET_TIMESET_SHIFT 0 715 /* Only if this flag is set, timeset will take effect */ 716 #define COALESCING_TIMESET_VALID_MASK 0x1 717 #define COALESCING_TIMESET_VALID_SHIFT 7 718 }; 719 720 struct common_queue_zone { 721 __le16 ring_drv_data_consumer; 722 __le16 reserved; 723 }; 724 725 /* 726 * ETH Rx producers data 727 */ 728 struct eth_rx_prod_data { 729 __le16 bd_prod /* BD producer. */; 730 __le16 cqe_prod /* CQE producer. */; 731 }; 732 733 734 struct tcp_ulp_connect_done_params { 735 __le16 mss; 736 u8 snd_wnd_scale; 737 u8 flags; 738 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1 739 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0 740 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F 741 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1 742 }; 743 744 struct iscsi_connect_done_results { 745 __le16 icid /* Context ID of the connection */; 746 __le16 conn_id /* Driver connection ID */; 747 /* decided tcp params after connect done */ 748 struct tcp_ulp_connect_done_params params; 749 }; 750 751 752 struct iscsi_eqe_data { 753 __le16 icid /* Context ID of the connection */; 754 __le16 conn_id /* Driver connection ID */; 755 __le16 reserved; 756 /* error code - relevant only if the opcode indicates its an error */ 757 u8 error_code; 758 u8 error_pdu_opcode_reserved; 759 /* The processed PDUs opcode on which happened the error - updated for specific 760 * error codes, by default=0xFF 761 */ 762 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F 763 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 764 /* Indication for driver is the error_pdu_opcode field has valid value */ 765 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 766 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 767 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 768 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 769 }; 770 771 772 /* 773 * Multi function mode 774 */ 775 enum mf_mode { 776 ERROR_MODE /* Unsupported mode */, 777 MF_OVLAN /* Multi function based on outer VLAN */, 778 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 779 MAX_MF_MODE 780 }; 781 782 /* Per-protocol connection types */ 783 enum protocol_type { 784 PROTOCOLID_ISCSI /* iSCSI */, 785 PROTOCOLID_FCOE /* FCoE */, 786 PROTOCOLID_ROCE /* RoCE */, 787 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 788 PROTOCOLID_ETH /* Ethernet */, 789 PROTOCOLID_IWARP /* iWARP */, 790 PROTOCOLID_TOE /* TOE */, 791 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 792 PROTOCOLID_COMMON /* ProtocolCommon */, 793 PROTOCOLID_TCP /* TCP */, 794 MAX_PROTOCOL_TYPE 795 }; 796 797 798 struct regpair { 799 __le32 lo /* low word for reg-pair */; 800 __le32 hi /* high word for reg-pair */; 801 }; 802 803 804 805 /* 806 * Ustorm Queue Zone 807 */ 808 struct ustorm_eth_queue_zone { 809 /* Rx interrupt coalescing TimeSet */ 810 struct coalescing_timeset int_coalescing_timeset; 811 u8 reserved[3]; 812 }; 813 814 815 struct ustorm_queue_zone { 816 struct ustorm_eth_queue_zone eth; 817 struct common_queue_zone common; 818 }; 819 820 /* status block structure */ 821 struct cau_pi_entry { 822 __le32 prod; 823 /* A per protocol indexPROD value. */ 824 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF 825 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 826 /* This value determines the TimeSet that the PI is associated with */ 827 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F 828 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 829 /* Select the FSM within the SB */ 830 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 831 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 832 /* Select the FSM within the SB */ 833 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF 834 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 835 }; 836 837 /* status block structure */ 838 struct cau_sb_entry { 839 __le32 data; 840 /* The SB PROD index which is sent to the IGU. */ 841 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF 842 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 843 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 844 #define CAU_SB_ENTRY_STATE0_SHIFT 24 845 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 846 #define CAU_SB_ENTRY_STATE1_SHIFT 28 847 __le32 params; 848 /* Indicates the RX TimeSet that this SB is associated with. */ 849 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F 850 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 851 /* Indicates the TX TimeSet that this SB is associated with. */ 852 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F 853 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 854 /* This value will determine the RX FSM timer resolution in ticks */ 855 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 856 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 857 /* This value will determine the TX FSM timer resolution in ticks */ 858 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 859 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 860 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 861 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 862 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 863 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 864 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 865 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 866 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise 867 * the STAG will be equal to all ones. 868 */ 869 #define CAU_SB_ENTRY_TPH_MASK 0x1 870 #define CAU_SB_ENTRY_TPH_SHIFT 31 871 }; 872 873 874 /* 875 * Igu cleanup bit values to distinguish between clean or producer consumer 876 * update. 877 */ 878 enum command_type_bit { 879 IGU_COMMAND_TYPE_NOP = 0, 880 IGU_COMMAND_TYPE_SET = 1, 881 MAX_COMMAND_TYPE_BIT 882 }; 883 884 885 /* core doorbell data */ 886 struct core_db_data { 887 u8 params; 888 /* destination of doorbell (use enum db_dest) */ 889 #define CORE_DB_DATA_DEST_MASK 0x3 890 #define CORE_DB_DATA_DEST_SHIFT 0 891 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 892 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 893 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 894 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 895 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 896 #define CORE_DB_DATA_RESERVED_MASK 0x1 897 #define CORE_DB_DATA_RESERVED_SHIFT 5 898 /* aggregative value selection */ 899 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 900 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 901 /* bit for every DQ counter flags in CM context that DQ can increment */ 902 u8 agg_flags; 903 __le16 spq_prod; 904 }; 905 906 /* Enum of doorbell aggregative command selection */ 907 enum db_agg_cmd_sel { 908 DB_AGG_CMD_NOP /* No operation */, 909 DB_AGG_CMD_SET /* Set the value */, 910 DB_AGG_CMD_ADD /* Add the value */, 911 DB_AGG_CMD_MAX /* Set max of current and new value */, 912 MAX_DB_AGG_CMD_SEL 913 }; 914 915 /* Enum of doorbell destination */ 916 enum db_dest { 917 DB_DEST_XCM /* TX doorbell to XCM */, 918 DB_DEST_UCM /* RX doorbell to UCM */, 919 DB_DEST_TCM /* RX doorbell to TCM */, 920 DB_NUM_DESTINATIONS, 921 MAX_DB_DEST 922 }; 923 924 925 /* 926 * Enum of doorbell DPM types 927 */ 928 enum db_dpm_type { 929 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 930 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 931 /* L2 DPM inline- to PBF, with packet data on doorbell */ 932 DPM_L2_INLINE, 933 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 934 MAX_DB_DPM_TYPE 935 }; 936 937 /* 938 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM 939 * burst 940 */ 941 struct db_l2_dpm_data { 942 __le16 icid /* internal CID */; 943 __le16 bd_prod /* bd producer value to update */; 944 __le32 params; 945 /* Size in QWORD-s of the DPM burst */ 946 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F 947 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 948 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) 949 */ 950 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 951 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 952 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 953 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 954 /* size of the packet to be transmitted in bytes */ 955 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF 956 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 957 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 958 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 959 /* In DPM_L2_BD mode: the number of SGE-s */ 960 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 961 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 962 /* Flag indicating whether to enable GFS search */ 963 #define DB_L2_DPM_DATA_RESERVED1_MASK 0x1 964 #define DB_L2_DPM_DATA_RESERVED1_SHIFT 31 965 }; 966 967 /* 968 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 969 */ 970 struct db_l2_dpm_sge { 971 struct regpair addr /* Single continuous buffer */; 972 __le16 nbytes /* Number of bytes in this BD. */; 973 __le16 bitfields; 974 /* The TPH STAG index value */ 975 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF 976 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 977 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 978 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 979 /* Indicate if ST hint is requested or not */ 980 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 981 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 982 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 983 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 984 __le32 reserved2; 985 }; 986 987 /* Structure for doorbell address, in legacy mode */ 988 struct db_legacy_addr { 989 __le32 addr; 990 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 991 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 992 /* doorbell extraction mode specifier- 0 if not used */ 993 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 994 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 995 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 996 #define DB_LEGACY_ADDR_ICID_SHIFT 5 997 }; 998 999 /* 1000 * Structure for doorbell address, in PWM mode 1001 */ 1002 struct db_pwm_addr { 1003 __le32 addr; 1004 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 1005 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 1006 /* Offset in PWM address space */ 1007 #define DB_PWM_ADDR_OFFSET_MASK 0x7F 1008 #define DB_PWM_ADDR_OFFSET_SHIFT 3 1009 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 1010 #define DB_PWM_ADDR_WID_SHIFT 10 1011 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 1012 #define DB_PWM_ADDR_DPI_SHIFT 12 1013 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 1014 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 1015 }; 1016 1017 /* 1018 * Parameters to RDMA firmware, passed in EDPM doorbell 1019 */ 1020 struct db_rdma_dpm_params { 1021 __le32 params; 1022 /* Size in QWORD-s of the DPM burst */ 1023 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F 1024 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 1025 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 1026 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 1027 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 1028 /* opcode for RDMA operation */ 1029 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF 1030 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 1031 /* the size of the WQE payload in bytes */ 1032 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF 1033 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 1034 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 1035 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 1036 /* RoCE ack request (will be set 1) */ 1037 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1 1038 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT 28 1039 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 1040 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 1041 /* RoCE completion flag for FW use */ 1042 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 1043 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 30 1044 /* Connection type is iWARP */ 1045 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 1046 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 1047 }; 1048 1049 /* 1050 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a 1051 * DPM burst 1052 */ 1053 struct db_rdma_dpm_data { 1054 __le16 icid /* internal CID */; 1055 __le16 prod_val /* aggregated value to update */; 1056 /* parameters passed to RDMA firmware */ 1057 struct db_rdma_dpm_params params; 1058 }; 1059 1060 /* Igu interrupt command */ 1061 enum igu_int_cmd { 1062 IGU_INT_ENABLE = 0, 1063 IGU_INT_DISABLE = 1, 1064 IGU_INT_NOP = 2, 1065 IGU_INT_NOP2 = 3, 1066 MAX_IGU_INT_CMD 1067 }; 1068 1069 /* IGU producer or consumer update command */ 1070 struct igu_prod_cons_update { 1071 __le32 sb_id_and_flags; 1072 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1073 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1074 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1075 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1076 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1077 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 1078 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1079 /* (use enum igu_seg_access) */ 1080 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 1081 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1082 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1083 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1084 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1085 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1086 /* must always be set cleared (use enum command_type_bit) */ 1087 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 1088 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1089 __le32 reserved1; 1090 }; 1091 1092 /* Igu segments access for default status block only */ 1093 enum igu_seg_access { 1094 IGU_SEG_ACCESS_REG = 0, 1095 IGU_SEG_ACCESS_ATTN = 1, 1096 MAX_IGU_SEG_ACCESS 1097 }; 1098 1099 1100 /* 1101 * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type: 1102 * 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according 1103 * to the last-ethertype) 1104 */ 1105 enum l3_type { 1106 e_l3_type_unknown, 1107 e_l3_type_ipv4, 1108 e_l3_type_ipv6, 1109 MAX_L3_TYPE 1110 }; 1111 1112 1113 /* 1114 * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol 1115 * 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the 1116 * first fragment, the protocol-type should be set to none. 1117 */ 1118 enum l4_protocol { 1119 e_l4_protocol_none, 1120 e_l4_protocol_tcp, 1121 e_l4_protocol_udp, 1122 MAX_L4_PROTOCOL 1123 }; 1124 1125 1126 /* 1127 * Parsing and error flags field. 1128 */ 1129 struct parsing_and_err_flags { 1130 __le16 flags; 1131 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled 1132 * according to the last-ethertype) (use enum l3_type) 1133 */ 1134 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 1135 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1136 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and 1137 * its not the first fragment, the protocol-type should be set to none. 1138 * (use enum l4_protocol) 1139 */ 1140 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 1141 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1142 /* Set if the packet is IPv4 fragment. */ 1143 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 1144 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1145 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */ 1146 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 1147 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1148 /* Set if L4 checksum was calculated. */ 1149 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 1150 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1151 /* Set for PTP packet. */ 1152 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 1153 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1154 /* Set if PTP timestamp recorded. */ 1155 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 1156 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1157 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 1158 * ver mismatch 1159 */ 1160 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 1161 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1162 /* Set if L4 checksum validation failed. Valid only if L4 checksum was 1163 * calculated. 1164 */ 1165 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 1166 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1167 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1168 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 1169 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1170 /* Set if VLAN tag exists in tunnel header. */ 1171 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 1172 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1173 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or 1174 * tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch 1175 */ 1176 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 1177 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1178 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */ 1179 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 1180 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1181 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum 1182 * was calculated. 1183 */ 1184 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 1185 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1186 }; 1187 1188 1189 /* 1190 * Parsing error flags bitmap. 1191 */ 1192 struct parsing_err_flags { 1193 __le16 flags; 1194 /* MAC error indication */ 1195 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 1196 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1197 /* truncation error indication */ 1198 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 1199 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1200 /* packet too small indication */ 1201 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 1202 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1203 /* Header Missing Tag */ 1204 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 1205 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1206 /* from frame cracker output */ 1207 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 1208 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1209 /* from frame cracker output */ 1210 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 1211 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1212 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len 1213 * indicates number that is bigger than real packet length 3. tunneling: 1214 * total-ip-length of the outer header points to offset that is smaller than 1215 * the one pointed to by the total-ip-len of the inner hdr. 1216 */ 1217 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 1218 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1219 /* from frame cracker output */ 1220 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 1221 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1222 /* from frame cracker output. for either TCP or UDP */ 1223 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 1224 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1225 /* from frame cracker output */ 1226 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 1227 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1228 /* cksm calculated and value isn't 0xffff or L4-cksm-wasnt-calculated for any 1229 * reason, like: udp/ipv4 checksum is 0 etc. 1230 */ 1231 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 1232 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1233 /* from frame cracker output */ 1234 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 1235 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1236 /* from frame cracker output */ 1237 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 1238 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1239 /* set if geneve option size was over 32 byte */ 1240 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 1241 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1242 /* from frame cracker output */ 1243 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 1244 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1245 /* from frame cracker output */ 1246 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 1247 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1248 }; 1249 1250 1251 /* 1252 * Pb context 1253 */ 1254 struct pb_context { 1255 __le32 crc[4]; 1256 }; 1257 1258 /* Concrete Function ID. */ 1259 struct pxp_concrete_fid { 1260 __le16 fid; 1261 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1262 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1263 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1264 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1265 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1266 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1267 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1268 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1269 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1270 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1271 }; 1272 1273 struct pxp_pretend_concrete_fid { 1274 __le16 fid; 1275 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF 1276 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1277 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 1278 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1279 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1280 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1281 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1282 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1283 }; 1284 1285 union pxp_pretend_fid { 1286 struct pxp_pretend_concrete_fid concrete_fid; 1287 __le16 opaque_fid; 1288 }; 1289 1290 /* Pxp Pretend Command Register. */ 1291 struct pxp_pretend_cmd { 1292 union pxp_pretend_fid fid; 1293 __le16 control; 1294 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1295 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1296 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1297 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1298 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1299 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1300 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1301 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1302 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1303 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1304 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 1305 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1306 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 1307 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1308 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 1309 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1310 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 1311 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1312 }; 1313 1314 /* PTT Record in PXP Admin Window. */ 1315 struct pxp_ptt_entry { 1316 __le32 offset; 1317 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1318 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1319 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1320 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1321 struct pxp_pretend_cmd pretend; 1322 }; 1323 1324 1325 /* 1326 * VF Zone A Permission Register. 1327 */ 1328 struct pxp_vf_zone_a_permission { 1329 __le32 control; 1330 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1331 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1332 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1333 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1334 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1335 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1336 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1337 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1338 }; 1339 1340 1341 /* 1342 * Rdif context 1343 */ 1344 struct rdif_task_context { 1345 __le32 initial_ref_tag; 1346 __le16 app_tag_value; 1347 __le16 app_tag_mask; 1348 u8 flags0; 1349 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1350 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1351 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1352 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1353 /* 0 = IP checksum, 1 = CRC */ 1354 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 1355 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1356 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1357 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1358 /* 1/2/3 - Protection Type */ 1359 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 1360 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1361 /* 0=0x0000, 1=0xffff */ 1362 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1363 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1364 /* Keep reference tag constant */ 1365 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 1366 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7 1367 u8 partial_dif_data[7]; 1368 __le16 partial_crc_value; 1369 __le16 partial_checksum_value; 1370 __le32 offset_in_io; 1371 __le16 flags1; 1372 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1373 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1374 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1375 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1376 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1377 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1378 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1379 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1380 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1381 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1382 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1383 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1384 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1385 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 1386 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1387 /* 0=None, 1=DIF, 2=DIX */ 1388 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 1389 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1390 /* DIF tag right at the beginning of DIF interval */ 1391 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 1392 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1393 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1394 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1395 /* 0=None, 1=DIF */ 1396 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 1397 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1398 /* Forward application tag with mask */ 1399 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 1400 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14 1401 /* Forward reference tag with mask */ 1402 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 1403 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15 1404 __le16 state; 1405 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF 1406 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0 1407 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF 1408 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4 1409 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1 1410 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8 1411 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1 1412 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9 1413 /* mask for refernce tag handling */ 1414 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF 1415 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10 1416 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1417 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1418 __le32 reserved2; 1419 }; 1420 1421 /* 1422 * RSS hash type 1423 */ 1424 enum rss_hash_type { 1425 RSS_HASH_TYPE_DEFAULT = 0, 1426 RSS_HASH_TYPE_IPV4 = 1, 1427 RSS_HASH_TYPE_TCP_IPV4 = 2, 1428 RSS_HASH_TYPE_IPV6 = 3, 1429 RSS_HASH_TYPE_TCP_IPV6 = 4, 1430 RSS_HASH_TYPE_UDP_IPV4 = 5, 1431 RSS_HASH_TYPE_UDP_IPV6 = 6, 1432 MAX_RSS_HASH_TYPE 1433 }; 1434 1435 /* 1436 * status block structure 1437 */ 1438 struct status_block_e4 { 1439 __le16 pi_array[PIS_PER_SB_E4]; 1440 __le32 sb_num; 1441 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF 1442 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0 1443 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F 1444 #define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9 1445 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF 1446 #define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16 1447 __le32 prod_index; 1448 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF 1449 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0 1450 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF 1451 #define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24 1452 }; 1453 1454 1455 /* 1456 * status block structure 1457 */ 1458 struct status_block_e5 { 1459 __le16 pi_array[PIS_PER_SB_E5]; 1460 __le32 sb_num; 1461 #define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF 1462 #define STATUS_BLOCK_E5_SB_NUM_SHIFT 0 1463 #define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F 1464 #define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9 1465 #define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF 1466 #define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16 1467 __le32 prod_index; 1468 #define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF 1469 #define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0 1470 #define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF 1471 #define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24 1472 }; 1473 1474 1475 /* 1476 * Tdif context 1477 */ 1478 struct tdif_task_context { 1479 __le32 initial_ref_tag; 1480 __le16 app_tag_value; 1481 __le16 app_tag_mask; 1482 __le16 partial_crc_value_b; 1483 __le16 partial_checksum_value_b; 1484 __le16 stateB; 1485 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF 1486 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0 1487 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF 1488 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4 1489 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1 1490 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8 1491 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1 1492 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9 1493 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1494 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1495 u8 reserved1; 1496 u8 flags0; 1497 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1498 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1499 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1500 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1501 /* 0 = IP checksum, 1 = CRC */ 1502 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 1503 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1504 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1505 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1506 /* 1/2/3 - Protection Type */ 1507 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 1508 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1509 /* 0=0x0000, 1=0xffff */ 1510 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 1511 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1512 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1513 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1514 __le32 flags1; 1515 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1516 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1517 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1518 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1519 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1520 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1521 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1522 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1523 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1524 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1525 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1526 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1527 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1528 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 1529 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1530 /* 0=None, 1=DIF, 2=DIX */ 1531 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 1532 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1533 /* DIF tag right at the beginning of DIF interval */ 1534 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 1535 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1536 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1537 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1538 /* 0=None, 1=DIF */ 1539 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 1540 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1541 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF 1542 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14 1543 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF 1544 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18 1545 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1 1546 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22 1547 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1 1548 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23 1549 /* mask for refernce tag handling */ 1550 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF 1551 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24 1552 /* Forward application tag with mask */ 1553 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 1554 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28 1555 /* Forward reference tag with mask */ 1556 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 1557 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29 1558 /* Keep reference tag constant */ 1559 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 1560 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30 1561 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1562 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1563 __le32 offset_in_io_b; 1564 __le16 partial_crc_value_a; 1565 __le16 partial_checksum_value_a; 1566 __le32 offset_in_io_a; 1567 u8 partial_dif_data_a[8]; 1568 u8 partial_dif_data_b[8]; 1569 }; 1570 1571 1572 /* 1573 * Timers context 1574 */ 1575 struct timers_context { 1576 __le32 logical_client_0; 1577 /* Expiration time of logical client 0 */ 1578 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF 1579 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1580 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1581 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1582 /* Valid bit of logical client 0 */ 1583 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 1584 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1585 /* Active bit of logical client 0 */ 1586 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 1587 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1588 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1589 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1590 __le32 logical_client_1; 1591 /* Expiration time of logical client 1 */ 1592 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF 1593 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1594 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1595 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1596 /* Valid bit of logical client 1 */ 1597 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 1598 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1599 /* Active bit of logical client 1 */ 1600 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 1601 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1602 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1603 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1604 __le32 logical_client_2; 1605 /* Expiration time of logical client 2 */ 1606 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF 1607 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1608 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1609 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1610 /* Valid bit of logical client 2 */ 1611 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 1612 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1613 /* Active bit of logical client 2 */ 1614 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 1615 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1616 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1617 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1618 __le32 host_expiration_fields; 1619 /* Expiration time on host (closest one) */ 1620 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF 1621 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1622 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1623 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1624 /* Valid bit of host expiration */ 1625 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 1626 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1627 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1628 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1629 }; 1630 1631 1632 /* 1633 * Enum for next_protocol field of tunnel_parsing_flags 1634 */ 1635 enum tunnel_next_protocol { 1636 e_unknown = 0, 1637 e_l2 = 1, 1638 e_ipv4 = 2, 1639 e_ipv6 = 3, 1640 MAX_TUNNEL_NEXT_PROTOCOL 1641 }; 1642 1643 #endif /* __COMMON_HSI__ */ 1644