1 /* 2 * Copyright (c) 2014, 2015 Netronome Systems, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution 14 * 15 * 3. Neither the name of the copyright holder nor the names of its 16 * contributors may be used to endorse or promote products derived from this 17 * software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * vim:shiftwidth=8:noexpandtab 34 * 35 * Netronome network device driver: Control BAR layout 36 */ 37 #ifndef _NFP_NET_CTRL_H_ 38 #define _NFP_NET_CTRL_H_ 39 40 /* 41 * Configuration BAR size. 42 * 43 * The configuration BAR is 8K in size, but on the NFP6000, due to 44 * THB-350, 32k needs to be reserved. 45 */ 46 #ifdef __NFP_IS_6000 47 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 48 #else 49 #define NFP_NET_CFG_BAR_SZ (8 * 1024) 50 #endif 51 52 /* Offset in Freelist buffer where packet starts on RX */ 53 #define NFP_NET_RX_OFFSET 32 54 55 /* working with metadata api (NFD version > 3.0) */ 56 #define NFP_NET_META_FIELD_SIZE 4 57 #define NFP_NET_META_FIELD_MASK ((1 << NFP_NET_META_FIELD_SIZE) - 1) 58 59 /* Prepend field types */ 60 #define NFP_NET_META_HASH 1 /* next field carries hash type */ 61 62 /* Hash type pre-pended when a RSS hash was computed */ 63 #define NFP_NET_RSS_NONE 0 64 #define NFP_NET_RSS_IPV4 1 65 #define NFP_NET_RSS_IPV6 2 66 #define NFP_NET_RSS_IPV6_EX 3 67 #define NFP_NET_RSS_IPV4_TCP 4 68 #define NFP_NET_RSS_IPV6_TCP 5 69 #define NFP_NET_RSS_IPV6_EX_TCP 6 70 #define NFP_NET_RSS_IPV4_UDP 7 71 #define NFP_NET_RSS_IPV6_UDP 8 72 #define NFP_NET_RSS_IPV6_EX_UDP 9 73 74 /* 75 * @NFP_NET_TXR_MAX: Maximum number of TX rings 76 * @NFP_NET_TXR_MASK: Mask for TX rings 77 * @NFP_NET_RXR_MAX: Maximum number of RX rings 78 * @NFP_NET_RXR_MASK: Mask for RX rings 79 */ 80 #define NFP_NET_TXR_MAX 64 81 #define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1) 82 #define NFP_NET_RXR_MAX 64 83 #define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1) 84 85 /* 86 * Read/Write config words (0x0000 - 0x002c) 87 * @NFP_NET_CFG_CTRL: Global control 88 * @NFP_NET_CFG_UPDATE: Indicate which fields are updated 89 * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 90 * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 91 * @NFP_NET_CFG_MTU: Set MTU size 92 * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 93 * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions 94 * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes 95 * @NFP_NET_CFG_MACADDR: MAC address 96 * 97 * TODO: 98 * - define Error details in UPDATE 99 */ 100 #define NFP_NET_CFG_CTRL 0x0000 101 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 102 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 103 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 104 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 105 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 106 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 107 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 108 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 109 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 110 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 111 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */ 112 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 113 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */ 114 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 115 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 116 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 117 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 118 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 119 #define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */ 120 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */ 121 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */ 122 #define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */ 123 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 124 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 125 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31)/* live MAC addr change */ 126 #define NFP_NET_CFG_UPDATE 0x0004 127 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 128 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 129 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 130 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 131 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 132 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 133 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 134 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 135 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 136 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 137 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 138 #define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */ 139 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 140 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 141 #define NFP_NET_CFG_MTU 0x0018 142 #define NFP_NET_CFG_FLBUFSZ 0x001c 143 #define NFP_NET_CFG_EXN 0x001f 144 #define NFP_NET_CFG_LSC 0x0020 145 #define NFP_NET_CFG_MACADDR 0x0024 146 147 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2) 148 149 /* 150 * Read-only words (0x0030 - 0x0050): 151 * @NFP_NET_CFG_VERSION: Firmware version number 152 * @NFP_NET_CFG_STS: Status 153 * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL) 154 * @NFP_NET_MAX_TXRINGS: Maximum number of TX rings 155 * @NFP_NET_MAX_RXRINGS: Maximum number of RX rings 156 * @NFP_NET_MAX_MTU: Maximum support MTU 157 * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 158 * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 159 * 160 * TODO: 161 * - define more STS bits 162 */ 163 #define NFP_NET_CFG_VERSION 0x0030 164 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24) 165 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 166 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 167 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 168 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 169 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 170 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 171 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 172 #define NFP_NET_CFG_STS 0x0034 173 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 174 /* Link rate */ 175 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 176 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 177 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 178 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 179 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 180 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 181 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 182 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 183 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 184 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 185 #define NFP_NET_CFG_CAP 0x0038 186 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 187 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 188 #define NFP_NET_CFG_MAX_MTU 0x0044 189 /* Next two words are being used by VFs for solving THB350 issue */ 190 #define NFP_NET_CFG_START_TXQ 0x0048 191 #define NFP_NET_CFG_START_RXQ 0x004c 192 193 /* 194 * NFP-3200 workaround (0x0050 - 0x0058) 195 * @NFP_NET_CFG_SPARE_ADDR: DMA address for ME code to use (e.g. YDS-155 fix) 196 */ 197 #define NFP_NET_CFG_SPARE_ADDR 0x0050 198 /** 199 * NFP6000/NFP4000 - Prepend configuration 200 */ 201 #define NFP_NET_CFG_RX_OFFSET 0x0050 202 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 203 204 /** 205 * Reuse spare address to contain the offset from the start of 206 * the host buffer where the first byte of the received frame 207 * will land. Any metadata will come prior to that offset. If the 208 * value in this field is 0, it means that that the metadata will 209 * always land starting at the first byte of the host buffer and 210 * packet data will immediately follow the metadata. As always, 211 * the RX descriptor indicates the presence or absence of metadata 212 * along with the length thereof. 213 */ 214 #define NFP_NET_CFG_RX_OFFSET_ADDR 0x0050 215 216 #define NFP_NET_CFG_VXLAN_PORT 0x0060 217 #define NFP_NET_CFG_VXLAN_SZ 0x0008 218 219 /* Offload definitions */ 220 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t)) 221 222 /** 223 * 64B reserved for future use (0x0080 - 0x00c0) 224 */ 225 #define NFP_NET_CFG_RESERVED 0x0080 226 #define NFP_NET_CFG_RESERVED_SZ 0x0040 227 228 /* 229 * RSS configuration (0x0100 - 0x01ac): 230 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 231 * @NFP_NET_CFG_RSS_CFG: RSS configuration word 232 * @NFP_NET_CFG_RSS_KEY: RSS "secret" key 233 * @NFP_NET_CFG_RSS_ITBL: RSS indirection table 234 */ 235 #define NFP_NET_CFG_RSS_BASE 0x0100 236 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 237 #define NFP_NET_CFG_RSS_MASK (0x7f) 238 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 239 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 240 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 241 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 242 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 243 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 244 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 245 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 246 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 247 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 248 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 249 NFP_NET_CFG_RSS_KEY_SZ) 250 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 251 252 /* 253 * TX ring configuration (0x200 - 0x800) 254 * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 255 * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 256 * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 257 * @NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 258 * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 259 * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 260 * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 261 */ 262 #define NFP_NET_CFG_TXR_BASE 0x0200 263 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 264 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 265 ((_x) * 0x8)) 266 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 267 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 268 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 269 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 270 ((_x) * 0x4)) 271 272 /* 273 * RX ring configuration (0x0800 - 0x0c00) 274 * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 275 * @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries) 276 * @NFP_NET_CFG_RXR_SZ: Per TX ring ring size (1B entries) 277 * @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries) 278 * @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries) 279 * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries) 280 */ 281 #define NFP_NET_CFG_RXR_BASE 0x0800 282 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 283 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 284 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 285 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 286 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 287 ((_x) * 0x4)) 288 289 /* 290 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 291 * These registers are only used when MSI-X auto-masking is not 292 * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 293 * by MSI-X entry and are 1B in size. If an entry is zero, the 294 * corresponding entry is enabled. If the FW generates an interrupt, 295 * it writes a cause into the corresponding field. This also masks 296 * the MSI-X entry and the host driver must clear the register to 297 * re-enable the interrupt. 298 */ 299 #define NFP_NET_CFG_ICR_BASE 0x0c00 300 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 301 #define NFP_NET_CFG_ICR_UNMASKED 0x0 302 #define NFP_NET_CFG_ICR_RXTX 0x1 303 #define NFP_NET_CFG_ICR_LSC 0x2 304 305 /* 306 * General device stats (0x0d00 - 0x0d90) 307 * all counters are 64bit. 308 */ 309 #define NFP_NET_CFG_STATS_BASE 0x0d00 310 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 311 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 312 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 313 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 314 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 315 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 316 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 317 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 318 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 319 320 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 321 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 322 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 323 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 324 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 325 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 326 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 327 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 328 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 329 330 /* 331 * Per ring stats (0x1000 - 0x1800) 332 * options, 64bit per entry 333 * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 334 * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 335 */ 336 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 337 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 338 ((_x) * 0x10)) 339 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 340 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 341 ((_x) * 0x10)) 342 343 /* PF multiport offset */ 344 #define NFP_PF_CSR_SLICE_SIZE (32 * 1024) 345 346 #endif /* _NFP_NET_CTRL_H_ */ 347 /* 348 * Local variables: 349 * c-file-style: "Linux" 350 * indent-tabs-mode: t 351 * End: 352 */ 353