1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdint.h> 11 #include <limits.h> 12 #include <net/if.h> 13 #include <netinet/in.h> 14 #include <sys/queue.h> 15 16 /* Verbs header. */ 17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic ignored "-Wpedantic" 20 #endif 21 #include <infiniband/verbs.h> 22 #ifdef PEDANTIC 23 #pragma GCC diagnostic error "-Wpedantic" 24 #endif 25 26 #include <rte_pci.h> 27 #include <rte_ether.h> 28 #include <rte_ethdev_driver.h> 29 #include <rte_rwlock.h> 30 #include <rte_interrupts.h> 31 #include <rte_errno.h> 32 #include <rte_flow.h> 33 34 #include "mlx5_utils.h" 35 #include "mlx5_mr.h" 36 #include "mlx5_rxtx.h" 37 #include "mlx5_autoconf.h" 38 #include "mlx5_defs.h" 39 40 enum { 41 PCI_VENDOR_ID_MELLANOX = 0x15b3, 42 }; 43 44 enum { 45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 55 }; 56 57 /** Switch information returned by mlx5_nl_switch_info(). */ 58 struct mlx5_switch_info { 59 uint32_t master:1; /**< Master device. */ 60 uint32_t representor:1; /**< Representor device. */ 61 int32_t port_name; /**< Representor port name. */ 62 uint64_t switch_id; /**< Switch identifier. */ 63 }; 64 65 LIST_HEAD(mlx5_dev_list, priv); 66 67 /* Shared memory between primary and secondary processes. */ 68 struct mlx5_shared_data { 69 struct mlx5_dev_list mem_event_cb_list; 70 rte_rwlock_t mem_event_rwlock; 71 }; 72 73 extern struct mlx5_shared_data *mlx5_shared_data; 74 75 struct mlx5_counter_ctrl { 76 /* Name of the counter. */ 77 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 78 /* Name of the counter on the device table. */ 79 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 80 uint32_t ib:1; /**< Nonzero for IB counters. */ 81 }; 82 83 struct mlx5_xstats_ctrl { 84 /* Number of device stats. */ 85 uint16_t stats_n; 86 /* Number of device stats identified by PMD. */ 87 uint16_t mlx5_stats_n; 88 /* Index in the device counters table. */ 89 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 90 uint64_t base[MLX5_MAX_XSTATS]; 91 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 92 }; 93 94 /* Flow list . */ 95 TAILQ_HEAD(mlx5_flows, rte_flow); 96 97 /* Default PMD specific parameter value. */ 98 #define MLX5_ARG_UNSET (-1) 99 100 /* 101 * Device configuration structure. 102 * 103 * Merged configuration from: 104 * 105 * - Device capabilities, 106 * - User device parameters disabled features. 107 */ 108 struct mlx5_dev_config { 109 unsigned int hw_csum:1; /* Checksum offload is supported. */ 110 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 111 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 112 unsigned int hw_padding:1; /* End alignment padding is supported. */ 113 unsigned int vf:1; /* This is a VF. */ 114 unsigned int tunnel_en:1; 115 /* Whether tunnel stateless offloads are supported. */ 116 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 117 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 118 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 119 unsigned int tso:1; /* Whether TSO is supported. */ 120 unsigned int tx_vec_en:1; /* Tx vector is enabled. */ 121 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 122 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */ 123 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 124 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 125 unsigned int dv_flow_en:1; /* Enable DV flow. */ 126 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 127 struct { 128 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 129 unsigned int stride_num_n; /* Number of strides. */ 130 unsigned int min_stride_size_n; /* Min size of a stride. */ 131 unsigned int max_stride_size_n; /* Max size of a stride. */ 132 unsigned int max_memcpy_len; 133 /* Maximum packet size to memcpy Rx packets. */ 134 unsigned int min_rxqs_num; 135 /* Rx queue count threshold to enable MPRQ. */ 136 } mprq; /* Configurations for Multi-Packet RQ. */ 137 int mps; /* Multi-packet send supported mode. */ 138 unsigned int flow_prio; /* Number of flow priorities. */ 139 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 140 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 141 int txq_inline; /* Maximum packet size for inlining. */ 142 int txqs_inline; /* Queue number threshold for inlining. */ 143 int txqs_vec; /* Queue number threshold for vectorized Tx. */ 144 int inline_max_packet_sz; /* Max packet size for inlining. */ 145 }; 146 147 /** 148 * Type of objet being allocated. 149 */ 150 enum mlx5_verbs_alloc_type { 151 MLX5_VERBS_ALLOC_TYPE_NONE, 152 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 153 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 154 }; 155 156 /** 157 * Verbs allocator needs a context to know in the callback which kind of 158 * resources it is allocating. 159 */ 160 struct mlx5_verbs_alloc_ctx { 161 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 162 const void *obj; /* Pointer to the DPDK object. */ 163 }; 164 165 LIST_HEAD(mlx5_mr_list, mlx5_mr); 166 167 /* Flow drop context necessary due to Verbs API. */ 168 struct mlx5_drop { 169 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 170 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */ 171 }; 172 173 struct mlx5_flow_tcf_context; 174 175 struct priv { 176 LIST_ENTRY(priv) mem_event_cb; /* Called by memory event callback. */ 177 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 178 struct ibv_context *ctx; /* Verbs context. */ 179 struct ibv_device_attr_ex device_attr; /* Device properties. */ 180 struct ibv_pd *pd; /* Protection Domain. */ 181 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */ 182 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ 183 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 184 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 185 /* Bit-field of MAC addresses owned by the PMD. */ 186 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 187 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 188 /* Device properties. */ 189 uint16_t mtu; /* Configured MTU. */ 190 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 191 unsigned int representor:1; /* Device is a port representor. */ 192 uint16_t domain_id; /* Switch domain identifier. */ 193 int32_t representor_id; /* Port representor identifier. */ 194 /* RX/TX queues. */ 195 unsigned int rxqs_n; /* RX queues array size. */ 196 unsigned int txqs_n; /* TX queues array size. */ 197 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 198 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 199 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 200 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 201 struct rte_intr_handle intr_handle; /* Interrupt handler. */ 202 unsigned int (*reta_idx)[]; /* RETA index table. */ 203 unsigned int reta_idx_n; /* RETA index size. */ 204 struct mlx5_drop drop_queue; /* Flow drop queues. */ 205 struct mlx5_flows flows; /* RTE Flow rules. */ 206 struct mlx5_flows ctrl_flows; /* Control flow rules. */ 207 LIST_HEAD(counters, mlx5_flow_counter) flow_counters; 208 /* Flow counters. */ 209 struct { 210 uint32_t dev_gen; /* Generation number to flush local caches. */ 211 rte_rwlock_t rwlock; /* MR Lock. */ 212 struct mlx5_mr_btree cache; /* Global MR cache table. */ 213 struct mlx5_mr_list mr_list; /* Registered MR list. */ 214 struct mlx5_mr_list mr_free_list; /* Freed MR list. */ 215 } mr; 216 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 217 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */ 218 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ 219 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 220 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */ 221 /* Verbs Indirection tables. */ 222 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls; 223 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 224 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps; 225 uint32_t link_speed_capa; /* Link speed capabilities. */ 226 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 227 int primary_socket; /* Unix socket for primary process. */ 228 void *uar_base; /* Reserved address space for UAR mapping */ 229 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */ 230 struct mlx5_dev_config config; /* Device configuration. */ 231 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 232 /* Context for Verbs allocator. */ 233 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 234 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 235 uint32_t nl_sn; /* Netlink message sequence number. */ 236 #ifndef RTE_ARCH_64 237 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 238 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 239 /* UAR same-page access control required in 32bit implementations. */ 240 #endif 241 struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */ 242 }; 243 244 #define PORT_ID(priv) ((priv)->dev_data->port_id) 245 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 246 247 /* mlx5.c */ 248 249 int mlx5_getenv_int(const char *); 250 251 /* mlx5_ethdev.c */ 252 253 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); 254 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 255 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); 256 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 257 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, 258 unsigned int flags); 259 int mlx5_dev_configure(struct rte_eth_dev *dev); 260 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 261 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 262 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 263 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); 264 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 265 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 266 struct rte_eth_fc_conf *fc_conf); 267 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 268 struct rte_eth_fc_conf *fc_conf); 269 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device, 270 struct rte_pci_addr *pci_addr); 271 void mlx5_dev_link_status_handler(void *arg); 272 void mlx5_dev_interrupt_handler(void *arg); 273 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); 274 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); 275 int mlx5_set_link_down(struct rte_eth_dev *dev); 276 int mlx5_set_link_up(struct rte_eth_dev *dev); 277 int mlx5_is_removed(struct rte_eth_dev *dev); 278 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 279 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 280 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev, 281 uint16_t *port_list, 282 unsigned int port_list_n); 283 int mlx5_sysfs_switch_info(unsigned int ifindex, 284 struct mlx5_switch_info *info); 285 286 /* mlx5_mac.c */ 287 288 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]); 289 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 290 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac, 291 uint32_t index, uint32_t vmdq); 292 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr); 293 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 294 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr); 295 296 /* mlx5_rss.c */ 297 298 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 299 struct rte_eth_rss_conf *rss_conf); 300 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 301 struct rte_eth_rss_conf *rss_conf); 302 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 303 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 304 struct rte_eth_rss_reta_entry64 *reta_conf, 305 uint16_t reta_size); 306 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 307 struct rte_eth_rss_reta_entry64 *reta_conf, 308 uint16_t reta_size); 309 310 /* mlx5_rxmode.c */ 311 312 void mlx5_promiscuous_enable(struct rte_eth_dev *dev); 313 void mlx5_promiscuous_disable(struct rte_eth_dev *dev); 314 void mlx5_allmulticast_enable(struct rte_eth_dev *dev); 315 void mlx5_allmulticast_disable(struct rte_eth_dev *dev); 316 317 /* mlx5_stats.c */ 318 319 void mlx5_xstats_init(struct rte_eth_dev *dev); 320 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 321 void mlx5_stats_reset(struct rte_eth_dev *dev); 322 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 323 unsigned int n); 324 void mlx5_xstats_reset(struct rte_eth_dev *dev); 325 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 326 struct rte_eth_xstat_name *xstats_names, 327 unsigned int n); 328 329 /* mlx5_vlan.c */ 330 331 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 332 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 333 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 334 335 /* mlx5_trigger.c */ 336 337 int mlx5_dev_start(struct rte_eth_dev *dev); 338 void mlx5_dev_stop(struct rte_eth_dev *dev); 339 int mlx5_traffic_enable(struct rte_eth_dev *dev); 340 void mlx5_traffic_disable(struct rte_eth_dev *dev); 341 int mlx5_traffic_restart(struct rte_eth_dev *dev); 342 343 /* mlx5_flow.c */ 344 345 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 346 void mlx5_flow_print(struct rte_flow *flow); 347 int mlx5_flow_validate(struct rte_eth_dev *dev, 348 const struct rte_flow_attr *attr, 349 const struct rte_flow_item items[], 350 const struct rte_flow_action actions[], 351 struct rte_flow_error *error); 352 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 353 const struct rte_flow_attr *attr, 354 const struct rte_flow_item items[], 355 const struct rte_flow_action actions[], 356 struct rte_flow_error *error); 357 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 358 struct rte_flow_error *error); 359 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list); 360 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 361 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 362 const struct rte_flow_action *action, void *data, 363 struct rte_flow_error *error); 364 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 365 struct rte_flow_error *error); 366 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 367 enum rte_filter_type filter_type, 368 enum rte_filter_op filter_op, 369 void *arg); 370 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list); 371 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list); 372 int mlx5_flow_verify(struct rte_eth_dev *dev); 373 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 374 struct rte_flow_item_eth *eth_spec, 375 struct rte_flow_item_eth *eth_mask, 376 struct rte_flow_item_vlan *vlan_spec, 377 struct rte_flow_item_vlan *vlan_mask); 378 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 379 struct rte_flow_item_eth *eth_spec, 380 struct rte_flow_item_eth *eth_mask); 381 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 382 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 383 384 /* mlx5_socket.c */ 385 386 int mlx5_socket_init(struct rte_eth_dev *priv); 387 void mlx5_socket_uninit(struct rte_eth_dev *priv); 388 void mlx5_socket_handle(struct rte_eth_dev *priv); 389 int mlx5_socket_connect(struct rte_eth_dev *priv); 390 391 /* mlx5_nl.c */ 392 393 int mlx5_nl_init(int protocol); 394 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac, 395 uint32_t index); 396 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac, 397 uint32_t index); 398 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev); 399 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev); 400 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable); 401 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable); 402 unsigned int mlx5_nl_ifindex(int nl, const char *name); 403 int mlx5_nl_switch_info(int nl, unsigned int ifindex, 404 struct mlx5_switch_info *info); 405 406 #endif /* RTE_PMD_MLX5_H_ */ 407