1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef RTE_PMD_MLX5_H_ 35 #define RTE_PMD_MLX5_H_ 36 37 #include <stddef.h> 38 #include <stdint.h> 39 #include <limits.h> 40 #include <net/if.h> 41 #include <netinet/in.h> 42 #include <sys/queue.h> 43 44 /* Verbs header. */ 45 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 46 #ifdef PEDANTIC 47 #pragma GCC diagnostic ignored "-Wpedantic" 48 #endif 49 #include <infiniband/verbs.h> 50 #ifdef PEDANTIC 51 #pragma GCC diagnostic error "-Wpedantic" 52 #endif 53 54 #include <rte_pci.h> 55 #include <rte_ether.h> 56 #include <rte_ethdev.h> 57 #include <rte_spinlock.h> 58 #include <rte_interrupts.h> 59 #include <rte_errno.h> 60 #include <rte_flow.h> 61 62 #include "mlx5_utils.h" 63 #include "mlx5_rxtx.h" 64 #include "mlx5_autoconf.h" 65 #include "mlx5_defs.h" 66 67 enum { 68 PCI_VENDOR_ID_MELLANOX = 0x15b3, 69 }; 70 71 enum { 72 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 73 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 74 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 75 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 76 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 77 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 78 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 79 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 80 }; 81 82 struct mlx5_xstats_ctrl { 83 /* Number of device stats. */ 84 uint16_t stats_n; 85 /* Index in the device counters table. */ 86 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 87 uint64_t base[MLX5_MAX_XSTATS]; 88 }; 89 90 /* Flow list . */ 91 TAILQ_HEAD(mlx5_flows, rte_flow); 92 93 /** 94 * Type of objet being allocated. 95 */ 96 enum mlx5_verbs_alloc_type { 97 MLX5_VERBS_ALLOC_TYPE_NONE, 98 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 99 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 100 }; 101 102 /** 103 * Verbs allocator needs a context to know in the callback which kind of 104 * resources it is allocating. 105 */ 106 struct mlx5_verbs_alloc_ctx { 107 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 108 const void *obj; /* Pointer to the DPDK object. */ 109 }; 110 111 struct priv { 112 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 113 struct ibv_context *ctx; /* Verbs context. */ 114 struct ibv_device_attr_ex device_attr; /* Device properties. */ 115 struct ibv_pd *pd; /* Protection Domain. */ 116 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ 117 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 118 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 119 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 120 /* Device properties. */ 121 uint16_t mtu; /* Configured MTU. */ 122 uint8_t port; /* Physical port number. */ 123 unsigned int hw_csum:1; /* Checksum offload is supported. */ 124 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */ 125 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 126 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 127 unsigned int hw_padding:1; /* End alignment padding is supported. */ 128 unsigned int mps:2; /* Multi-packet send mode (0: disabled). */ 129 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */ 130 unsigned int cqe_comp:1; /* Whether CQE compression is enabled. */ 131 unsigned int tso:1; /* Whether TSO is supported. */ 132 unsigned int tunnel_en:1; 133 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 134 unsigned int tx_vec_en:1; /* Whether Tx vector is enabled. */ 135 unsigned int rx_vec_en:1; /* Whether Rx vector is enabled. */ 136 unsigned int counter_set_supported:1; /* Counter set is supported. */ 137 /* Whether Tx offloads for tunneled packets are supported. */ 138 unsigned int max_tso_payload_sz; /* Maximum TCP payload for TSO. */ 139 unsigned int txq_inline; /* Maximum packet size for inlining. */ 140 unsigned int txqs_inline; /* Queue number threshold for inlining. */ 141 unsigned int inline_max_packet_sz; /* Max packet size for inlining. */ 142 /* RX/TX queues. */ 143 unsigned int rxqs_n; /* RX queues array size. */ 144 unsigned int txqs_n; /* TX queues array size. */ 145 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 146 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 147 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 148 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 149 struct rte_intr_handle intr_handle; /* Interrupt handler. */ 150 unsigned int (*reta_idx)[]; /* RETA index table. */ 151 unsigned int reta_idx_n; /* RETA index size. */ 152 struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */ 153 struct mlx5_flows flows; /* RTE Flow rules. */ 154 struct mlx5_flows ctrl_flows; /* Control flow rules. */ 155 LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */ 156 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 157 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */ 158 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ 159 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 160 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */ 161 /* Verbs Indirection tables. */ 162 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls; 163 uint32_t link_speed_capa; /* Link speed capabilities. */ 164 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 165 rte_spinlock_t mr_lock; /* MR Lock. */ 166 int primary_socket; /* Unix socket for primary process. */ 167 void *uar_base; /* Reserved address space for UAR mapping */ 168 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */ 169 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 170 /* Context for Verbs allocator. */ 171 }; 172 173 #define PORT_ID(priv) ((priv)->dev_data->port_id) 174 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 175 176 /* mlx5.c */ 177 178 int mlx5_getenv_int(const char *); 179 180 /* mlx5_ethdev.c */ 181 182 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); 183 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); 184 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 185 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, 186 unsigned int flags); 187 int mlx5_dev_configure(struct rte_eth_dev *dev); 188 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 189 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 190 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 191 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); 192 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 193 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 194 struct rte_eth_fc_conf *fc_conf); 195 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 196 struct rte_eth_fc_conf *fc_conf); 197 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device, 198 struct rte_pci_addr *pci_addr); 199 void mlx5_dev_link_status_handler(void *arg); 200 void mlx5_dev_interrupt_handler(void *arg); 201 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); 202 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); 203 int mlx5_set_link_down(struct rte_eth_dev *dev); 204 int mlx5_set_link_up(struct rte_eth_dev *dev); 205 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 206 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 207 208 /* mlx5_mac.c */ 209 210 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]); 211 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 212 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac, 213 uint32_t index, uint32_t vmdq); 214 void mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr); 215 216 /* mlx5_rss.c */ 217 218 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 219 struct rte_eth_rss_conf *rss_conf); 220 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 221 struct rte_eth_rss_conf *rss_conf); 222 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 223 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 224 struct rte_eth_rss_reta_entry64 *reta_conf, 225 uint16_t reta_size); 226 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 227 struct rte_eth_rss_reta_entry64 *reta_conf, 228 uint16_t reta_size); 229 230 /* mlx5_rxmode.c */ 231 232 void mlx5_promiscuous_enable(struct rte_eth_dev *dev); 233 void mlx5_promiscuous_disable(struct rte_eth_dev *dev); 234 void mlx5_allmulticast_enable(struct rte_eth_dev *dev); 235 void mlx5_allmulticast_disable(struct rte_eth_dev *dev); 236 237 /* mlx5_stats.c */ 238 239 void mlx5_xstats_init(struct rte_eth_dev *dev); 240 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 241 void mlx5_stats_reset(struct rte_eth_dev *dev); 242 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 243 unsigned int n); 244 void mlx5_xstats_reset(struct rte_eth_dev *dev); 245 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 246 struct rte_eth_xstat_name *xstats_names, 247 unsigned int n); 248 249 /* mlx5_vlan.c */ 250 251 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 252 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 253 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 254 255 /* mlx5_trigger.c */ 256 257 int mlx5_dev_start(struct rte_eth_dev *dev); 258 void mlx5_dev_stop(struct rte_eth_dev *dev); 259 int mlx5_traffic_enable(struct rte_eth_dev *dev); 260 void mlx5_traffic_disable(struct rte_eth_dev *dev); 261 int mlx5_traffic_restart(struct rte_eth_dev *dev); 262 263 /* mlx5_flow.c */ 264 265 int mlx5_flow_validate(struct rte_eth_dev *dev, 266 const struct rte_flow_attr *attr, 267 const struct rte_flow_item items[], 268 const struct rte_flow_action actions[], 269 struct rte_flow_error *error); 270 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 271 const struct rte_flow_attr *attr, 272 const struct rte_flow_item items[], 273 const struct rte_flow_action actions[], 274 struct rte_flow_error *error); 275 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 276 struct rte_flow_error *error); 277 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list); 278 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 279 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 280 enum rte_flow_action_type action, void *data, 281 struct rte_flow_error *error); 282 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 283 struct rte_flow_error *error); 284 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 285 enum rte_filter_type filter_type, 286 enum rte_filter_op filter_op, 287 void *arg); 288 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list); 289 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list); 290 int mlx5_flow_verify(struct rte_eth_dev *dev); 291 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 292 struct rte_flow_item_eth *eth_spec, 293 struct rte_flow_item_eth *eth_mask, 294 struct rte_flow_item_vlan *vlan_spec, 295 struct rte_flow_item_vlan *vlan_mask); 296 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 297 struct rte_flow_item_eth *eth_spec, 298 struct rte_flow_item_eth *eth_mask); 299 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 300 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 301 302 /* mlx5_socket.c */ 303 304 int mlx5_socket_init(struct rte_eth_dev *priv); 305 void mlx5_socket_uninit(struct rte_eth_dev *priv); 306 void mlx5_socket_handle(struct rte_eth_dev *priv); 307 int mlx5_socket_connect(struct rte_eth_dev *priv); 308 309 /* mlx5_mr.c */ 310 311 struct mlx5_mr *mlx5_mr_new(struct rte_eth_dev *dev, struct rte_mempool *mp); 312 struct mlx5_mr *mlx5_mr_get(struct rte_eth_dev *dev, struct rte_mempool *mp); 313 int mlx5_mr_release(struct mlx5_mr *mr); 314 int mlx5_mr_verify(struct rte_eth_dev *dev); 315 316 #endif /* RTE_PMD_MLX5_H_ */ 317