1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2017 6WIND S.A. 5 * Copyright 2017 Mellanox 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef MLX4_PRM_H_ 35 #define MLX4_PRM_H_ 36 37 #include <rte_atomic.h> 38 #include <rte_branch_prediction.h> 39 #include <rte_byteorder.h> 40 41 /* Verbs headers do not support -pedantic. */ 42 #ifdef PEDANTIC 43 #pragma GCC diagnostic ignored "-Wpedantic" 44 #endif 45 #include <infiniband/mlx4dv.h> 46 #include <infiniband/verbs.h> 47 #ifdef PEDANTIC 48 #pragma GCC diagnostic error "-Wpedantic" 49 #endif 50 51 /* ConnectX-3 Tx queue basic block. */ 52 #define MLX4_TXBB_SHIFT 6 53 #define MLX4_TXBB_SIZE (1 << MLX4_TXBB_SHIFT) 54 55 /* Typical TSO descriptor with 16 gather entries is 352 bytes. */ 56 #define MLX4_MAX_WQE_SIZE 512 57 #define MLX4_MAX_WQE_TXBBS (MLX4_MAX_WQE_SIZE / MLX4_TXBB_SIZE) 58 59 /* Send queue stamping/invalidating information. */ 60 #define MLX4_SQ_STAMP_STRIDE 64 61 #define MLX4_SQ_STAMP_DWORDS (MLX4_SQ_STAMP_STRIDE / 4) 62 #define MLX4_SQ_STAMP_SHIFT 31 63 #define MLX4_SQ_STAMP_VAL 0x7fffffff 64 65 /* Work queue element (WQE) flags. */ 66 #define MLX4_BIT_WQE_OWN 0x80000000 67 #define MLX4_WQE_CTRL_IIP_HDR_CSUM (1 << 28) 68 #define MLX4_WQE_CTRL_IL4_HDR_CSUM (1 << 27) 69 70 #define MLX4_SIZE_TO_TXBBS(size) \ 71 (RTE_ALIGN((size), (MLX4_TXBB_SIZE)) >> (MLX4_TXBB_SHIFT)) 72 73 /* CQE checksum flags. */ 74 enum { 75 MLX4_CQE_L2_TUNNEL_IPV4 = (int)(1u << 25), 76 MLX4_CQE_L2_TUNNEL_L4_CSUM = (int)(1u << 26), 77 MLX4_CQE_L2_TUNNEL = (int)(1u << 27), 78 MLX4_CQE_L2_VLAN_MASK = (int)(3u << 29), 79 MLX4_CQE_L2_TUNNEL_IPOK = (int)(1u << 31), 80 }; 81 82 /* CQE status flags. */ 83 #define MLX4_CQE_STATUS_IPV4 (1 << 22) 84 #define MLX4_CQE_STATUS_IPV4F (1 << 23) 85 #define MLX4_CQE_STATUS_IPV6 (1 << 24) 86 #define MLX4_CQE_STATUS_IPV4OPT (1 << 25) 87 #define MLX4_CQE_STATUS_TCP (1 << 26) 88 #define MLX4_CQE_STATUS_UDP (1 << 27) 89 #define MLX4_CQE_STATUS_PTYPE_MASK \ 90 (MLX4_CQE_STATUS_IPV4 | \ 91 MLX4_CQE_STATUS_IPV4F | \ 92 MLX4_CQE_STATUS_IPV6 | \ 93 MLX4_CQE_STATUS_IPV4OPT | \ 94 MLX4_CQE_STATUS_TCP | \ 95 MLX4_CQE_STATUS_UDP) 96 97 /* Send queue information. */ 98 struct mlx4_sq { 99 volatile uint8_t *buf; /**< SQ buffer. */ 100 volatile uint8_t *eob; /**< End of SQ buffer */ 101 uint32_t head; /**< SQ head counter in units of TXBBS. */ 102 uint32_t tail; /**< SQ tail counter in units of TXBBS. */ 103 uint32_t txbb_cnt; /**< Num of WQEBB in the Q (should be ^2). */ 104 uint32_t txbb_cnt_mask; /**< txbbs_cnt mask (txbb_cnt is ^2). */ 105 uint32_t headroom_txbbs; /**< Num of txbbs that should be kept free. */ 106 volatile uint32_t *db; /**< Pointer to the doorbell. */ 107 uint32_t doorbell_qpn; /**< qp number to write to the doorbell. */ 108 }; 109 110 #define mlx4_get_send_wqe(sq, n) ((sq)->buf + ((n) * (MLX4_TXBB_SIZE))) 111 112 /* Completion queue events, numbers and masks. */ 113 #define MLX4_CQ_DB_GEQ_N_MASK 0x3 114 #define MLX4_CQ_DOORBELL 0x20 115 #define MLX4_CQ_DB_CI_MASK 0xffffff 116 117 /* Completion queue information. */ 118 struct mlx4_cq { 119 volatile void *cq_uar; /**< CQ user access region. */ 120 volatile void *cq_db_reg; /**< CQ doorbell register. */ 121 volatile uint32_t *set_ci_db; /**< Pointer to the CQ doorbell. */ 122 volatile uint32_t *arm_db; /**< Arming Rx events doorbell. */ 123 volatile uint8_t *buf; /**< Pointer to the completion queue buffer. */ 124 uint32_t cqe_cnt; /**< Number of entries in the queue. */ 125 uint32_t cqe_64:1; /**< CQ entry size is 64 bytes. */ 126 uint32_t cons_index; /**< Last queue entry that was handled. */ 127 uint32_t cqn; /**< CQ number. */ 128 int arm_sn; /**< Rx event counter. */ 129 }; 130 131 /** 132 * Retrieve a CQE entry from a CQ. 133 * 134 * cqe = cq->buf + cons_index * cqe_size + cqe_offset 135 * 136 * Where cqe_size is 32 or 64 bytes and cqe_offset is 0 or 32 (depending on 137 * cqe_size). 138 * 139 * @param cq 140 * CQ to retrieve entry from. 141 * @param index 142 * Entry index. 143 * 144 * @return 145 * Pointer to CQE entry. 146 */ 147 static inline volatile struct mlx4_cqe * 148 mlx4_get_cqe(struct mlx4_cq *cq, uint32_t index) 149 { 150 return (volatile struct mlx4_cqe *)(cq->buf + 151 ((index & (cq->cqe_cnt - 1)) << 152 (5 + cq->cqe_64)) + 153 (cq->cqe_64 << 5)); 154 } 155 156 /** 157 * Transpose a flag in a value. 158 * 159 * @param val 160 * Input value. 161 * @param from 162 * Flag to retrieve from input value. 163 * @param to 164 * Flag to set in output value. 165 * 166 * @return 167 * Output value with transposed flag enabled if present on input. 168 */ 169 static inline uint64_t 170 mlx4_transpose(uint64_t val, uint64_t from, uint64_t to) 171 { 172 return (from >= to ? 173 (val & from) / (from / to) : 174 (val & from) * (to / from)); 175 } 176 177 #endif /* MLX4_PRM_H_ */ 178