1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2012 6WIND S.A. 3 * Copyright 2012 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX4_H_ 7 #define RTE_PMD_MLX4_H_ 8 9 #include <net/if.h> 10 #include <stdint.h> 11 #include <sys/queue.h> 12 13 /* Verbs headers do not support -pedantic. */ 14 #ifdef PEDANTIC 15 #pragma GCC diagnostic ignored "-Wpedantic" 16 #endif 17 #include <infiniband/verbs.h> 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic error "-Wpedantic" 20 #endif 21 22 #include <rte_ethdev_driver.h> 23 #include <rte_ether.h> 24 #include <rte_interrupts.h> 25 #include <rte_mempool.h> 26 #include <rte_rwlock.h> 27 28 #include "mlx4_mr.h" 29 30 #ifndef IBV_RX_HASH_INNER 31 /** This is not necessarily defined by supported RDMA core versions. */ 32 #define IBV_RX_HASH_INNER (1ull << 31) 33 #endif /* IBV_RX_HASH_INNER */ 34 35 /** Maximum number of simultaneous MAC addresses. This value is arbitrary. */ 36 #define MLX4_MAX_MAC_ADDRESSES 128 37 38 /** Request send completion once in every 64 sends, might be less. */ 39 #define MLX4_PMD_TX_PER_COMP_REQ 64 40 41 /** Maximum size for inline data. */ 42 #define MLX4_PMD_MAX_INLINE 0 43 44 /** Fixed RSS hash key size in bytes. Cannot be modified. */ 45 #define MLX4_RSS_HASH_KEY_SIZE 40 46 47 /** Interrupt alarm timeout value in microseconds. */ 48 #define MLX4_INTR_ALARM_TIMEOUT 100000 49 50 /* Maximum packet headers size (L2+L3+L4) for TSO. */ 51 #define MLX4_MAX_TSO_HEADER 192 52 53 /** Port parameter. */ 54 #define MLX4_PMD_PORT_KVARG "port" 55 56 enum { 57 PCI_VENDOR_ID_MELLANOX = 0x15b3, 58 }; 59 60 enum { 61 PCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003, 62 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004, 63 PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007, 64 }; 65 66 /** Driver name reported to lower layers and used in log output. */ 67 #define MLX4_DRIVER_NAME "net_mlx4" 68 69 struct mlx4_drop; 70 struct mlx4_rss; 71 struct rxq; 72 struct txq; 73 struct rte_flow; 74 75 LIST_HEAD(mlx4_dev_list, mlx4_priv); 76 LIST_HEAD(mlx4_mr_list, mlx4_mr); 77 78 /** Private data structure. */ 79 struct mlx4_priv { 80 LIST_ENTRY(mlx4_priv) mem_event_cb; 81 /**< Called by memory event callback. */ 82 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 83 struct ibv_context *ctx; /**< Verbs context. */ 84 struct ibv_device_attr device_attr; /**< Device properties. */ 85 struct ibv_pd *pd; /**< Protection Domain. */ 86 /* Device properties. */ 87 uint16_t mtu; /**< Configured MTU. */ 88 uint8_t port; /**< Physical port number. */ 89 uint32_t started:1; /**< Device started, flows enabled. */ 90 uint32_t vf:1; /**< This is a VF device. */ 91 uint32_t intr_alarm:1; /**< An interrupt alarm is scheduled. */ 92 uint32_t isolated:1; /**< Toggle isolated mode. */ 93 uint32_t rss_init:1; /**< Common RSS context is initialized. */ 94 uint32_t hw_csum:1; /**< Checksum offload is supported. */ 95 uint32_t hw_csum_l2tun:1; /**< Checksum support for L2 tunnels. */ 96 uint32_t hw_fcs_strip:1; /**< FCS stripping toggling is supported. */ 97 uint32_t tso:1; /**< Transmit segmentation offload is supported. */ 98 uint32_t tso_max_payload_sz; /**< Max supported TSO payload size. */ 99 uint32_t hw_rss_max_qps; /**< Max Rx Queues supported by RSS. */ 100 uint64_t hw_rss_sup; /**< Supported RSS hash fields (Verbs format). */ 101 struct rte_intr_handle intr_handle; /**< Port interrupt handle. */ 102 struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */ 103 struct { 104 uint32_t dev_gen; /* Generation number to flush local caches. */ 105 rte_rwlock_t rwlock; /* MR Lock. */ 106 struct mlx4_mr_btree cache; /* Global MR cache table. */ 107 struct mlx4_mr_list mr_list; /* Registered MR list. */ 108 struct mlx4_mr_list mr_free_list; /* Freed MR list. */ 109 } mr; 110 LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */ 111 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */ 112 struct ether_addr mac[MLX4_MAX_MAC_ADDRESSES]; 113 /**< Configured MAC addresses. Unused entries are zeroed. */ 114 }; 115 116 #define PORT_ID(priv) ((priv)->dev_data->port_id) 117 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 118 119 /* mlx4_ethdev.c */ 120 121 int mlx4_get_ifname(const struct mlx4_priv *priv, char (*ifname)[IF_NAMESIZE]); 122 int mlx4_get_mac(struct mlx4_priv *priv, uint8_t (*mac)[ETHER_ADDR_LEN]); 123 int mlx4_mtu_get(struct mlx4_priv *priv, uint16_t *mtu); 124 int mlx4_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 125 int mlx4_dev_set_link_down(struct rte_eth_dev *dev); 126 int mlx4_dev_set_link_up(struct rte_eth_dev *dev); 127 void mlx4_promiscuous_enable(struct rte_eth_dev *dev); 128 void mlx4_promiscuous_disable(struct rte_eth_dev *dev); 129 void mlx4_allmulticast_enable(struct rte_eth_dev *dev); 130 void mlx4_allmulticast_disable(struct rte_eth_dev *dev); 131 void mlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 132 int mlx4_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 133 uint32_t index, uint32_t vmdq); 134 int mlx4_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr); 135 int mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 136 int mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 137 void mlx4_stats_reset(struct rte_eth_dev *dev); 138 void mlx4_dev_infos_get(struct rte_eth_dev *dev, 139 struct rte_eth_dev_info *info); 140 int mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete); 141 int mlx4_flow_ctrl_get(struct rte_eth_dev *dev, 142 struct rte_eth_fc_conf *fc_conf); 143 int mlx4_flow_ctrl_set(struct rte_eth_dev *dev, 144 struct rte_eth_fc_conf *fc_conf); 145 const uint32_t *mlx4_dev_supported_ptypes_get(struct rte_eth_dev *dev); 146 int mlx4_is_removed(struct rte_eth_dev *dev); 147 148 /* mlx4_intr.c */ 149 150 int mlx4_intr_uninstall(struct mlx4_priv *priv); 151 int mlx4_intr_install(struct mlx4_priv *priv); 152 int mlx4_rxq_intr_enable(struct mlx4_priv *priv); 153 void mlx4_rxq_intr_disable(struct mlx4_priv *priv); 154 int mlx4_rx_intr_disable(struct rte_eth_dev *dev, uint16_t idx); 155 int mlx4_rx_intr_enable(struct rte_eth_dev *dev, uint16_t idx); 156 157 #endif /* RTE_PMD_MLX4_H_ */ 158