1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2015 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _IXGBE_REGS_H_ 34 #define _IXGBE_REGS_H_ 35 36 #include "ixgbe_ethdev.h" 37 38 struct ixgbe_hw; 39 struct reg_info { 40 uint32_t base_addr; 41 uint32_t count; 42 uint32_t stride; 43 const char *name; 44 }; 45 46 static const struct reg_info ixgbe_regs_general[] = { 47 {IXGBE_CTRL, 1, 1, "IXGBE_CTRL"}, 48 {IXGBE_STATUS, 1, 1, "IXGBE_STATUS"}, 49 {IXGBE_CTRL_EXT, 1, 1, "IXGBE_CTRL_EXT"}, 50 {IXGBE_ESDP, 1, 1, "IXGBE_ESDP"}, 51 {IXGBE_EODSDP, 1, 1, "IXGBE_EODSDP"}, 52 {IXGBE_LEDCTL, 1, 1, "IXGBE_LEDCTL"}, 53 {IXGBE_FRTIMER, 1, 1, "IXGBE_FRTIMER"}, 54 {IXGBE_TCPTIMER, 1, 1, "IXGBE_TCPTIMER"}, 55 {0, 0, 0, ""} 56 }; 57 58 static const struct reg_info ixgbevf_regs_general[] = { 59 {IXGBE_VFCTRL, 1, 1, "IXGBE_VFCTRL"}, 60 {IXGBE_VFSTATUS, 1, 1, "IXGBE_VFSTATUS"}, 61 {IXGBE_VFLINKS, 1, 1, "IXGBE_VFLINKS"}, 62 {IXGBE_VFFRTIMER, 1, 1, "IXGBE_VFFRTIMER"}, 63 {IXGBE_VFMAILBOX, 1, 1, "IXGBE_VFMAILBOX"}, 64 {IXGBE_VFMBMEM, 16, 4, "IXGBE_VFMBMEM"}, 65 {IXGBE_VFRXMEMWRAP, 1, 1, "IXGBE_VFRXMEMWRAP"}, 66 {0, 0, 0, ""} 67 }; 68 69 static const struct reg_info ixgbe_regs_nvm[] = { 70 {IXGBE_EEC, 1, 1, "IXGBE_EEC"}, 71 {IXGBE_EERD, 1, 1, "IXGBE_EERD"}, 72 {IXGBE_FLA, 1, 1, "IXGBE_FLA"}, 73 {IXGBE_EEMNGCTL, 1, 1, "IXGBE_EEMNGCTL"}, 74 {IXGBE_EEMNGDATA, 1, 1, "IXGBE_EEMNGDATA"}, 75 {IXGBE_FLMNGCTL, 1, 1, "IXGBE_FLMNGCTL"}, 76 {IXGBE_FLMNGDATA, 1, 1, "IXGBE_FLMNGDATA"}, 77 {IXGBE_FLMNGCNT, 1, 1, "IXGBE_FLMNGCNT"}, 78 {IXGBE_FLOP, 1, 1, "IXGBE_FLOP"}, 79 {IXGBE_GRC, 1, 1, "IXGBE_GRC"}, 80 {0, 0, 0, ""} 81 }; 82 83 static const struct reg_info ixgbe_regs_interrupt[] = { 84 {IXGBE_EICS, 1, 1, "IXGBE_EICS"}, 85 {IXGBE_EIMS, 1, 1, "IXGBE_EIMS"}, 86 {IXGBE_EIMC, 1, 1, "IXGBE_EIMC"}, 87 {IXGBE_EIAC, 1, 1, "IXGBE_EIAC"}, 88 {IXGBE_EIAM, 1, 1, "IXGBE_EIAM"}, 89 {IXGBE_EITR(0), 24, 4, "IXGBE_EITR"}, 90 {IXGBE_IVAR(0), 24, 4, "IXGBE_IVAR"}, 91 {IXGBE_MSIXT, 1, 1, "IXGBE_MSIXT"}, 92 {IXGBE_MSIXPBA, 1, 1, "IXGBE_MSIXPBA"}, 93 {IXGBE_PBACL(0), 1, 4, "IXGBE_PBACL"}, 94 {IXGBE_GPIE, 1, 1, ""}, 95 {0, 0, 0, ""} 96 }; 97 98 static const struct reg_info ixgbevf_regs_interrupt[] = { 99 {IXGBE_VTEICR, 1, 1, "IXGBE_VTEICR"}, 100 {IXGBE_VTEICS, 1, 1, "IXGBE_VTEICS"}, 101 {IXGBE_VTEIMS, 1, 1, "IXGBE_VTEIMS"}, 102 {IXGBE_VTEIMC, 1, 1, "IXGBE_VTEIMC"}, 103 {IXGBE_VTEIAM, 1, 1, "IXGBE_VTEIAM"}, 104 {IXGBE_VTEITR(0), 2, 4, "IXGBE_VTEITR"}, 105 {IXGBE_VTIVAR(0), 4, 4, "IXGBE_VTIVAR"}, 106 {IXGBE_VTIVAR_MISC, 1, 1, "IXGBE_VTIVAR_MISC"}, 107 {IXGBE_VTRSCINT(0), 2, 4, "IXGBE_VTRSCINT"}, 108 {0, 0, 0, ""} 109 }; 110 111 static const struct reg_info ixgbe_regs_fctl_mac_82598EB[] = { 112 {IXGBE_PFCTOP, 1, 1, ""}, 113 {IXGBE_FCTTV(0), 4, 4, ""}, 114 {IXGBE_FCRTV, 1, 1, ""}, 115 {IXGBE_TFCS, 1, 1, ""}, 116 {IXGBE_FCRTL(0), 8, 8, "IXGBE_FCRTL"}, 117 {IXGBE_FCRTH(0), 8, 8, "IXGBE_FCRTH"}, 118 {0, 0, 0, ""} 119 }; 120 121 static const struct reg_info ixgbe_regs_fctl_others[] = { 122 {IXGBE_PFCTOP, 1, 1, ""}, 123 {IXGBE_FCTTV(0), 4, 4, ""}, 124 {IXGBE_FCRTV, 1, 1, ""}, 125 {IXGBE_TFCS, 1, 1, ""}, 126 {IXGBE_FCRTL_82599(0), 8, 4, "IXGBE_FCRTL"}, 127 {IXGBE_FCRTH_82599(0), 8, 4, "IXGBE_FCRTH"}, 128 {0, 0, 0, ""} 129 }; 130 131 static const struct reg_info ixgbe_regs_rxdma[] = { 132 {IXGBE_RDBAL(0), 64, 0x40, "IXGBE_RDBAL"}, 133 {IXGBE_RDBAH(0), 64, 0x40, "IXGBE_RDBAH"}, 134 {IXGBE_RDLEN(0), 64, 0x40, "IXGBE_RDLEN"}, 135 {IXGBE_RDH(0), 64, 0x40, "IXGBE_RDH"}, 136 {IXGBE_RDT(0), 64, 0x40, "IXGBE_RDT"}, 137 {IXGBE_RXDCTL(0), 64, 0x40, "IXGBE_RXDCTL"}, 138 {IXGBE_SRRCTL(0), 16, 0x4, "IXGBE_SRRCTL"}, 139 {IXGBE_DCA_RXCTRL(0), 16, 4, "IXGBE_DCA_RXCTRL"}, 140 {IXGBE_RDRXCTL, 1, 1, "IXGBE_RDRXCTL"}, 141 {IXGBE_RXPBSIZE(0), 8, 4, "IXGBE_RXPBSIZE"}, 142 {IXGBE_RXCTRL, 1, 1, "IXGBE_RXCTRL"}, 143 {IXGBE_DROPEN, 1, 1, "IXGBE_DROPEN"}, 144 {0, 0, 0, ""} 145 }; 146 147 static const struct reg_info ixgbevf_regs_rxdma[] = { 148 {IXGBE_VFRDBAL(0), 8, 0x40, "IXGBE_VFRDBAL"}, 149 {IXGBE_VFRDBAH(0), 8, 0x40, "IXGBE_VFRDBAH"}, 150 {IXGBE_VFRDLEN(0), 8, 0x40, "IXGBE_VFRDLEN"}, 151 {IXGBE_VFRDH(0), 8, 0x40, "IXGBE_VFRDH"}, 152 {IXGBE_VFRDT(0), 8, 0x40, "IXGBE_VFRDT"}, 153 {IXGBE_VFRXDCTL(0), 8, 0x40, "IXGBE_VFRXDCTL"}, 154 {IXGBE_VFSRRCTL(0), 8, 0x40, "IXGBE_VFSRRCTL"}, 155 {IXGBE_VFPSRTYPE, 1, 1, "IXGBE_VFPSRTYPE"}, 156 {IXGBE_VFRSCCTL(0), 8, 0x40, "IXGBE_VFRSCCTL"}, 157 {IXGBE_VFDCA_RXCTRL(0), 8, 0x40, "IXGBE_VFDCA_RXCTRL"}, 158 {IXGBE_VFDCA_TXCTRL(0), 8, 0x40, "IXGBE_VFDCA_TXCTRL"}, 159 {0, 0, 0, ""} 160 }; 161 162 static const struct reg_info ixgbe_regs_rx[] = { 163 {IXGBE_RXCSUM, 1, 1, "IXGBE_RXCSUM"}, 164 {IXGBE_RFCTL, 1, 1, "IXGBE_RFCTL"}, 165 {IXGBE_RAL(0), 16, 8, "IXGBE_RAL"}, 166 {IXGBE_RAH(0), 16, 8, "IXGBE_RAH"}, 167 {IXGBE_PSRTYPE(0), 1, 4, "IXGBE_PSRTYPE"}, 168 {IXGBE_FCTRL, 1, 1, "IXGBE_FCTRL"}, 169 {IXGBE_VLNCTRL, 1, 1, "IXGBE_VLNCTRL"}, 170 {IXGBE_MCSTCTRL, 1, 1, "IXGBE_MCSTCTRL"}, 171 {IXGBE_MRQC, 1, 1, "IXGBE_MRQC"}, 172 {IXGBE_VMD_CTL, 1, 1, "IXGBE_VMD_CTL"}, 173 {IXGBE_IMIR(0), 8, 4, "IXGBE_IMIR"}, 174 {IXGBE_IMIREXT(0), 8, 4, "IXGBE_IMIREXT"}, 175 {IXGBE_IMIRVP, 1, 1, "IXGBE_IMIRVP"}, 176 {0, 0, 0, ""} 177 }; 178 179 static struct reg_info ixgbe_regs_tx[] = { 180 {IXGBE_TDBAL(0), 32, 0x40, "IXGBE_TDBAL"}, 181 {IXGBE_TDBAH(0), 32, 0x40, "IXGBE_TDBAH"}, 182 {IXGBE_TDLEN(0), 32, 0x40, "IXGBE_TDLEN"}, 183 {IXGBE_TDH(0), 32, 0x40, "IXGBE_TDH"}, 184 {IXGBE_TDT(0), 32, 0x40, "IXGBE_TDT"}, 185 {IXGBE_TXDCTL(0), 32, 0x40, "IXGBE_TXDCTL"}, 186 {IXGBE_TDWBAL(0), 32, 0x40, "IXGBE_TDWBAL"}, 187 {IXGBE_TDWBAH(0), 32, 0x40, "IXGBE_TDWBAH"}, 188 {IXGBE_DTXCTL, 1, 1, "IXGBE_DTXCTL"}, 189 {IXGBE_DCA_TXCTRL(0), 16, 4, "IXGBE_DCA_TXCTRL"}, 190 {IXGBE_TXPBSIZE(0), 8, 4, "IXGBE_TXPBSIZE"}, 191 {IXGBE_MNGTXMAP, 1, 1, "IXGBE_MNGTXMAP"}, 192 {0, 0, 0, ""} 193 }; 194 195 static const struct reg_info ixgbevf_regs_tx[] = { 196 {IXGBE_VFTDBAL(0), 4, 0x40, "IXGBE_VFTDBAL"}, 197 {IXGBE_VFTDBAH(0), 4, 0x40, "IXGBE_VFTDBAH"}, 198 {IXGBE_VFTDLEN(0), 4, 0x40, "IXGBE_VFTDLEN"}, 199 {IXGBE_VFTDH(0), 4, 0x40, "IXGBE_VFTDH"}, 200 {IXGBE_VFTDT(0), 4, 0x40, "IXGBE_VFTDT"}, 201 {IXGBE_VFTXDCTL(0), 4, 0x40, "IXGBE_VFTXDCTL"}, 202 {IXGBE_VFTDWBAL(0), 4, 0x40, "IXGBE_VFTDWBAL"}, 203 {IXGBE_VFTDWBAH(0), 4, 0x40, "IXGBE_VFTDWBAH"}, 204 {0, 0, 0, ""} 205 }; 206 207 static const struct reg_info ixgbe_regs_wakeup[] = { 208 {IXGBE_WUC, 1, 1, "IXGBE_WUC"}, 209 {IXGBE_WUFC, 1, 1, "IXGBE_WUFC"}, 210 {IXGBE_WUS, 1, 1, "IXGBE_WUS"}, 211 {IXGBE_IPAV, 1, 1, "IXGBE_IPAV"}, 212 {IXGBE_IP4AT, 1, 1, "IXGBE_IP4AT"}, 213 {IXGBE_IP6AT, 1, 1, "IXGBE_IP6AT"}, 214 {IXGBE_WUPL, 1, 1, "IXGBE_WUPL"}, 215 {IXGBE_WUPM, 1, 1, "IXGBE_WUPM"}, 216 {IXGBE_FHFT(0), 1, 1, "IXGBE_FHFT"}, 217 {0, 0, 0, ""} 218 }; 219 220 static const struct reg_info ixgbe_regs_dcb[] = { 221 {IXGBE_RMCS, 1, 1, "IXGBE_RMCS"}, 222 {IXGBE_DPMCS, 1, 1, "IXGBE_DPMCS"}, 223 {IXGBE_PDPMCS, 1, 1, "IXGBE_PDPMCS"}, 224 {IXGBE_RUPPBMR, 1, 1, "IXGBE_RUPPBMR"}, 225 {IXGBE_RT2CR(0), 8, 4, "IXGBE_RT2CR"}, 226 {IXGBE_RT2SR(0), 8, 4, "IXGBE_RT2SR"}, 227 {IXGBE_TDTQ2TCCR(0), 8, 0x40, "IXGBE_TDTQ2TCCR"}, 228 {IXGBE_TDTQ2TCSR(0), 8, 0x40, "IXGBE_TDTQ2TCSR"}, 229 {IXGBE_TDPT2TCCR(0), 8, 4, "IXGBE_TDPT2TCCR"}, 230 {IXGBE_TDPT2TCSR(0), 8, 4, "IXGBE_TDPT2TCSR"}, 231 {0, 0, 0, ""} 232 }; 233 234 static const struct reg_info ixgbe_regs_mac[] = { 235 {IXGBE_PCS1GCFIG, 1, 1, "IXGBE_PCS1GCFIG"}, 236 {IXGBE_PCS1GLCTL, 1, 1, "IXGBE_PCS1GLCTL"}, 237 {IXGBE_PCS1GLSTA, 1, 1, "IXGBE_PCS1GLSTA"}, 238 {IXGBE_PCS1GDBG0, 1, 1, "IXGBE_PCS1GDBG0"}, 239 {IXGBE_PCS1GDBG1, 1, 1, "IXGBE_PCS1GDBG1"}, 240 {IXGBE_PCS1GANA, 1, 1, "IXGBE_PCS1GANA"}, 241 {IXGBE_PCS1GANLP, 1, 1, "IXGBE_PCS1GANLP"}, 242 {IXGBE_PCS1GANNP, 1, 1, "IXGBE_PCS1GANNP"}, 243 {IXGBE_PCS1GANLPNP, 1, 1, "IXGBE_PCS1GANLPNP"}, 244 {IXGBE_HLREG0, 1, 1, "IXGBE_HLREG0"}, 245 {IXGBE_HLREG1, 1, 1, "IXGBE_HLREG1"}, 246 {IXGBE_PAP, 1, 1, "IXGBE_PAP"}, 247 {IXGBE_MACA, 1, 1, "IXGBE_MACA"}, 248 {IXGBE_APAE, 1, 1, "IXGBE_APAE"}, 249 {IXGBE_ARD, 1, 1, "IXGBE_ARD"}, 250 {IXGBE_AIS, 1, 1, "IXGBE_AIS"}, 251 {IXGBE_MSCA, 1, 1, "IXGBE_MSCA"}, 252 {IXGBE_MSRWD, 1, 1, "IXGBE_MSRWD"}, 253 {IXGBE_MLADD, 1, 1, "IXGBE_MLADD"}, 254 {IXGBE_MHADD, 1, 1, "IXGBE_MHADD"}, 255 {IXGBE_TREG, 1, 1, "IXGBE_TREG"}, 256 {IXGBE_PCSS1, 1, 1, "IXGBE_PCSS1"}, 257 {IXGBE_PCSS2, 1, 1, "IXGBE_PCSS2"}, 258 {IXGBE_XPCSS, 1, 1, "IXGBE_XPCSS"}, 259 {IXGBE_SERDESC, 1, 1, "IXGBE_SERDESC"}, 260 {IXGBE_MACS, 1, 1, "IXGBE_MACS"}, 261 {IXGBE_AUTOC, 1, 1, "IXGBE_AUTOC"}, 262 {IXGBE_LINKS, 1, 1, "IXGBE_LINKS"}, 263 {IXGBE_AUTOC2, 1, 1, "IXGBE_AUTOC2"}, 264 {IXGBE_AUTOC3, 1, 1, "IXGBE_AUTOC3"}, 265 {IXGBE_ANLP1, 1, 1, "IXGBE_ANLP1"}, 266 {IXGBE_ANLP2, 1, 1, "IXGBE_ANLP2"}, 267 {IXGBE_ATLASCTL, 1, 1, "IXGBE_ATLASCTL"}, 268 {0, 0, 0, ""} 269 }; 270 271 static const struct reg_info ixgbe_regs_diagnostic[] = { 272 {IXGBE_RDSTATCTL, 1, 1, "IXGBE_RDSTATCTL"}, 273 {IXGBE_RDSTAT(0), 8, 4, "IXGBE_RDSTAT"}, 274 {IXGBE_RDHMPN, 1, 1, "IXGBE_RDHMPN"}, 275 {IXGBE_RIC_DW(0), 4, 4, "IXGBE_RIC_DW"}, 276 {IXGBE_RDPROBE, 1, 1, "IXGBE_RDPROBE"}, 277 {IXGBE_TDHMPN, 1, 1, "IXGBE_TDHMPN"}, 278 {IXGBE_TIC_DW(0), 4, 4, "IXGBE_TIC_DW"}, 279 {IXGBE_TDPROBE, 1, 1, "IXGBE_TDPROBE"}, 280 {IXGBE_TXBUFCTRL, 1, 1, "IXGBE_TXBUFCTRL"}, 281 {IXGBE_TXBUFDATA0, 1, 1, "IXGBE_TXBUFDATA0"}, 282 {IXGBE_TXBUFDATA1, 1, 1, "IXGBE_TXBUFDATA1"}, 283 {IXGBE_TXBUFDATA2, 1, 1, "IXGBE_TXBUFDATA2"}, 284 {IXGBE_TXBUFDATA3, 1, 1, "IXGBE_TXBUFDATA3"}, 285 {IXGBE_RXBUFCTRL, 1, 1, "IXGBE_RXBUFCTRL"}, 286 {IXGBE_RXBUFDATA0, 1, 1, "IXGBE_RXBUFDATA0"}, 287 {IXGBE_RXBUFDATA1, 1, 1, "IXGBE_RXBUFDATA1"}, 288 {IXGBE_RXBUFDATA2, 1, 1, "IXGBE_RXBUFDATA2"}, 289 {IXGBE_RXBUFDATA3, 1, 1, "IXGBE_RXBUFDATA3"}, 290 {IXGBE_PCIE_DIAG(0), 8, 4, ""}, 291 {IXGBE_RFVAL, 1, 1, "IXGBE_RFVAL"}, 292 {IXGBE_MDFTC1, 1, 1, "IXGBE_MDFTC1"}, 293 {IXGBE_MDFTC2, 1, 1, "IXGBE_MDFTC2"}, 294 {IXGBE_MDFTFIFO1, 1, 1, "IXGBE_MDFTFIFO1"}, 295 {IXGBE_MDFTFIFO2, 1, 1, "IXGBE_MDFTFIFO2"}, 296 {IXGBE_MDFTS, 1, 1, "IXGBE_MDFTS"}, 297 {IXGBE_PCIEECCCTL, 1, 1, "IXGBE_PCIEECCCTL"}, 298 {IXGBE_PBTXECC, 1, 1, "IXGBE_PBTXECC"}, 299 {IXGBE_PBRXECC, 1, 1, "IXGBE_PBRXECC"}, 300 {IXGBE_MFLCN, 1, 1, "IXGBE_MFLCN"}, 301 {0, 0, 0, ""}, 302 }; 303 304 /* PF registers */ 305 static const struct reg_info *ixgbe_regs_others[] = { 306 ixgbe_regs_general, 307 ixgbe_regs_nvm, ixgbe_regs_interrupt, 308 ixgbe_regs_fctl_others, 309 ixgbe_regs_rxdma, 310 ixgbe_regs_rx, 311 ixgbe_regs_tx, 312 ixgbe_regs_wakeup, 313 ixgbe_regs_dcb, 314 ixgbe_regs_mac, 315 ixgbe_regs_diagnostic, 316 NULL}; 317 318 static const struct reg_info *ixgbe_regs_mac_82598EB[] = { 319 ixgbe_regs_general, 320 ixgbe_regs_nvm, 321 ixgbe_regs_interrupt, 322 ixgbe_regs_fctl_mac_82598EB, 323 ixgbe_regs_rxdma, 324 ixgbe_regs_rx, 325 ixgbe_regs_tx, 326 ixgbe_regs_wakeup, 327 ixgbe_regs_dcb, 328 ixgbe_regs_mac, 329 ixgbe_regs_diagnostic, 330 NULL}; 331 332 /* VF registers */ 333 static const struct reg_info *ixgbevf_regs[] = { 334 ixgbevf_regs_general, 335 ixgbevf_regs_interrupt, 336 ixgbevf_regs_rxdma, 337 ixgbevf_regs_tx, 338 NULL}; 339 340 static inline int 341 ixgbe_read_regs(struct ixgbe_hw *hw, const struct reg_info *reg, 342 uint32_t *reg_buf) 343 { 344 unsigned int i; 345 346 for (i = 0; i < reg->count; i++) 347 reg_buf[i] = IXGBE_READ_REG(hw, 348 reg->base_addr + i * reg->stride); 349 return reg->count; 350 }; 351 352 static inline int 353 ixgbe_regs_group_count(const struct reg_info *regs) 354 { 355 int count = 0; 356 int i = 0; 357 358 while (regs[i].count) 359 count += regs[i++].count; 360 return count; 361 }; 362 363 static inline int 364 ixgbe_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf, 365 const struct reg_info *regs) 366 { 367 int count = 0; 368 int i = 0; 369 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 370 371 while (regs[i].count) 372 count += ixgbe_read_regs(hw, ®s[i++], ®_buf[count]); 373 return count; 374 }; 375 376 #endif /* _IXGBE_REGS_H_ */ 377