1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2016 Intel Corporation 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <stdlib.h> 9 #include <unistd.h> 10 #include <stdarg.h> 11 #include <inttypes.h> 12 13 #include <rte_interrupts.h> 14 #include <rte_log.h> 15 #include <rte_debug.h> 16 #include <rte_eal.h> 17 #include <rte_ether.h> 18 #include <rte_ethdev_driver.h> 19 #include <rte_memcpy.h> 20 #include <rte_malloc.h> 21 #include <rte_random.h> 22 23 #include "base/ixgbe_common.h" 24 #include "ixgbe_ethdev.h" 25 #include "rte_pmd_ixgbe.h" 26 27 #define IXGBE_MAX_VFTA (128) 28 #define IXGBE_VF_MSG_SIZE_DEFAULT 1 29 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5 30 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808 31 32 static inline uint16_t 33 dev_num_vf(struct rte_eth_dev *eth_dev) 34 { 35 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 36 37 return pci_dev->max_vfs; 38 } 39 40 static inline 41 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num) 42 { 43 unsigned char vf_mac_addr[ETHER_ADDR_LEN]; 44 struct ixgbe_vf_info *vfinfo = 45 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 46 uint16_t vfn; 47 48 for (vfn = 0; vfn < vf_num; vfn++) { 49 eth_random_addr(vf_mac_addr); 50 /* keep the random address as default */ 51 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr, 52 ETHER_ADDR_LEN); 53 } 54 55 return 0; 56 } 57 58 static inline int 59 ixgbe_mb_intr_setup(struct rte_eth_dev *dev) 60 { 61 struct ixgbe_interrupt *intr = 62 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 63 64 intr->mask |= IXGBE_EICR_MAILBOX; 65 66 return 0; 67 } 68 69 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev) 70 { 71 struct ixgbe_vf_info **vfinfo = 72 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private); 73 struct ixgbe_mirror_info *mirror_info = 74 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private); 75 struct ixgbe_uta_info *uta_info = 76 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private); 77 struct ixgbe_hw *hw = 78 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 79 uint16_t vf_num; 80 uint8_t nb_queue; 81 82 PMD_INIT_FUNC_TRACE(); 83 84 RTE_ETH_DEV_SRIOV(eth_dev).active = 0; 85 vf_num = dev_num_vf(eth_dev); 86 if (vf_num == 0) 87 return; 88 89 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0); 90 if (*vfinfo == NULL) 91 rte_panic("Cannot allocate memory for private VF data\n"); 92 93 rte_eth_switch_domain_alloc(&(*vfinfo)->switch_domain_id); 94 95 memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info)); 96 memset(uta_info, 0, sizeof(struct ixgbe_uta_info)); 97 hw->mac.mc_filter_type = 0; 98 99 if (vf_num >= ETH_32_POOLS) { 100 nb_queue = 2; 101 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS; 102 } else if (vf_num >= ETH_16_POOLS) { 103 nb_queue = 4; 104 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS; 105 } else { 106 nb_queue = 8; 107 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS; 108 } 109 110 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue; 111 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num; 112 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue); 113 114 ixgbe_vf_perm_addr_gen(eth_dev, vf_num); 115 116 /* init_mailbox_params */ 117 hw->mbx.ops.init_params(hw); 118 119 /* set mb interrupt mask */ 120 ixgbe_mb_intr_setup(eth_dev); 121 } 122 123 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev) 124 { 125 struct ixgbe_vf_info **vfinfo; 126 uint16_t vf_num; 127 int ret; 128 129 PMD_INIT_FUNC_TRACE(); 130 131 RTE_ETH_DEV_SRIOV(eth_dev).active = 0; 132 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0; 133 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0; 134 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0; 135 136 vf_num = dev_num_vf(eth_dev); 137 if (vf_num == 0) 138 return; 139 140 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private); 141 if (*vfinfo == NULL) 142 return; 143 144 ret = rte_eth_switch_domain_free((*vfinfo)->switch_domain_id); 145 if (ret) 146 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret); 147 148 rte_free(*vfinfo); 149 *vfinfo = NULL; 150 } 151 152 static void 153 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev) 154 { 155 struct ixgbe_hw *hw = 156 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 157 struct ixgbe_filter_info *filter_info = 158 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 159 uint16_t vf_num; 160 int i; 161 struct ixgbe_ethertype_filter ethertype_filter; 162 163 if (!hw->mac.ops.set_ethertype_anti_spoofing) { 164 RTE_LOG(INFO, PMD, "ether type anti-spoofing is not" 165 " supported.\n"); 166 return; 167 } 168 169 i = ixgbe_ethertype_filter_lookup(filter_info, 170 IXGBE_ETHERTYPE_FLOW_CTRL); 171 if (i >= 0) { 172 RTE_LOG(ERR, PMD, "A ether type filter" 173 " entity for flow control already exists!\n"); 174 return; 175 } 176 177 ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL; 178 ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN | 179 IXGBE_ETQF_TX_ANTISPOOF | 180 IXGBE_ETHERTYPE_FLOW_CTRL; 181 ethertype_filter.etqs = 0; 182 ethertype_filter.conf = TRUE; 183 i = ixgbe_ethertype_filter_insert(filter_info, 184 ðertype_filter); 185 if (i < 0) { 186 RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter" 187 " entity for flow control.\n"); 188 return; 189 } 190 191 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 192 (IXGBE_ETQF_FILTER_EN | 193 IXGBE_ETQF_TX_ANTISPOOF | 194 IXGBE_ETHERTYPE_FLOW_CTRL)); 195 196 vf_num = dev_num_vf(eth_dev); 197 for (i = 0; i < vf_num; i++) 198 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i); 199 } 200 201 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev) 202 { 203 uint32_t vtctl, fcrth; 204 uint32_t vfre_slot, vfre_offset; 205 uint16_t vf_num; 206 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ 207 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); 208 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 209 uint32_t gpie, gcr_ext; 210 uint32_t vlanctrl; 211 int i; 212 213 vf_num = dev_num_vf(eth_dev); 214 if (vf_num == 0) 215 return -1; 216 217 /* enable VMDq and set the default pool for PF */ 218 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 219 vtctl |= IXGBE_VMD_CTL_VMDQ_EN; 220 vtctl &= ~IXGBE_VT_CTL_POOL_MASK; 221 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx 222 << IXGBE_VT_CTL_POOL_SHIFT; 223 vtctl |= IXGBE_VT_CTL_REPLEN; 224 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl); 225 226 vfre_offset = vf_num & VFRE_MASK; 227 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0; 228 229 /* Enable pools reserved to PF only */ 230 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset); 231 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1); 232 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset); 233 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1); 234 235 /* PFDMA Tx General Switch Control Enables VMDQ loopback */ 236 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 237 238 /* clear VMDq map to perment rar 0 */ 239 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 240 241 /* clear VMDq map to scan rar 127 */ 242 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0); 243 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0); 244 245 /* set VMDq map to default PF pool */ 246 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx); 247 248 /* 249 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode 250 */ 251 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 252 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK; 253 254 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 255 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 256 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT; 257 258 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) { 259 case ETH_64_POOLS: 260 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; 261 gpie |= IXGBE_GPIE_VTMODE_64; 262 break; 263 case ETH_32_POOLS: 264 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32; 265 gpie |= IXGBE_GPIE_VTMODE_32; 266 break; 267 case ETH_16_POOLS: 268 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16; 269 gpie |= IXGBE_GPIE_VTMODE_16; 270 break; 271 } 272 273 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 274 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 275 276 /* 277 * enable vlan filtering and allow all vlan tags through 278 */ 279 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 280 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 281 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 282 283 /* VFTA - enable all vlan filters */ 284 for (i = 0; i < IXGBE_MAX_VFTA; i++) 285 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF); 286 287 /* Enable MAC Anti-Spoofing */ 288 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num); 289 290 /* set flow control threshold to max to avoid tx switch hang */ 291 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 292 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 293 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 294 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 295 } 296 297 ixgbe_add_tx_flow_control_drop_filter(eth_dev); 298 299 return 0; 300 } 301 302 static void 303 set_rx_mode(struct rte_eth_dev *dev) 304 { 305 struct rte_eth_dev_data *dev_data = dev->data; 306 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 307 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 308 uint16_t vfn = dev_num_vf(dev); 309 310 /* Check for Promiscuous and All Multicast modes */ 311 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 312 313 /* set all bits that we expect to always be set */ 314 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 315 fctrl |= IXGBE_FCTRL_BAM; 316 317 /* clear the bits we are changing the status of */ 318 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 319 320 if (dev_data->promiscuous) { 321 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 322 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); 323 } else { 324 if (dev_data->all_multicast) { 325 fctrl |= IXGBE_FCTRL_MPE; 326 vmolr |= IXGBE_VMOLR_MPE; 327 } else { 328 vmolr |= IXGBE_VMOLR_ROMPE; 329 } 330 } 331 332 if (hw->mac.type != ixgbe_mac_82598EB) { 333 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) & 334 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 335 IXGBE_VMOLR_ROPE); 336 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr); 337 } 338 339 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 340 341 ixgbe_vlan_hw_strip_config(dev); 342 } 343 344 static inline void 345 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf) 346 { 347 struct ixgbe_hw *hw = 348 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 349 struct ixgbe_vf_info *vfinfo = 350 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 351 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 352 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); 353 354 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE | 355 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 356 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); 357 358 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0); 359 360 /* reset multicast table array for vf */ 361 vfinfo[vf].num_vf_mc_hashes = 0; 362 363 /* reset rx mode */ 364 set_rx_mode(dev); 365 366 hw->mac.ops.clear_rar(hw, rar_entry); 367 } 368 369 static inline void 370 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf) 371 { 372 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 373 uint32_t reg; 374 uint32_t reg_offset, vf_shift; 375 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ 376 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); 377 uint8_t nb_q_per_pool; 378 int i; 379 380 vf_shift = vf & VFRE_MASK; 381 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0; 382 383 /* enable transmit for vf */ 384 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); 385 reg |= (reg | (1 << vf_shift)); 386 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); 387 388 /* enable all queue drop for IOV */ 389 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 390 for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) { 391 IXGBE_WRITE_FLUSH(hw); 392 reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE; 393 reg |= i << IXGBE_QDE_IDX_SHIFT; 394 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg); 395 } 396 397 /* enable receive for vf */ 398 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); 399 reg |= (reg | (1 << vf_shift)); 400 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); 401 402 /* Enable counting of spoofed packets in the SSVPC register */ 403 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset)); 404 reg |= (1 << vf_shift); 405 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); 406 407 ixgbe_vf_reset_event(dev, vf); 408 } 409 410 static int 411 ixgbe_enable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf) 412 { 413 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 414 uint32_t vmolr; 415 416 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); 417 418 RTE_LOG(INFO, PMD, "VF %u: enabling multicast promiscuous\n", vf); 419 420 vmolr |= IXGBE_VMOLR_MPE; 421 422 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); 423 424 return 0; 425 } 426 427 static int 428 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf) 429 { 430 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 431 uint32_t vmolr; 432 433 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); 434 435 RTE_LOG(INFO, PMD, "VF %u: disabling multicast promiscuous\n", vf); 436 437 vmolr &= ~IXGBE_VMOLR_MPE; 438 439 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); 440 441 return 0; 442 } 443 444 static int 445 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf) 446 { 447 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 448 struct ixgbe_vf_info *vfinfo = 449 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 450 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses; 451 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 452 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 453 454 ixgbe_vf_reset_msg(dev, vf); 455 456 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV); 457 458 /* Disable multicast promiscuous at reset */ 459 ixgbe_disable_vf_mc_promisc(dev, vf); 460 461 /* reply to reset with ack and vf mac address */ 462 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK; 463 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN); 464 /* 465 * Piggyback the multicast filter type so VF can compute the 466 * correct vectors 467 */ 468 msgbuf[3] = hw->mac.mc_filter_type; 469 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf); 470 471 return 0; 472 } 473 474 static int 475 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 476 { 477 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 478 struct ixgbe_vf_info *vfinfo = 479 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 480 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 481 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 482 483 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) { 484 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6); 485 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV); 486 } 487 return -1; 488 } 489 490 static int 491 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 492 { 493 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 494 struct ixgbe_vf_info *vfinfo = 495 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 496 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >> 497 IXGBE_VT_MSGINFO_SHIFT; 498 uint16_t *hash_list = (uint16_t *)&msgbuf[1]; 499 uint32_t mta_idx; 500 uint32_t mta_shift; 501 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F; 502 const uint32_t IXGBE_MTA_BIT_SHIFT = 5; 503 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1; 504 uint32_t reg_val; 505 int i; 506 507 /* Disable multicast promiscuous first */ 508 ixgbe_disable_vf_mc_promisc(dev, vf); 509 510 /* only so many hash values supported */ 511 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES); 512 513 /* store the mc entries */ 514 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries; 515 for (i = 0; i < nb_entries; i++) { 516 vfinfo->vf_mc_hashes[i] = hash_list[i]; 517 } 518 519 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) { 520 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT) 521 & IXGBE_MTA_INDEX_MASK; 522 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK; 523 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx)); 524 reg_val |= (1 << mta_shift); 525 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val); 526 } 527 528 return 0; 529 } 530 531 static int 532 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 533 { 534 int add, vid; 535 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 536 struct ixgbe_vf_info *vfinfo = 537 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 538 539 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) 540 >> IXGBE_VT_MSGINFO_SHIFT; 541 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK); 542 543 if (add) 544 vfinfo[vf].vlan_count++; 545 else if (vfinfo[vf].vlan_count) 546 vfinfo[vf].vlan_count--; 547 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false); 548 } 549 550 static int 551 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf) 552 { 553 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 554 uint32_t new_mtu = msgbuf[1]; 555 uint32_t max_frs; 556 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 557 558 /* X540 and X550 support jumbo frames in IOV mode */ 559 if (hw->mac.type != ixgbe_mac_X540 && 560 hw->mac.type != ixgbe_mac_X550 && 561 hw->mac.type != ixgbe_mac_X550EM_x && 562 hw->mac.type != ixgbe_mac_X550EM_a) 563 return -1; 564 565 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN)) 566 return -1; 567 568 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) & 569 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT; 570 if (max_frs < new_mtu) { 571 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT; 572 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs); 573 } 574 575 return 0; 576 } 577 578 static int 579 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 580 { 581 uint32_t api_version = msgbuf[1]; 582 struct ixgbe_vf_info *vfinfo = 583 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 584 585 switch (api_version) { 586 case ixgbe_mbox_api_10: 587 case ixgbe_mbox_api_11: 588 case ixgbe_mbox_api_12: 589 vfinfo[vf].api_version = (uint8_t)api_version; 590 return 0; 591 default: 592 break; 593 } 594 595 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n", 596 api_version, vf); 597 598 return -1; 599 } 600 601 static int 602 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 603 { 604 struct ixgbe_vf_info *vfinfo = 605 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 606 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 607 struct rte_eth_conf *eth_conf; 608 struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf; 609 u8 num_tcs; 610 struct ixgbe_hw *hw; 611 u32 vmvir; 612 #define IXGBE_VMVIR_VLANA_MASK 0xC0000000 613 #define IXGBE_VMVIR_VLAN_VID_MASK 0x00000FFF 614 #define IXGBE_VMVIR_VLAN_UP_MASK 0x0000E000 615 #define VLAN_PRIO_SHIFT 13 616 u32 vlana; 617 u32 vid; 618 u32 user_priority; 619 620 /* Verify if the PF supports the mbox APIs version or not */ 621 switch (vfinfo[vf].api_version) { 622 case ixgbe_mbox_api_20: 623 case ixgbe_mbox_api_11: 624 case ixgbe_mbox_api_12: 625 break; 626 default: 627 return -1; 628 } 629 630 /* Notify VF of Rx and Tx queue number */ 631 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 632 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 633 634 /* Notify VF of default queue */ 635 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q; 636 637 /* Notify VF of number of DCB traffic classes */ 638 eth_conf = &dev->data->dev_conf; 639 switch (eth_conf->txmode.mq_mode) { 640 case ETH_MQ_TX_NONE: 641 case ETH_MQ_TX_DCB: 642 RTE_LOG(ERR, PMD, "PF must work with virtualization for VF %u" 643 ", but its tx mode = %d\n", vf, 644 eth_conf->txmode.mq_mode); 645 return -1; 646 647 case ETH_MQ_TX_VMDQ_DCB: 648 vmdq_dcb_tx_conf = ð_conf->tx_adv_conf.vmdq_dcb_tx_conf; 649 switch (vmdq_dcb_tx_conf->nb_queue_pools) { 650 case ETH_16_POOLS: 651 num_tcs = ETH_8_TCS; 652 break; 653 case ETH_32_POOLS: 654 num_tcs = ETH_4_TCS; 655 break; 656 default: 657 return -1; 658 } 659 break; 660 661 /* ETH_MQ_TX_VMDQ_ONLY, DCB not enabled */ 662 case ETH_MQ_TX_VMDQ_ONLY: 663 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 664 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf)); 665 vlana = vmvir & IXGBE_VMVIR_VLANA_MASK; 666 vid = vmvir & IXGBE_VMVIR_VLAN_VID_MASK; 667 user_priority = 668 (vmvir & IXGBE_VMVIR_VLAN_UP_MASK) >> VLAN_PRIO_SHIFT; 669 if ((vlana == IXGBE_VMVIR_VLANA_DEFAULT) && 670 ((vid != 0) || (user_priority != 0))) 671 num_tcs = 1; 672 else 673 num_tcs = 0; 674 break; 675 676 default: 677 RTE_LOG(ERR, PMD, "PF work with invalid mode = %d\n", 678 eth_conf->txmode.mq_mode); 679 return -1; 680 } 681 msgbuf[IXGBE_VF_TRANS_VLAN] = num_tcs; 682 683 return 0; 684 } 685 686 static int 687 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 688 { 689 struct ixgbe_vf_info *vfinfo = 690 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 691 bool enable = !!msgbuf[1]; /* msgbuf contains the flag to enable */ 692 693 switch (vfinfo[vf].api_version) { 694 case ixgbe_mbox_api_12: 695 break; 696 default: 697 return -1; 698 } 699 700 if (enable) 701 return ixgbe_enable_vf_mc_promisc(dev, vf); 702 else 703 return ixgbe_disable_vf_mc_promisc(dev, vf); 704 } 705 706 static int 707 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf) 708 { 709 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE; 710 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT; 711 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE]; 712 int32_t retval; 713 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 714 struct ixgbe_vf_info *vfinfo = 715 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 716 struct rte_pmd_ixgbe_mb_event_param ret_param; 717 718 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf); 719 if (retval) { 720 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf); 721 return retval; 722 } 723 724 /* do nothing with the message already been processed */ 725 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK)) 726 return retval; 727 728 /* flush the ack before we write any messages back */ 729 IXGBE_WRITE_FLUSH(hw); 730 731 /** 732 * initialise structure to send to user application 733 * will return response from user in retval field 734 */ 735 ret_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED; 736 ret_param.vfid = vf; 737 ret_param.msg_type = msgbuf[0] & 0xFFFF; 738 ret_param.msg = (void *)msgbuf; 739 740 /* perform VF reset */ 741 if (msgbuf[0] == IXGBE_VF_RESET) { 742 int ret = ixgbe_vf_reset(dev, vf, msgbuf); 743 744 vfinfo[vf].clear_to_send = true; 745 746 /* notify application about VF reset */ 747 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, 748 &ret_param); 749 return ret; 750 } 751 752 /** 753 * ask user application if we allowed to perform those functions 754 * if we get ret_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED 755 * then business as usual, 756 * if 0, do nothing and send ACK to VF 757 * if ret_param.retval > 1, do nothing and send NAK to VF 758 */ 759 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, 760 &ret_param); 761 762 retval = ret_param.retval; 763 764 /* check & process VF to PF mailbox message */ 765 switch ((msgbuf[0] & 0xFFFF)) { 766 case IXGBE_VF_SET_MAC_ADDR: 767 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 768 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf); 769 break; 770 case IXGBE_VF_SET_MULTICAST: 771 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 772 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf); 773 break; 774 case IXGBE_VF_SET_LPE: 775 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 776 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf); 777 break; 778 case IXGBE_VF_SET_VLAN: 779 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 780 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf); 781 break; 782 case IXGBE_VF_API_NEGOTIATE: 783 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf); 784 break; 785 case IXGBE_VF_GET_QUEUES: 786 retval = ixgbe_get_vf_queues(dev, vf, msgbuf); 787 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE; 788 break; 789 case IXGBE_VF_UPDATE_XCAST_MODE: 790 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 791 retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf); 792 break; 793 default: 794 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]); 795 retval = IXGBE_ERR_MBX; 796 break; 797 } 798 799 /* response the VF according to the message process result */ 800 if (retval) 801 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK; 802 else 803 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK; 804 805 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS; 806 807 ixgbe_write_mbx(hw, msgbuf, msg_size, vf); 808 809 return retval; 810 } 811 812 static inline void 813 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf) 814 { 815 uint32_t msg = IXGBE_VT_MSGTYPE_NACK; 816 struct ixgbe_hw *hw = 817 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 818 struct ixgbe_vf_info *vfinfo = 819 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 820 821 if (!vfinfo[vf].clear_to_send) 822 ixgbe_write_mbx(hw, &msg, 1, vf); 823 } 824 825 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev) 826 { 827 uint16_t vf; 828 struct ixgbe_hw *hw = 829 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 830 831 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) { 832 /* check & process vf function level reset */ 833 if (!ixgbe_check_for_rst(hw, vf)) 834 ixgbe_vf_reset_event(eth_dev, vf); 835 836 /* check & process vf mailbox messages */ 837 if (!ixgbe_check_for_msg(hw, vf)) 838 ixgbe_rcv_msg_from_vf(eth_dev, vf); 839 840 /* check & process acks from vf */ 841 if (!ixgbe_check_for_ack(hw, vf)) 842 ixgbe_rcv_ack_from_vf(eth_dev, vf); 843 } 844 } 845