1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stdio.h> 35 #include <errno.h> 36 #include <stdint.h> 37 #include <stdlib.h> 38 #include <unistd.h> 39 #include <stdarg.h> 40 #include <inttypes.h> 41 42 #include <rte_interrupts.h> 43 #include <rte_log.h> 44 #include <rte_debug.h> 45 #include <rte_eal.h> 46 #include <rte_ether.h> 47 #include <rte_ethdev.h> 48 #include <rte_memcpy.h> 49 #include <rte_malloc.h> 50 #include <rte_random.h> 51 52 #include "base/ixgbe_common.h" 53 #include "ixgbe_ethdev.h" 54 #include "rte_pmd_ixgbe.h" 55 56 #define IXGBE_MAX_VFTA (128) 57 #define IXGBE_VF_MSG_SIZE_DEFAULT 1 58 #define IXGBE_VF_GET_QUEUE_MSG_SIZE 5 59 #define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808 60 61 static inline uint16_t 62 dev_num_vf(struct rte_eth_dev *eth_dev) 63 { 64 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 65 66 return pci_dev->max_vfs; 67 } 68 69 static inline 70 int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num) 71 { 72 unsigned char vf_mac_addr[ETHER_ADDR_LEN]; 73 struct ixgbe_vf_info *vfinfo = 74 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 75 uint16_t vfn; 76 77 for (vfn = 0; vfn < vf_num; vfn++) { 78 eth_random_addr(vf_mac_addr); 79 /* keep the random address as default */ 80 memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr, 81 ETHER_ADDR_LEN); 82 } 83 84 return 0; 85 } 86 87 static inline int 88 ixgbe_mb_intr_setup(struct rte_eth_dev *dev) 89 { 90 struct ixgbe_interrupt *intr = 91 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 92 93 intr->mask |= IXGBE_EICR_MAILBOX; 94 95 return 0; 96 } 97 98 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev) 99 { 100 struct ixgbe_vf_info **vfinfo = 101 IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private); 102 struct ixgbe_mirror_info *mirror_info = 103 IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private); 104 struct ixgbe_uta_info *uta_info = 105 IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private); 106 struct ixgbe_hw *hw = 107 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 108 uint16_t vf_num; 109 uint8_t nb_queue; 110 111 PMD_INIT_FUNC_TRACE(); 112 113 RTE_ETH_DEV_SRIOV(eth_dev).active = 0; 114 vf_num = dev_num_vf(eth_dev); 115 if (vf_num == 0) 116 return; 117 118 *vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0); 119 if (*vfinfo == NULL) 120 rte_panic("Cannot allocate memory for private VF data\n"); 121 122 memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info)); 123 memset(uta_info, 0, sizeof(struct ixgbe_uta_info)); 124 hw->mac.mc_filter_type = 0; 125 126 if (vf_num >= ETH_32_POOLS) { 127 nb_queue = 2; 128 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS; 129 } else if (vf_num >= ETH_16_POOLS) { 130 nb_queue = 4; 131 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS; 132 } else { 133 nb_queue = 8; 134 RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS; 135 } 136 137 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue; 138 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num; 139 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue); 140 141 ixgbe_vf_perm_addr_gen(eth_dev, vf_num); 142 143 /* init_mailbox_params */ 144 hw->mbx.ops.init_params(hw); 145 146 /* set mb interrupt mask */ 147 ixgbe_mb_intr_setup(eth_dev); 148 } 149 150 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev) 151 { 152 struct ixgbe_vf_info **vfinfo; 153 uint16_t vf_num; 154 155 PMD_INIT_FUNC_TRACE(); 156 157 vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private); 158 159 RTE_ETH_DEV_SRIOV(eth_dev).active = 0; 160 RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0; 161 RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0; 162 RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0; 163 164 vf_num = dev_num_vf(eth_dev); 165 if (vf_num == 0) 166 return; 167 168 rte_free(*vfinfo); 169 *vfinfo = NULL; 170 } 171 172 static void 173 ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev) 174 { 175 struct ixgbe_hw *hw = 176 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 177 struct ixgbe_filter_info *filter_info = 178 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 179 uint16_t vf_num; 180 int i; 181 struct ixgbe_ethertype_filter ethertype_filter; 182 183 if (!hw->mac.ops.set_ethertype_anti_spoofing) { 184 RTE_LOG(INFO, PMD, "ether type anti-spoofing is not" 185 " supported.\n"); 186 return; 187 } 188 189 i = ixgbe_ethertype_filter_lookup(filter_info, 190 IXGBE_ETHERTYPE_FLOW_CTRL); 191 if (i >= 0) { 192 RTE_LOG(ERR, PMD, "A ether type filter" 193 " entity for flow control already exists!\n"); 194 return; 195 } 196 197 ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL; 198 ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN | 199 IXGBE_ETQF_TX_ANTISPOOF | 200 IXGBE_ETHERTYPE_FLOW_CTRL; 201 ethertype_filter.etqs = 0; 202 ethertype_filter.conf = TRUE; 203 i = ixgbe_ethertype_filter_insert(filter_info, 204 ðertype_filter); 205 if (i < 0) { 206 RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter" 207 " entity for flow control.\n"); 208 return; 209 } 210 211 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 212 (IXGBE_ETQF_FILTER_EN | 213 IXGBE_ETQF_TX_ANTISPOOF | 214 IXGBE_ETHERTYPE_FLOW_CTRL)); 215 216 vf_num = dev_num_vf(eth_dev); 217 for (i = 0; i < vf_num; i++) 218 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i); 219 } 220 221 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev) 222 { 223 uint32_t vtctl, fcrth; 224 uint32_t vfre_slot, vfre_offset; 225 uint16_t vf_num; 226 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ 227 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); 228 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 229 uint32_t gpie, gcr_ext; 230 uint32_t vlanctrl; 231 int i; 232 233 vf_num = dev_num_vf(eth_dev); 234 if (vf_num == 0) 235 return -1; 236 237 /* enable VMDq and set the default pool for PF */ 238 vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 239 vtctl |= IXGBE_VMD_CTL_VMDQ_EN; 240 vtctl &= ~IXGBE_VT_CTL_POOL_MASK; 241 vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx 242 << IXGBE_VT_CTL_POOL_SHIFT; 243 vtctl |= IXGBE_VT_CTL_REPLEN; 244 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl); 245 246 vfre_offset = vf_num & VFRE_MASK; 247 vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0; 248 249 /* Enable pools reserved to PF only */ 250 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset); 251 IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1); 252 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset); 253 IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1); 254 255 /* PFDMA Tx General Switch Control Enables VMDQ loopback */ 256 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); 257 258 /* clear VMDq map to perment rar 0 */ 259 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 260 261 /* clear VMDq map to scan rar 127 */ 262 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0); 263 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0); 264 265 /* set VMDq map to default PF pool */ 266 hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx); 267 268 /* 269 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode 270 */ 271 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 272 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK; 273 274 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 275 gpie &= ~IXGBE_GPIE_VTMODE_MASK; 276 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT; 277 278 switch (RTE_ETH_DEV_SRIOV(eth_dev).active) { 279 case ETH_64_POOLS: 280 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; 281 gpie |= IXGBE_GPIE_VTMODE_64; 282 break; 283 case ETH_32_POOLS: 284 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32; 285 gpie |= IXGBE_GPIE_VTMODE_32; 286 break; 287 case ETH_16_POOLS: 288 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16; 289 gpie |= IXGBE_GPIE_VTMODE_16; 290 break; 291 } 292 293 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 294 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 295 296 /* 297 * enable vlan filtering and allow all vlan tags through 298 */ 299 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 300 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 301 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 302 303 /* VFTA - enable all vlan filters */ 304 for (i = 0; i < IXGBE_MAX_VFTA; i++) 305 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF); 306 307 /* Enable MAC Anti-Spoofing */ 308 hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num); 309 310 /* set flow control threshold to max to avoid tx switch hang */ 311 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 312 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 313 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 314 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 315 } 316 317 ixgbe_add_tx_flow_control_drop_filter(eth_dev); 318 319 return 0; 320 } 321 322 static void 323 set_rx_mode(struct rte_eth_dev *dev) 324 { 325 struct rte_eth_dev_data *dev_data = dev->data; 326 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 327 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; 328 uint16_t vfn = dev_num_vf(dev); 329 330 /* Check for Promiscuous and All Multicast modes */ 331 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 332 333 /* set all bits that we expect to always be set */ 334 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ 335 fctrl |= IXGBE_FCTRL_BAM; 336 337 /* clear the bits we are changing the status of */ 338 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 339 340 if (dev_data->promiscuous) { 341 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 342 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); 343 } else { 344 if (dev_data->all_multicast) { 345 fctrl |= IXGBE_FCTRL_MPE; 346 vmolr |= IXGBE_VMOLR_MPE; 347 } else { 348 vmolr |= IXGBE_VMOLR_ROMPE; 349 } 350 } 351 352 if (hw->mac.type != ixgbe_mac_82598EB) { 353 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) & 354 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | 355 IXGBE_VMOLR_ROPE); 356 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr); 357 } 358 359 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 360 361 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 362 ixgbe_vlan_hw_strip_enable_all(dev); 363 else 364 ixgbe_vlan_hw_strip_disable_all(dev); 365 } 366 367 static inline void 368 ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf) 369 { 370 struct ixgbe_hw *hw = 371 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 372 struct ixgbe_vf_info *vfinfo = 373 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 374 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 375 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); 376 377 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE | 378 IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); 379 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); 380 381 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0); 382 383 /* reset multicast table array for vf */ 384 vfinfo[vf].num_vf_mc_hashes = 0; 385 386 /* reset rx mode */ 387 set_rx_mode(dev); 388 389 hw->mac.ops.clear_rar(hw, rar_entry); 390 } 391 392 static inline void 393 ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf) 394 { 395 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 396 uint32_t reg; 397 uint32_t reg_offset, vf_shift; 398 const uint8_t VFRE_SHIFT = 5; /* VFRE 32 bits per slot */ 399 const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1); 400 uint8_t nb_q_per_pool; 401 int i; 402 403 vf_shift = vf & VFRE_MASK; 404 reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0; 405 406 /* enable transmit for vf */ 407 reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset)); 408 reg |= (reg | (1 << vf_shift)); 409 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg); 410 411 /* enable all queue drop for IOV */ 412 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 413 for (i = vf * nb_q_per_pool; i < (vf + 1) * nb_q_per_pool; i++) { 414 IXGBE_WRITE_FLUSH(hw); 415 reg = IXGBE_QDE_ENABLE | IXGBE_QDE_WRITE; 416 reg |= i << IXGBE_QDE_IDX_SHIFT; 417 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg); 418 } 419 420 /* enable receive for vf */ 421 reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset)); 422 reg |= (reg | (1 << vf_shift)); 423 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg); 424 425 /* Enable counting of spoofed packets in the SSVPC register */ 426 reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset)); 427 reg |= (1 << vf_shift); 428 IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg); 429 430 ixgbe_vf_reset_event(dev, vf); 431 } 432 433 static int 434 ixgbe_enable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf) 435 { 436 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 437 uint32_t vmolr; 438 439 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); 440 441 RTE_LOG(INFO, PMD, "VF %u: enabling multicast promiscuous\n", vf); 442 443 vmolr |= IXGBE_VMOLR_MPE; 444 445 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); 446 447 return 0; 448 } 449 450 static int 451 ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf) 452 { 453 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 454 uint32_t vmolr; 455 456 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf)); 457 458 RTE_LOG(INFO, PMD, "VF %u: disabling multicast promiscuous\n", vf); 459 460 vmolr &= ~IXGBE_VMOLR_MPE; 461 462 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr); 463 464 return 0; 465 } 466 467 static int 468 ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf) 469 { 470 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 471 struct ixgbe_vf_info *vfinfo = 472 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 473 unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses; 474 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 475 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 476 477 ixgbe_vf_reset_msg(dev, vf); 478 479 hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV); 480 481 /* Disable multicast promiscuous at reset */ 482 ixgbe_disable_vf_mc_promisc(dev, vf); 483 484 /* reply to reset with ack and vf mac address */ 485 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK; 486 rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN); 487 /* 488 * Piggyback the multicast filter type so VF can compute the 489 * correct vectors 490 */ 491 msgbuf[3] = hw->mac.mc_filter_type; 492 ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf); 493 494 return 0; 495 } 496 497 static int 498 ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 499 { 500 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 501 struct ixgbe_vf_info *vfinfo = 502 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 503 int rar_entry = hw->mac.num_rar_entries - (vf + 1); 504 uint8_t *new_mac = (uint8_t *)(&msgbuf[1]); 505 506 if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) { 507 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6); 508 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV); 509 } 510 return -1; 511 } 512 513 static int 514 ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 515 { 516 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 517 struct ixgbe_vf_info *vfinfo = 518 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 519 int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >> 520 IXGBE_VT_MSGINFO_SHIFT; 521 uint16_t *hash_list = (uint16_t *)&msgbuf[1]; 522 uint32_t mta_idx; 523 uint32_t mta_shift; 524 const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F; 525 const uint32_t IXGBE_MTA_BIT_SHIFT = 5; 526 const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1; 527 uint32_t reg_val; 528 int i; 529 530 /* Disable multicast promiscuous first */ 531 ixgbe_disable_vf_mc_promisc(dev, vf); 532 533 /* only so many hash values supported */ 534 nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES); 535 536 /* store the mc entries */ 537 vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries; 538 for (i = 0; i < nb_entries; i++) { 539 vfinfo->vf_mc_hashes[i] = hash_list[i]; 540 } 541 542 for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) { 543 mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT) 544 & IXGBE_MTA_INDEX_MASK; 545 mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK; 546 reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx)); 547 reg_val |= (1 << mta_shift); 548 IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val); 549 } 550 551 return 0; 552 } 553 554 static int 555 ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 556 { 557 int add, vid; 558 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 559 struct ixgbe_vf_info *vfinfo = 560 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 561 562 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) 563 >> IXGBE_VT_MSGINFO_SHIFT; 564 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK); 565 566 if (add) 567 vfinfo[vf].vlan_count++; 568 else if (vfinfo[vf].vlan_count) 569 vfinfo[vf].vlan_count--; 570 return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false); 571 } 572 573 static int 574 ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf) 575 { 576 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 577 uint32_t new_mtu = msgbuf[1]; 578 uint32_t max_frs; 579 int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 580 581 /* X540 and X550 support jumbo frames in IOV mode */ 582 if (hw->mac.type != ixgbe_mac_X540 && 583 hw->mac.type != ixgbe_mac_X550 && 584 hw->mac.type != ixgbe_mac_X550EM_x && 585 hw->mac.type != ixgbe_mac_X550EM_a) 586 return -1; 587 588 if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN)) 589 return -1; 590 591 max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) & 592 IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT; 593 if (max_frs < new_mtu) { 594 max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT; 595 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs); 596 } 597 598 return 0; 599 } 600 601 static int 602 ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 603 { 604 uint32_t api_version = msgbuf[1]; 605 struct ixgbe_vf_info *vfinfo = 606 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 607 608 switch (api_version) { 609 case ixgbe_mbox_api_10: 610 case ixgbe_mbox_api_11: 611 case ixgbe_mbox_api_12: 612 vfinfo[vf].api_version = (uint8_t)api_version; 613 return 0; 614 default: 615 break; 616 } 617 618 RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n", 619 api_version, vf); 620 621 return -1; 622 } 623 624 static int 625 ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 626 { 627 struct ixgbe_vf_info *vfinfo = 628 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 629 uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 630 struct rte_eth_conf *eth_conf; 631 struct rte_eth_vmdq_dcb_tx_conf *vmdq_dcb_tx_conf; 632 u8 num_tcs; 633 struct ixgbe_hw *hw; 634 u32 vmvir; 635 #define IXGBE_VMVIR_VLANA_MASK 0xC0000000 636 #define IXGBE_VMVIR_VLAN_VID_MASK 0x00000FFF 637 #define IXGBE_VMVIR_VLAN_UP_MASK 0x0000E000 638 #define VLAN_PRIO_SHIFT 13 639 u32 vlana; 640 u32 vid; 641 u32 user_priority; 642 643 /* Verify if the PF supports the mbox APIs version or not */ 644 switch (vfinfo[vf].api_version) { 645 case ixgbe_mbox_api_20: 646 case ixgbe_mbox_api_11: 647 case ixgbe_mbox_api_12: 648 break; 649 default: 650 return -1; 651 } 652 653 /* Notify VF of Rx and Tx queue number */ 654 msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 655 msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 656 657 /* Notify VF of default queue */ 658 msgbuf[IXGBE_VF_DEF_QUEUE] = default_q; 659 660 /* Notify VF of number of DCB traffic classes */ 661 eth_conf = &dev->data->dev_conf; 662 switch (eth_conf->txmode.mq_mode) { 663 case ETH_MQ_TX_NONE: 664 case ETH_MQ_TX_DCB: 665 RTE_LOG(ERR, PMD, "PF must work with virtualization for VF %u" 666 ", but its tx mode = %d\n", vf, 667 eth_conf->txmode.mq_mode); 668 return -1; 669 670 case ETH_MQ_TX_VMDQ_DCB: 671 vmdq_dcb_tx_conf = ð_conf->tx_adv_conf.vmdq_dcb_tx_conf; 672 switch (vmdq_dcb_tx_conf->nb_queue_pools) { 673 case ETH_16_POOLS: 674 num_tcs = ETH_8_TCS; 675 break; 676 case ETH_32_POOLS: 677 num_tcs = ETH_4_TCS; 678 break; 679 default: 680 return -1; 681 } 682 break; 683 684 /* ETH_MQ_TX_VMDQ_ONLY, DCB not enabled */ 685 case ETH_MQ_TX_VMDQ_ONLY: 686 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 687 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf)); 688 vlana = vmvir & IXGBE_VMVIR_VLANA_MASK; 689 vid = vmvir & IXGBE_VMVIR_VLAN_VID_MASK; 690 user_priority = 691 (vmvir & IXGBE_VMVIR_VLAN_UP_MASK) >> VLAN_PRIO_SHIFT; 692 if ((vlana == IXGBE_VMVIR_VLANA_DEFAULT) && 693 ((vid != 0) || (user_priority != 0))) 694 num_tcs = 1; 695 else 696 num_tcs = 0; 697 break; 698 699 default: 700 RTE_LOG(ERR, PMD, "PF work with invalid mode = %d\n", 701 eth_conf->txmode.mq_mode); 702 return -1; 703 } 704 msgbuf[IXGBE_VF_TRANS_VLAN] = num_tcs; 705 706 return 0; 707 } 708 709 static int 710 ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf) 711 { 712 struct ixgbe_vf_info *vfinfo = 713 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 714 bool enable = !!msgbuf[1]; /* msgbuf contains the flag to enable */ 715 716 switch (vfinfo[vf].api_version) { 717 case ixgbe_mbox_api_12: 718 break; 719 default: 720 return -1; 721 } 722 723 if (enable) 724 return ixgbe_enable_vf_mc_promisc(dev, vf); 725 else 726 return ixgbe_disable_vf_mc_promisc(dev, vf); 727 } 728 729 static int 730 ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf) 731 { 732 uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE; 733 uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT; 734 uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE]; 735 int32_t retval; 736 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 737 struct ixgbe_vf_info *vfinfo = 738 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 739 struct rte_pmd_ixgbe_mb_event_param ret_param; 740 741 retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf); 742 if (retval) { 743 PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf); 744 return retval; 745 } 746 747 /* do nothing with the message already been processed */ 748 if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK)) 749 return retval; 750 751 /* flush the ack before we write any messages back */ 752 IXGBE_WRITE_FLUSH(hw); 753 754 /** 755 * initialise structure to send to user application 756 * will return response from user in retval field 757 */ 758 ret_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED; 759 ret_param.vfid = vf; 760 ret_param.msg_type = msgbuf[0] & 0xFFFF; 761 ret_param.msg = (void *)msgbuf; 762 763 /* perform VF reset */ 764 if (msgbuf[0] == IXGBE_VF_RESET) { 765 int ret = ixgbe_vf_reset(dev, vf, msgbuf); 766 767 vfinfo[vf].clear_to_send = true; 768 769 /* notify application about VF reset */ 770 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, 771 NULL, &ret_param); 772 return ret; 773 } 774 775 /** 776 * ask user application if we allowed to perform those functions 777 * if we get ret_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED 778 * then business as usual, 779 * if 0, do nothing and send ACK to VF 780 * if ret_param.retval > 1, do nothing and send NAK to VF 781 */ 782 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, 783 NULL, &ret_param); 784 785 retval = ret_param.retval; 786 787 /* check & process VF to PF mailbox message */ 788 switch ((msgbuf[0] & 0xFFFF)) { 789 case IXGBE_VF_SET_MAC_ADDR: 790 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 791 retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf); 792 break; 793 case IXGBE_VF_SET_MULTICAST: 794 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 795 retval = ixgbe_vf_set_multicast(dev, vf, msgbuf); 796 break; 797 case IXGBE_VF_SET_LPE: 798 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 799 retval = ixgbe_set_vf_lpe(dev, vf, msgbuf); 800 break; 801 case IXGBE_VF_SET_VLAN: 802 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 803 retval = ixgbe_vf_set_vlan(dev, vf, msgbuf); 804 break; 805 case IXGBE_VF_API_NEGOTIATE: 806 retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf); 807 break; 808 case IXGBE_VF_GET_QUEUES: 809 retval = ixgbe_get_vf_queues(dev, vf, msgbuf); 810 msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE; 811 break; 812 case IXGBE_VF_UPDATE_XCAST_MODE: 813 if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED) 814 retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf); 815 break; 816 default: 817 PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]); 818 retval = IXGBE_ERR_MBX; 819 break; 820 } 821 822 /* response the VF according to the message process result */ 823 if (retval) 824 msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK; 825 else 826 msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK; 827 828 msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS; 829 830 ixgbe_write_mbx(hw, msgbuf, msg_size, vf); 831 832 return retval; 833 } 834 835 static inline void 836 ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf) 837 { 838 uint32_t msg = IXGBE_VT_MSGTYPE_NACK; 839 struct ixgbe_hw *hw = 840 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 841 struct ixgbe_vf_info *vfinfo = 842 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 843 844 if (!vfinfo[vf].clear_to_send) 845 ixgbe_write_mbx(hw, &msg, 1, vf); 846 } 847 848 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev) 849 { 850 uint16_t vf; 851 struct ixgbe_hw *hw = 852 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 853 854 for (vf = 0; vf < dev_num_vf(eth_dev); vf++) { 855 /* check & process vf function level reset */ 856 if (!ixgbe_check_for_rst(hw, vf)) 857 ixgbe_vf_reset_event(eth_dev, vf); 858 859 /* check & process vf mailbox messages */ 860 if (!ixgbe_check_for_msg(hw, vf)) 861 ixgbe_rcv_msg_from_vf(eth_dev, vf); 862 863 /* check & process acks from vf */ 864 if (!ixgbe_check_for_ack(hw, vf)) 865 ixgbe_rcv_ack_from_vf(eth_dev, vf); 866 } 867 } 868