1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2010-2017 Intel Corporation 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <errno.h> 8 #include <stdint.h> 9 #include <string.h> 10 #include <unistd.h> 11 #include <stdarg.h> 12 #include <inttypes.h> 13 #include <netinet/in.h> 14 #include <rte_byteorder.h> 15 #include <rte_common.h> 16 #include <rte_cycles.h> 17 18 #include <rte_interrupts.h> 19 #include <rte_log.h> 20 #include <rte_debug.h> 21 #include <rte_pci.h> 22 #include <rte_bus_pci.h> 23 #include <rte_branch_prediction.h> 24 #include <rte_memory.h> 25 #include <rte_eal.h> 26 #include <rte_alarm.h> 27 #include <rte_ether.h> 28 #include <rte_ethdev_driver.h> 29 #include <rte_ethdev_pci.h> 30 #include <rte_malloc.h> 31 #include <rte_random.h> 32 #include <rte_dev.h> 33 #include <rte_hash_crc.h> 34 #ifdef RTE_LIBRTE_SECURITY 35 #include <rte_security_driver.h> 36 #endif 37 38 #include "ixgbe_logs.h" 39 #include "base/ixgbe_api.h" 40 #include "base/ixgbe_vf.h" 41 #include "base/ixgbe_common.h" 42 #include "ixgbe_ethdev.h" 43 #include "ixgbe_bypass.h" 44 #include "ixgbe_rxtx.h" 45 #include "base/ixgbe_type.h" 46 #include "base/ixgbe_phy.h" 47 #include "ixgbe_regs.h" 48 49 /* 50 * High threshold controlling when to start sending XOFF frames. Must be at 51 * least 8 bytes less than receive packet buffer size. This value is in units 52 * of 1024 bytes. 53 */ 54 #define IXGBE_FC_HI 0x80 55 56 /* 57 * Low threshold controlling when to start sending XON frames. This value is 58 * in units of 1024 bytes. 59 */ 60 #define IXGBE_FC_LO 0x40 61 62 /* Timer value included in XOFF frames. */ 63 #define IXGBE_FC_PAUSE 0x680 64 65 /*Default value of Max Rx Queue*/ 66 #define IXGBE_MAX_RX_QUEUE_NUM 128 67 68 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */ 69 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */ 70 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */ 71 72 #define IXGBE_MMW_SIZE_DEFAULT 0x4 73 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14 74 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */ 75 76 /* 77 * Default values for RX/TX configuration 78 */ 79 #define IXGBE_DEFAULT_RX_FREE_THRESH 32 80 #define IXGBE_DEFAULT_RX_PTHRESH 8 81 #define IXGBE_DEFAULT_RX_HTHRESH 8 82 #define IXGBE_DEFAULT_RX_WTHRESH 0 83 84 #define IXGBE_DEFAULT_TX_FREE_THRESH 32 85 #define IXGBE_DEFAULT_TX_PTHRESH 32 86 #define IXGBE_DEFAULT_TX_HTHRESH 0 87 #define IXGBE_DEFAULT_TX_WTHRESH 0 88 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32 89 90 /* Bit shift and mask */ 91 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2) 92 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t) 93 #define IXGBE_8_BIT_WIDTH CHAR_BIT 94 #define IXGBE_8_BIT_MASK UINT8_MAX 95 96 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */ 97 98 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0])) 99 100 /* Additional timesync values. */ 101 #define NSEC_PER_SEC 1000000000L 102 #define IXGBE_INCVAL_10GB 0x66666666 103 #define IXGBE_INCVAL_1GB 0x40000000 104 #define IXGBE_INCVAL_100 0x50000000 105 #define IXGBE_INCVAL_SHIFT_10GB 28 106 #define IXGBE_INCVAL_SHIFT_1GB 24 107 #define IXGBE_INCVAL_SHIFT_100 21 108 #define IXGBE_INCVAL_SHIFT_82599 7 109 #define IXGBE_INCPER_SHIFT_82599 24 110 111 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL 112 113 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000 114 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000 115 #define IXGBE_ETAG_ETYPE 0x00005084 116 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff 117 #define IXGBE_ETAG_ETYPE_VALID 0x80000000 118 #define IXGBE_RAH_ADTYPE 0x40000000 119 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff 120 #define IXGBE_VMVIR_TAGA_MASK 0x18000000 121 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000 122 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */ 123 #define IXGBE_QDE_STRIP_TAG 0x00000004 124 #define IXGBE_VTEICR_MASK 0x07 125 126 #define IXGBE_EXVET_VET_EXT_SHIFT 16 127 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000 128 129 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 130 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev); 131 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev); 132 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev); 133 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev); 134 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev); 135 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev); 136 static int ixgbe_dev_configure(struct rte_eth_dev *dev); 137 static int ixgbe_dev_start(struct rte_eth_dev *dev); 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev); 139 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev); 140 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev); 141 static void ixgbe_dev_close(struct rte_eth_dev *dev); 142 static int ixgbe_dev_reset(struct rte_eth_dev *dev); 143 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 144 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 145 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 146 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 147 static int ixgbe_dev_link_update(struct rte_eth_dev *dev, 148 int wait_to_complete); 149 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev, 150 struct rte_eth_stats *stats); 151 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev, 152 struct rte_eth_xstat *xstats, unsigned n); 153 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, 154 struct rte_eth_xstat *xstats, unsigned n); 155 static int 156 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 157 uint64_t *values, unsigned int n); 158 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev); 159 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev); 160 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 161 struct rte_eth_xstat_name *xstats_names, 162 unsigned int size); 163 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev, 164 struct rte_eth_xstat_name *xstats_names, unsigned limit); 165 static int ixgbe_dev_xstats_get_names_by_id( 166 struct rte_eth_dev *dev, 167 struct rte_eth_xstat_name *xstats_names, 168 const uint64_t *ids, 169 unsigned int limit); 170 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 171 uint16_t queue_id, 172 uint8_t stat_idx, 173 uint8_t is_rx); 174 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 175 size_t fw_size); 176 static void ixgbe_dev_info_get(struct rte_eth_dev *dev, 177 struct rte_eth_dev_info *dev_info); 178 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 179 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev, 180 struct rte_eth_dev_info *dev_info); 181 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 182 183 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev, 184 uint16_t vlan_id, int on); 185 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 186 enum rte_vlan_type vlan_type, 187 uint16_t tpid_id); 188 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, 189 uint16_t queue, bool on); 190 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, 191 int on); 192 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, 193 int mask); 194 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask); 195 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 196 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue); 197 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue); 198 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev); 199 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev); 200 201 static int ixgbe_dev_led_on(struct rte_eth_dev *dev); 202 static int ixgbe_dev_led_off(struct rte_eth_dev *dev); 203 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, 204 struct rte_eth_fc_conf *fc_conf); 205 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, 206 struct rte_eth_fc_conf *fc_conf); 207 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 208 struct rte_eth_pfc_conf *pfc_conf); 209 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 210 struct rte_eth_rss_reta_entry64 *reta_conf, 211 uint16_t reta_size); 212 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 213 struct rte_eth_rss_reta_entry64 *reta_conf, 214 uint16_t reta_size); 215 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev); 216 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on); 217 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev); 218 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev); 219 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev); 220 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev); 221 static void ixgbe_dev_interrupt_handler(void *param); 222 static void ixgbe_dev_interrupt_delayed_handler(void *param); 223 static void ixgbe_dev_setup_link_alarm_handler(void *param); 224 225 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 226 uint32_t index, uint32_t pool); 227 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index); 228 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, 229 struct ether_addr *mac_addr); 230 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config); 231 static bool is_device_supported(struct rte_eth_dev *dev, 232 struct rte_pci_driver *drv); 233 234 /* For Virtual Function support */ 235 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev); 236 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev); 237 static int ixgbevf_dev_configure(struct rte_eth_dev *dev); 238 static int ixgbevf_dev_start(struct rte_eth_dev *dev); 239 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, 240 int wait_to_complete); 241 static void ixgbevf_dev_stop(struct rte_eth_dev *dev); 242 static void ixgbevf_dev_close(struct rte_eth_dev *dev); 243 static int ixgbevf_dev_reset(struct rte_eth_dev *dev); 244 static void ixgbevf_intr_disable(struct rte_eth_dev *dev); 245 static void ixgbevf_intr_enable(struct rte_eth_dev *dev); 246 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, 247 struct rte_eth_stats *stats); 248 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); 249 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, 250 uint16_t vlan_id, int on); 251 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, 252 uint16_t queue, int on); 253 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask); 254 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask); 255 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on); 256 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 257 uint16_t queue_id); 258 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 259 uint16_t queue_id); 260 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 261 uint8_t queue, uint8_t msix_vector); 262 static void ixgbevf_configure_msix(struct rte_eth_dev *dev); 263 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev); 264 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev); 265 266 /* For Eth VMDQ APIs support */ 267 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct 268 ether_addr * mac_addr, uint8_t on); 269 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on); 270 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 271 struct rte_eth_mirror_conf *mirror_conf, 272 uint8_t rule_id, uint8_t on); 273 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, 274 uint8_t rule_id); 275 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, 276 uint16_t queue_id); 277 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, 278 uint16_t queue_id); 279 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 280 uint8_t queue, uint8_t msix_vector); 281 static void ixgbe_configure_msix(struct rte_eth_dev *dev); 282 283 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev, 284 struct ether_addr *mac_addr, 285 uint32_t index, uint32_t pool); 286 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index); 287 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, 288 struct ether_addr *mac_addr); 289 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev, 290 struct rte_eth_syn_filter *filter); 291 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 292 enum rte_filter_op filter_op, 293 void *arg); 294 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 295 struct ixgbe_5tuple_filter *filter); 296 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 297 struct ixgbe_5tuple_filter *filter); 298 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 299 enum rte_filter_op filter_op, 300 void *arg); 301 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 302 struct rte_eth_ntuple_filter *filter); 303 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 304 enum rte_filter_op filter_op, 305 void *arg); 306 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 307 struct rte_eth_ethertype_filter *filter); 308 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 309 enum rte_filter_type filter_type, 310 enum rte_filter_op filter_op, 311 void *arg); 312 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 313 314 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 315 struct ether_addr *mc_addr_set, 316 uint32_t nb_mc_addr); 317 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 318 struct rte_eth_dcb_info *dcb_info); 319 320 static int ixgbe_get_reg_length(struct rte_eth_dev *dev); 321 static int ixgbe_get_regs(struct rte_eth_dev *dev, 322 struct rte_dev_reg_info *regs); 323 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev); 324 static int ixgbe_get_eeprom(struct rte_eth_dev *dev, 325 struct rte_dev_eeprom_info *eeprom); 326 static int ixgbe_set_eeprom(struct rte_eth_dev *dev, 327 struct rte_dev_eeprom_info *eeprom); 328 329 static int ixgbe_get_module_info(struct rte_eth_dev *dev, 330 struct rte_eth_dev_module_info *modinfo); 331 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 332 struct rte_dev_eeprom_info *info); 333 334 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev); 335 static int ixgbevf_get_regs(struct rte_eth_dev *dev, 336 struct rte_dev_reg_info *regs); 337 338 static int ixgbe_timesync_enable(struct rte_eth_dev *dev); 339 static int ixgbe_timesync_disable(struct rte_eth_dev *dev); 340 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 341 struct timespec *timestamp, 342 uint32_t flags); 343 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 344 struct timespec *timestamp); 345 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 346 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev, 347 struct timespec *timestamp); 348 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev, 349 const struct timespec *timestamp); 350 static void ixgbevf_dev_interrupt_handler(void *param); 351 352 static int ixgbe_dev_l2_tunnel_eth_type_conf 353 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel); 354 static int ixgbe_dev_l2_tunnel_offload_set 355 (struct rte_eth_dev *dev, 356 struct rte_eth_l2_tunnel_conf *l2_tunnel, 357 uint32_t mask, 358 uint8_t en); 359 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 360 enum rte_filter_op filter_op, 361 void *arg); 362 363 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 364 struct rte_eth_udp_tunnel *udp_tunnel); 365 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 366 struct rte_eth_udp_tunnel *udp_tunnel); 367 static int ixgbe_filter_restore(struct rte_eth_dev *dev); 368 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev); 369 370 /* 371 * Define VF Stats MACRO for Non "cleared on read" register 372 */ 373 #define UPDATE_VF_STAT(reg, last, cur) \ 374 { \ 375 uint32_t latest = IXGBE_READ_REG(hw, reg); \ 376 cur += (latest - last) & UINT_MAX; \ 377 last = latest; \ 378 } 379 380 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \ 381 { \ 382 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \ 383 u64 new_msb = IXGBE_READ_REG(hw, msb); \ 384 u64 latest = ((new_msb << 32) | new_lsb); \ 385 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \ 386 last = latest; \ 387 } 388 389 #define IXGBE_SET_HWSTRIP(h, q) do {\ 390 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 391 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 392 (h)->bitmap[idx] |= 1 << bit;\ 393 } while (0) 394 395 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\ 396 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 397 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 398 (h)->bitmap[idx] &= ~(1 << bit);\ 399 } while (0) 400 401 #define IXGBE_GET_HWSTRIP(h, q, r) do {\ 402 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \ 403 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \ 404 (r) = (h)->bitmap[idx] >> bit & 1;\ 405 } while (0) 406 407 int ixgbe_logtype_init; 408 int ixgbe_logtype_driver; 409 410 /* 411 * The set of PCI devices this driver supports 412 */ 413 static const struct rte_pci_id pci_id_ixgbe_map[] = { 414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) }, 415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) }, 416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) }, 417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) }, 418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) }, 419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) }, 420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) }, 421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) }, 422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) }, 423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) }, 424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) }, 425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) }, 426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) }, 427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) }, 428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) }, 429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) }, 430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) }, 431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) }, 432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) }, 433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) }, 434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) }, 435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) }, 436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) }, 437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) }, 438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) }, 439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) }, 440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) }, 441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) }, 442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) }, 443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) }, 444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) }, 445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) }, 446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) }, 447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) }, 448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) }, 449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) }, 450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) }, 451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) }, 452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) }, 453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) }, 454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) }, 455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) }, 456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) }, 457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) }, 458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) }, 459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) }, 460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) }, 461 #ifdef RTE_LIBRTE_IXGBE_BYPASS 462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) }, 463 #endif 464 { .vendor_id = 0, /* sentinel */ }, 465 }; 466 467 /* 468 * The set of PCI devices this driver supports (for 82599 VF) 469 */ 470 static const struct rte_pci_id pci_id_ixgbevf_map[] = { 471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) }, 472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) }, 473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) }, 474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) }, 475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) }, 476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) }, 477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) }, 478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) }, 479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) }, 480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) }, 481 { .vendor_id = 0, /* sentinel */ }, 482 }; 483 484 static const struct rte_eth_desc_lim rx_desc_lim = { 485 .nb_max = IXGBE_MAX_RING_DESC, 486 .nb_min = IXGBE_MIN_RING_DESC, 487 .nb_align = IXGBE_RXD_ALIGN, 488 }; 489 490 static const struct rte_eth_desc_lim tx_desc_lim = { 491 .nb_max = IXGBE_MAX_RING_DESC, 492 .nb_min = IXGBE_MIN_RING_DESC, 493 .nb_align = IXGBE_TXD_ALIGN, 494 .nb_seg_max = IXGBE_TX_MAX_SEG, 495 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG, 496 }; 497 498 static const struct eth_dev_ops ixgbe_eth_dev_ops = { 499 .dev_configure = ixgbe_dev_configure, 500 .dev_start = ixgbe_dev_start, 501 .dev_stop = ixgbe_dev_stop, 502 .dev_set_link_up = ixgbe_dev_set_link_up, 503 .dev_set_link_down = ixgbe_dev_set_link_down, 504 .dev_close = ixgbe_dev_close, 505 .dev_reset = ixgbe_dev_reset, 506 .promiscuous_enable = ixgbe_dev_promiscuous_enable, 507 .promiscuous_disable = ixgbe_dev_promiscuous_disable, 508 .allmulticast_enable = ixgbe_dev_allmulticast_enable, 509 .allmulticast_disable = ixgbe_dev_allmulticast_disable, 510 .link_update = ixgbe_dev_link_update, 511 .stats_get = ixgbe_dev_stats_get, 512 .xstats_get = ixgbe_dev_xstats_get, 513 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id, 514 .stats_reset = ixgbe_dev_stats_reset, 515 .xstats_reset = ixgbe_dev_xstats_reset, 516 .xstats_get_names = ixgbe_dev_xstats_get_names, 517 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id, 518 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set, 519 .fw_version_get = ixgbe_fw_version_get, 520 .dev_infos_get = ixgbe_dev_info_get, 521 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 522 .mtu_set = ixgbe_dev_mtu_set, 523 .vlan_filter_set = ixgbe_vlan_filter_set, 524 .vlan_tpid_set = ixgbe_vlan_tpid_set, 525 .vlan_offload_set = ixgbe_vlan_offload_set, 526 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set, 527 .rx_queue_start = ixgbe_dev_rx_queue_start, 528 .rx_queue_stop = ixgbe_dev_rx_queue_stop, 529 .tx_queue_start = ixgbe_dev_tx_queue_start, 530 .tx_queue_stop = ixgbe_dev_tx_queue_stop, 531 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 532 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable, 533 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable, 534 .rx_queue_release = ixgbe_dev_rx_queue_release, 535 .rx_queue_count = ixgbe_dev_rx_queue_count, 536 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 537 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 538 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 539 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 540 .tx_queue_release = ixgbe_dev_tx_queue_release, 541 .dev_led_on = ixgbe_dev_led_on, 542 .dev_led_off = ixgbe_dev_led_off, 543 .flow_ctrl_get = ixgbe_flow_ctrl_get, 544 .flow_ctrl_set = ixgbe_flow_ctrl_set, 545 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set, 546 .mac_addr_add = ixgbe_add_rar, 547 .mac_addr_remove = ixgbe_remove_rar, 548 .mac_addr_set = ixgbe_set_default_mac_addr, 549 .uc_hash_table_set = ixgbe_uc_hash_table_set, 550 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set, 551 .mirror_rule_set = ixgbe_mirror_rule_set, 552 .mirror_rule_reset = ixgbe_mirror_rule_reset, 553 .set_queue_rate_limit = ixgbe_set_queue_rate_limit, 554 .reta_update = ixgbe_dev_rss_reta_update, 555 .reta_query = ixgbe_dev_rss_reta_query, 556 .rss_hash_update = ixgbe_dev_rss_hash_update, 557 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 558 .filter_ctrl = ixgbe_dev_filter_ctrl, 559 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 560 .rxq_info_get = ixgbe_rxq_info_get, 561 .txq_info_get = ixgbe_txq_info_get, 562 .timesync_enable = ixgbe_timesync_enable, 563 .timesync_disable = ixgbe_timesync_disable, 564 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp, 565 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp, 566 .get_reg = ixgbe_get_regs, 567 .get_eeprom_length = ixgbe_get_eeprom_length, 568 .get_eeprom = ixgbe_get_eeprom, 569 .set_eeprom = ixgbe_set_eeprom, 570 .get_module_info = ixgbe_get_module_info, 571 .get_module_eeprom = ixgbe_get_module_eeprom, 572 .get_dcb_info = ixgbe_dev_get_dcb_info, 573 .timesync_adjust_time = ixgbe_timesync_adjust_time, 574 .timesync_read_time = ixgbe_timesync_read_time, 575 .timesync_write_time = ixgbe_timesync_write_time, 576 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf, 577 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set, 578 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add, 579 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del, 580 .tm_ops_get = ixgbe_tm_ops_get, 581 }; 582 583 /* 584 * dev_ops for virtual function, bare necessities for basic vf 585 * operation have been implemented 586 */ 587 static const struct eth_dev_ops ixgbevf_eth_dev_ops = { 588 .dev_configure = ixgbevf_dev_configure, 589 .dev_start = ixgbevf_dev_start, 590 .dev_stop = ixgbevf_dev_stop, 591 .link_update = ixgbevf_dev_link_update, 592 .stats_get = ixgbevf_dev_stats_get, 593 .xstats_get = ixgbevf_dev_xstats_get, 594 .stats_reset = ixgbevf_dev_stats_reset, 595 .xstats_reset = ixgbevf_dev_stats_reset, 596 .xstats_get_names = ixgbevf_dev_xstats_get_names, 597 .dev_close = ixgbevf_dev_close, 598 .dev_reset = ixgbevf_dev_reset, 599 .allmulticast_enable = ixgbevf_dev_allmulticast_enable, 600 .allmulticast_disable = ixgbevf_dev_allmulticast_disable, 601 .dev_infos_get = ixgbevf_dev_info_get, 602 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get, 603 .mtu_set = ixgbevf_dev_set_mtu, 604 .vlan_filter_set = ixgbevf_vlan_filter_set, 605 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set, 606 .vlan_offload_set = ixgbevf_vlan_offload_set, 607 .rx_queue_setup = ixgbe_dev_rx_queue_setup, 608 .rx_queue_release = ixgbe_dev_rx_queue_release, 609 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done, 610 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status, 611 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status, 612 .tx_queue_setup = ixgbe_dev_tx_queue_setup, 613 .tx_queue_release = ixgbe_dev_tx_queue_release, 614 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable, 615 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable, 616 .mac_addr_add = ixgbevf_add_mac_addr, 617 .mac_addr_remove = ixgbevf_remove_mac_addr, 618 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list, 619 .rxq_info_get = ixgbe_rxq_info_get, 620 .txq_info_get = ixgbe_txq_info_get, 621 .mac_addr_set = ixgbevf_set_default_mac_addr, 622 .get_reg = ixgbevf_get_regs, 623 .reta_update = ixgbe_dev_rss_reta_update, 624 .reta_query = ixgbe_dev_rss_reta_query, 625 .rss_hash_update = ixgbe_dev_rss_hash_update, 626 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get, 627 }; 628 629 /* store statistics names and its offset in stats structure */ 630 struct rte_ixgbe_xstats_name_off { 631 char name[RTE_ETH_XSTATS_NAME_SIZE]; 632 unsigned offset; 633 }; 634 635 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = { 636 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)}, 637 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)}, 638 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)}, 639 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)}, 640 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)}, 641 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)}, 642 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)}, 643 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)}, 644 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)}, 645 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)}, 646 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)}, 647 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)}, 648 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)}, 649 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)}, 650 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 651 prc1023)}, 652 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 653 prc1522)}, 654 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)}, 655 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)}, 656 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)}, 657 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)}, 658 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)}, 659 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)}, 660 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)}, 661 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)}, 662 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)}, 663 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)}, 664 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)}, 665 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)}, 666 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)}, 667 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)}, 668 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)}, 669 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)}, 670 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats, 671 ptc1023)}, 672 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats, 673 ptc1522)}, 674 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)}, 675 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)}, 676 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)}, 677 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)}, 678 679 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats, 680 fdirustat_add)}, 681 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats, 682 fdirustat_remove)}, 683 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats, 684 fdirfstat_fadd)}, 685 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats, 686 fdirfstat_fremove)}, 687 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats, 688 fdirmatch)}, 689 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats, 690 fdirmiss)}, 691 692 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)}, 693 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)}, 694 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, 695 fclast)}, 696 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)}, 697 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)}, 698 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)}, 699 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)}, 700 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats, 701 fcoe_noddp)}, 702 {"rx_fcoe_no_direct_data_placement_ext_buff", 703 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)}, 704 705 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 706 lxontxc)}, 707 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats, 708 lxonrxc)}, 709 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 710 lxofftxc)}, 711 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats, 712 lxoffrxc)}, 713 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)}, 714 }; 715 716 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \ 717 sizeof(rte_ixgbe_stats_strings[0])) 718 719 /* MACsec statistics */ 720 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = { 721 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 722 out_pkts_untagged)}, 723 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats, 724 out_pkts_encrypted)}, 725 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats, 726 out_pkts_protected)}, 727 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats, 728 out_octets_encrypted)}, 729 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats, 730 out_octets_protected)}, 731 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats, 732 in_pkts_untagged)}, 733 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats, 734 in_pkts_badtag)}, 735 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats, 736 in_pkts_nosci)}, 737 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats, 738 in_pkts_unknownsci)}, 739 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats, 740 in_octets_decrypted)}, 741 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats, 742 in_octets_validated)}, 743 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats, 744 in_pkts_unchecked)}, 745 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats, 746 in_pkts_delayed)}, 747 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats, 748 in_pkts_late)}, 749 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats, 750 in_pkts_ok)}, 751 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats, 752 in_pkts_invalid)}, 753 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats, 754 in_pkts_notvalid)}, 755 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats, 756 in_pkts_unusedsa)}, 757 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats, 758 in_pkts_notusingsa)}, 759 }; 760 761 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \ 762 sizeof(rte_ixgbe_macsec_strings[0])) 763 764 /* Per-queue statistics */ 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = { 766 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)}, 767 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)}, 768 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)}, 769 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)}, 770 }; 771 772 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \ 773 sizeof(rte_ixgbe_rxq_strings[0])) 774 #define IXGBE_NB_RXQ_PRIO_VALUES 8 775 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = { 777 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)}, 778 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)}, 779 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats, 780 pxon2offc)}, 781 }; 782 783 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \ 784 sizeof(rte_ixgbe_txq_strings[0])) 785 #define IXGBE_NB_TXQ_PRIO_VALUES 8 786 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = { 788 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)}, 789 }; 790 791 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \ 792 sizeof(rte_ixgbevf_stats_strings[0])) 793 794 /* 795 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h. 796 */ 797 static inline int 798 ixgbe_is_sfp(struct ixgbe_hw *hw) 799 { 800 switch (hw->phy.type) { 801 case ixgbe_phy_sfp_avago: 802 case ixgbe_phy_sfp_ftl: 803 case ixgbe_phy_sfp_intel: 804 case ixgbe_phy_sfp_unknown: 805 case ixgbe_phy_sfp_passive_tyco: 806 case ixgbe_phy_sfp_passive_unknown: 807 return 1; 808 default: 809 return 0; 810 } 811 } 812 813 static inline int32_t 814 ixgbe_pf_reset_hw(struct ixgbe_hw *hw) 815 { 816 uint32_t ctrl_ext; 817 int32_t status; 818 819 status = ixgbe_reset_hw(hw); 820 821 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 822 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 823 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 824 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 825 IXGBE_WRITE_FLUSH(hw); 826 827 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 828 status = IXGBE_SUCCESS; 829 return status; 830 } 831 832 static inline void 833 ixgbe_enable_intr(struct rte_eth_dev *dev) 834 { 835 struct ixgbe_interrupt *intr = 836 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 837 struct ixgbe_hw *hw = 838 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 839 840 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask); 841 IXGBE_WRITE_FLUSH(hw); 842 } 843 844 /* 845 * This function is based on ixgbe_disable_intr() in base/ixgbe.h. 846 */ 847 static void 848 ixgbe_disable_intr(struct ixgbe_hw *hw) 849 { 850 PMD_INIT_FUNC_TRACE(); 851 852 if (hw->mac.type == ixgbe_mac_82598EB) { 853 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0); 854 } else { 855 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000); 856 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0); 857 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0); 858 } 859 IXGBE_WRITE_FLUSH(hw); 860 } 861 862 /* 863 * This function resets queue statistics mapping registers. 864 * From Niantic datasheet, Initialization of Statistics section: 865 * "...if software requires the queue counters, the RQSMR and TQSM registers 866 * must be re-programmed following a device reset. 867 */ 868 static void 869 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw) 870 { 871 uint32_t i; 872 873 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) { 874 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0); 875 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0); 876 } 877 } 878 879 880 static int 881 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev, 882 uint16_t queue_id, 883 uint8_t stat_idx, 884 uint8_t is_rx) 885 { 886 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8 887 #define NB_QMAP_FIELDS_PER_QSM_REG 4 888 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f 889 890 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 891 struct ixgbe_stat_mapping_registers *stat_mappings = 892 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private); 893 uint32_t qsmr_mask = 0; 894 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK; 895 uint32_t q_map; 896 uint8_t n, offset; 897 898 if ((hw->mac.type != ixgbe_mac_82599EB) && 899 (hw->mac.type != ixgbe_mac_X540) && 900 (hw->mac.type != ixgbe_mac_X550) && 901 (hw->mac.type != ixgbe_mac_X550EM_x) && 902 (hw->mac.type != ixgbe_mac_X550EM_a)) 903 return -ENOSYS; 904 905 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d", 906 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 907 queue_id, stat_idx); 908 909 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG); 910 if (n >= IXGBE_NB_STAT_MAPPING_REGS) { 911 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded"); 912 return -EIO; 913 } 914 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG); 915 916 /* Now clear any previous stat_idx set */ 917 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 918 if (!is_rx) 919 stat_mappings->tqsm[n] &= ~clearing_mask; 920 else 921 stat_mappings->rqsmr[n] &= ~clearing_mask; 922 923 q_map = (uint32_t)stat_idx; 924 q_map &= QMAP_FIELD_RESERVED_BITS_MASK; 925 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset); 926 if (!is_rx) 927 stat_mappings->tqsm[n] |= qsmr_mask; 928 else 929 stat_mappings->rqsmr[n] |= qsmr_mask; 930 931 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d", 932 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", 933 queue_id, stat_idx); 934 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n, 935 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]); 936 937 /* Now write the mapping in the appropriate register */ 938 if (is_rx) { 939 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d", 940 stat_mappings->rqsmr[n], n); 941 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]); 942 } else { 943 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d", 944 stat_mappings->tqsm[n], n); 945 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]); 946 } 947 return 0; 948 } 949 950 static void 951 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev) 952 { 953 struct ixgbe_stat_mapping_registers *stat_mappings = 954 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private); 955 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 956 int i; 957 958 /* write whatever was in stat mapping table to the NIC */ 959 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) { 960 /* rx */ 961 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]); 962 963 /* tx */ 964 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]); 965 } 966 } 967 968 static void 969 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config) 970 { 971 uint8_t i; 972 struct ixgbe_dcb_tc_config *tc; 973 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS; 974 975 dcb_config->num_tcs.pg_tcs = dcb_max_tc; 976 dcb_config->num_tcs.pfc_tcs = dcb_max_tc; 977 for (i = 0; i < dcb_max_tc; i++) { 978 tc = &dcb_config->tc_config[i]; 979 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i; 980 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 981 (uint8_t)(100/dcb_max_tc + (i & 1)); 982 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i; 983 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 984 (uint8_t)(100/dcb_max_tc + (i & 1)); 985 tc->pfc = ixgbe_dcb_pfc_disabled; 986 } 987 988 /* Initialize default user to priority mapping, UPx->TC0 */ 989 tc = &dcb_config->tc_config[0]; 990 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; 991 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; 992 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) { 993 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100; 994 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100; 995 } 996 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal; 997 dcb_config->pfc_mode_enable = false; 998 dcb_config->vt_mode = true; 999 dcb_config->round_robin_enable = false; 1000 /* support all DCB capabilities in 82599 */ 1001 dcb_config->support.capabilities = 0xFF; 1002 1003 /*we only support 4 Tcs for X540, X550 */ 1004 if (hw->mac.type == ixgbe_mac_X540 || 1005 hw->mac.type == ixgbe_mac_X550 || 1006 hw->mac.type == ixgbe_mac_X550EM_x || 1007 hw->mac.type == ixgbe_mac_X550EM_a) { 1008 dcb_config->num_tcs.pg_tcs = 4; 1009 dcb_config->num_tcs.pfc_tcs = 4; 1010 } 1011 } 1012 1013 /* 1014 * Ensure that all locks are released before first NVM or PHY access 1015 */ 1016 static void 1017 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw) 1018 { 1019 uint16_t mask; 1020 1021 /* 1022 * Phy lock should not fail in this early stage. If this is the case, 1023 * it is due to an improper exit of the application. 1024 * So force the release of the faulty lock. Release of common lock 1025 * is done automatically by swfw_sync function. 1026 */ 1027 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func; 1028 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1029 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func); 1030 } 1031 ixgbe_release_swfw_semaphore(hw, mask); 1032 1033 /* 1034 * These ones are more tricky since they are common to all ports; but 1035 * swfw_sync retries last long enough (1s) to be almost sure that if 1036 * lock can not be taken it is due to an improper lock of the 1037 * semaphore. 1038 */ 1039 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM; 1040 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) { 1041 PMD_DRV_LOG(DEBUG, "SWFW common locks released"); 1042 } 1043 ixgbe_release_swfw_semaphore(hw, mask); 1044 } 1045 1046 /* 1047 * This function is based on code in ixgbe_attach() in base/ixgbe.c. 1048 * It returns 0 on success. 1049 */ 1050 static int 1051 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) 1052 { 1053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1055 struct ixgbe_hw *hw = 1056 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1057 struct ixgbe_vfta *shadow_vfta = 1058 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1059 struct ixgbe_hwstrip *hwstrip = 1060 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1061 struct ixgbe_dcb_config *dcb_config = 1062 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private); 1063 struct ixgbe_filter_info *filter_info = 1064 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1065 struct ixgbe_bw_conf *bw_conf = 1066 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private); 1067 uint32_t ctrl_ext; 1068 uint16_t csum; 1069 int diag, i; 1070 1071 PMD_INIT_FUNC_TRACE(); 1072 1073 eth_dev->dev_ops = &ixgbe_eth_dev_ops; 1074 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1075 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1076 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts; 1077 1078 /* 1079 * For secondary processes, we don't initialise any further as primary 1080 * has already done this work. Only check we don't need a different 1081 * RX and TX function. 1082 */ 1083 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1084 struct ixgbe_tx_queue *txq; 1085 /* TX queue function in primary, set by last queue initialized 1086 * Tx queue may not initialized by primary process 1087 */ 1088 if (eth_dev->data->tx_queues) { 1089 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1]; 1090 ixgbe_set_tx_function(eth_dev, txq); 1091 } else { 1092 /* Use default TX function if we get here */ 1093 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. " 1094 "Using default TX function."); 1095 } 1096 1097 ixgbe_set_rx_function(eth_dev); 1098 1099 return 0; 1100 } 1101 1102 rte_eth_copy_pci_info(eth_dev, pci_dev); 1103 1104 /* Vendor and Device ID need to be set before init of shared code */ 1105 hw->device_id = pci_dev->id.device_id; 1106 hw->vendor_id = pci_dev->id.vendor_id; 1107 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1108 hw->allow_unsupported_sfp = 1; 1109 1110 /* Initialize the shared code (base driver) */ 1111 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1112 diag = ixgbe_bypass_init_shared_code(hw); 1113 #else 1114 diag = ixgbe_init_shared_code(hw); 1115 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1116 1117 if (diag != IXGBE_SUCCESS) { 1118 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag); 1119 return -EIO; 1120 } 1121 1122 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) { 1123 PMD_INIT_LOG(ERR, "\nERROR: " 1124 "Firmware recovery mode detected. Limiting functionality.\n" 1125 "Refer to the Intel(R) Ethernet Adapters and Devices " 1126 "User Guide for details on firmware recovery mode."); 1127 return -EIO; 1128 } 1129 1130 /* pick up the PCI bus settings for reporting later */ 1131 ixgbe_get_bus_info(hw); 1132 1133 /* Unlock any pending hardware semaphore */ 1134 ixgbe_swfw_lock_reset(hw); 1135 1136 #ifdef RTE_LIBRTE_SECURITY 1137 /* Initialize security_ctx only for primary process*/ 1138 if (ixgbe_ipsec_ctx_create(eth_dev)) 1139 return -ENOMEM; 1140 #endif 1141 1142 /* Initialize DCB configuration*/ 1143 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); 1144 ixgbe_dcb_init(hw, dcb_config); 1145 /* Get Hardware Flow Control setting */ 1146 hw->fc.requested_mode = ixgbe_fc_full; 1147 hw->fc.current_mode = ixgbe_fc_full; 1148 hw->fc.pause_time = IXGBE_FC_PAUSE; 1149 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 1150 hw->fc.low_water[i] = IXGBE_FC_LO; 1151 hw->fc.high_water[i] = IXGBE_FC_HI; 1152 } 1153 hw->fc.send_xon = 1; 1154 1155 /* Make sure we have a good EEPROM before we read from it */ 1156 diag = ixgbe_validate_eeprom_checksum(hw, &csum); 1157 if (diag != IXGBE_SUCCESS) { 1158 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag); 1159 return -EIO; 1160 } 1161 1162 #ifdef RTE_LIBRTE_IXGBE_BYPASS 1163 diag = ixgbe_bypass_init_hw(hw); 1164 #else 1165 diag = ixgbe_init_hw(hw); 1166 #endif /* RTE_LIBRTE_IXGBE_BYPASS */ 1167 1168 /* 1169 * Devices with copper phys will fail to initialise if ixgbe_init_hw() 1170 * is called too soon after the kernel driver unbinding/binding occurs. 1171 * The failure occurs in ixgbe_identify_phy_generic() for all devices, 1172 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is 1173 * also called. See ixgbe_identify_phy_82599(). The reason for the 1174 * failure is not known, and only occuts when virtualisation features 1175 * are disabled in the bios. A delay of 100ms was found to be enough by 1176 * trial-and-error, and is doubled to be safe. 1177 */ 1178 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) { 1179 rte_delay_ms(200); 1180 diag = ixgbe_init_hw(hw); 1181 } 1182 1183 if (diag == IXGBE_ERR_SFP_NOT_PRESENT) 1184 diag = IXGBE_SUCCESS; 1185 1186 if (diag == IXGBE_ERR_EEPROM_VERSION) { 1187 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/" 1188 "LOM. Please be aware there may be issues associated " 1189 "with your hardware."); 1190 PMD_INIT_LOG(ERR, "If you are experiencing problems " 1191 "please contact your Intel or hardware representative " 1192 "who provided you with this hardware."); 1193 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED) 1194 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module"); 1195 if (diag) { 1196 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag); 1197 return -EIO; 1198 } 1199 1200 /* Reset the hw statistics */ 1201 ixgbe_dev_stats_reset(eth_dev); 1202 1203 /* disable interrupt */ 1204 ixgbe_disable_intr(hw); 1205 1206 /* reset mappings for queue statistics hw counters*/ 1207 ixgbe_reset_qstat_mappings(hw); 1208 1209 /* Allocate memory for storing MAC addresses */ 1210 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN * 1211 hw->mac.num_rar_entries, 0); 1212 if (eth_dev->data->mac_addrs == NULL) { 1213 PMD_INIT_LOG(ERR, 1214 "Failed to allocate %u bytes needed to store " 1215 "MAC addresses", 1216 ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1217 return -ENOMEM; 1218 } 1219 /* Copy the permanent MAC address */ 1220 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr, 1221 ð_dev->data->mac_addrs[0]); 1222 1223 /* Allocate memory for storing hash filter MAC addresses */ 1224 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN * 1225 IXGBE_VMDQ_NUM_UC_MAC, 0); 1226 if (eth_dev->data->hash_mac_addrs == NULL) { 1227 PMD_INIT_LOG(ERR, 1228 "Failed to allocate %d bytes needed to store MAC addresses", 1229 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC); 1230 return -ENOMEM; 1231 } 1232 1233 /* initialize the vfta */ 1234 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1235 1236 /* initialize the hw strip bitmap*/ 1237 memset(hwstrip, 0, sizeof(*hwstrip)); 1238 1239 /* initialize PF if max_vfs not zero */ 1240 ixgbe_pf_host_init(eth_dev); 1241 1242 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 1243 /* let hardware know driver is loaded */ 1244 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD; 1245 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 1246 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; 1247 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 1248 IXGBE_WRITE_FLUSH(hw); 1249 1250 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) 1251 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d", 1252 (int) hw->mac.type, (int) hw->phy.type, 1253 (int) hw->phy.sfp_type); 1254 else 1255 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d", 1256 (int) hw->mac.type, (int) hw->phy.type); 1257 1258 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1259 eth_dev->data->port_id, pci_dev->id.vendor_id, 1260 pci_dev->id.device_id); 1261 1262 rte_intr_callback_register(intr_handle, 1263 ixgbe_dev_interrupt_handler, eth_dev); 1264 1265 /* enable uio/vfio intr/eventfd mapping */ 1266 rte_intr_enable(intr_handle); 1267 1268 /* enable support intr */ 1269 ixgbe_enable_intr(eth_dev); 1270 1271 /* initialize filter info */ 1272 memset(filter_info, 0, 1273 sizeof(struct ixgbe_filter_info)); 1274 1275 /* initialize 5tuple filter list */ 1276 TAILQ_INIT(&filter_info->fivetuple_list); 1277 1278 /* initialize flow director filter list & hash */ 1279 ixgbe_fdir_filter_init(eth_dev); 1280 1281 /* initialize l2 tunnel filter list & hash */ 1282 ixgbe_l2_tn_filter_init(eth_dev); 1283 1284 /* initialize flow filter lists */ 1285 ixgbe_filterlist_init(); 1286 1287 /* initialize bandwidth configuration info */ 1288 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf)); 1289 1290 /* initialize Traffic Manager configuration */ 1291 ixgbe_tm_conf_init(eth_dev); 1292 1293 return 0; 1294 } 1295 1296 static int 1297 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1298 { 1299 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1300 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1301 struct ixgbe_hw *hw; 1302 int retries = 0; 1303 int ret; 1304 1305 PMD_INIT_FUNC_TRACE(); 1306 1307 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1308 return 0; 1309 1310 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1311 1312 if (hw->adapter_stopped == 0) 1313 ixgbe_dev_close(eth_dev); 1314 1315 eth_dev->dev_ops = NULL; 1316 eth_dev->rx_pkt_burst = NULL; 1317 eth_dev->tx_pkt_burst = NULL; 1318 1319 /* Unlock any pending hardware semaphore */ 1320 ixgbe_swfw_lock_reset(hw); 1321 1322 /* disable uio intr before callback unregister */ 1323 rte_intr_disable(intr_handle); 1324 1325 do { 1326 ret = rte_intr_callback_unregister(intr_handle, 1327 ixgbe_dev_interrupt_handler, eth_dev); 1328 if (ret >= 0) { 1329 break; 1330 } else if (ret != -EAGAIN) { 1331 PMD_INIT_LOG(ERR, 1332 "intr callback unregister failed: %d", 1333 ret); 1334 return ret; 1335 } 1336 rte_delay_ms(100); 1337 } while (retries++ < (10 + IXGBE_LINK_UP_TIME)); 1338 1339 /* uninitialize PF if max_vfs not zero */ 1340 ixgbe_pf_host_uninit(eth_dev); 1341 1342 /* remove all the fdir filters & hash */ 1343 ixgbe_fdir_filter_uninit(eth_dev); 1344 1345 /* remove all the L2 tunnel filters & hash */ 1346 ixgbe_l2_tn_filter_uninit(eth_dev); 1347 1348 /* Remove all ntuple filters of the device */ 1349 ixgbe_ntuple_filter_uninit(eth_dev); 1350 1351 /* clear all the filters list */ 1352 ixgbe_filterlist_flush(); 1353 1354 /* Remove all Traffic Manager configuration */ 1355 ixgbe_tm_conf_uninit(eth_dev); 1356 1357 #ifdef RTE_LIBRTE_SECURITY 1358 rte_free(eth_dev->security_ctx); 1359 #endif 1360 1361 return 0; 1362 } 1363 1364 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev) 1365 { 1366 struct ixgbe_filter_info *filter_info = 1367 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private); 1368 struct ixgbe_5tuple_filter *p_5tuple; 1369 1370 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) { 1371 TAILQ_REMOVE(&filter_info->fivetuple_list, 1372 p_5tuple, 1373 entries); 1374 rte_free(p_5tuple); 1375 } 1376 memset(filter_info->fivetuple_mask, 0, 1377 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE); 1378 1379 return 0; 1380 } 1381 1382 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev) 1383 { 1384 struct ixgbe_hw_fdir_info *fdir_info = 1385 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1386 struct ixgbe_fdir_filter *fdir_filter; 1387 1388 if (fdir_info->hash_map) 1389 rte_free(fdir_info->hash_map); 1390 if (fdir_info->hash_handle) 1391 rte_hash_free(fdir_info->hash_handle); 1392 1393 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) { 1394 TAILQ_REMOVE(&fdir_info->fdir_list, 1395 fdir_filter, 1396 entries); 1397 rte_free(fdir_filter); 1398 } 1399 1400 return 0; 1401 } 1402 1403 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev) 1404 { 1405 struct ixgbe_l2_tn_info *l2_tn_info = 1406 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1407 struct ixgbe_l2_tn_filter *l2_tn_filter; 1408 1409 if (l2_tn_info->hash_map) 1410 rte_free(l2_tn_info->hash_map); 1411 if (l2_tn_info->hash_handle) 1412 rte_hash_free(l2_tn_info->hash_handle); 1413 1414 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 1415 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, 1416 l2_tn_filter, 1417 entries); 1418 rte_free(l2_tn_filter); 1419 } 1420 1421 return 0; 1422 } 1423 1424 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev) 1425 { 1426 struct ixgbe_hw_fdir_info *fdir_info = 1427 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private); 1428 char fdir_hash_name[RTE_HASH_NAMESIZE]; 1429 struct rte_hash_parameters fdir_hash_params = { 1430 .name = fdir_hash_name, 1431 .entries = IXGBE_MAX_FDIR_FILTER_NUM, 1432 .key_len = sizeof(union ixgbe_atr_input), 1433 .hash_func = rte_hash_crc, 1434 .hash_func_init_val = 0, 1435 .socket_id = rte_socket_id(), 1436 }; 1437 1438 TAILQ_INIT(&fdir_info->fdir_list); 1439 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE, 1440 "fdir_%s", eth_dev->device->name); 1441 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params); 1442 if (!fdir_info->hash_handle) { 1443 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!"); 1444 return -EINVAL; 1445 } 1446 fdir_info->hash_map = rte_zmalloc("ixgbe", 1447 sizeof(struct ixgbe_fdir_filter *) * 1448 IXGBE_MAX_FDIR_FILTER_NUM, 1449 0); 1450 if (!fdir_info->hash_map) { 1451 PMD_INIT_LOG(ERR, 1452 "Failed to allocate memory for fdir hash map!"); 1453 return -ENOMEM; 1454 } 1455 fdir_info->mask_added = FALSE; 1456 1457 return 0; 1458 } 1459 1460 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) 1461 { 1462 struct ixgbe_l2_tn_info *l2_tn_info = 1463 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private); 1464 char l2_tn_hash_name[RTE_HASH_NAMESIZE]; 1465 struct rte_hash_parameters l2_tn_hash_params = { 1466 .name = l2_tn_hash_name, 1467 .entries = IXGBE_MAX_L2_TN_FILTER_NUM, 1468 .key_len = sizeof(struct ixgbe_l2_tn_key), 1469 .hash_func = rte_hash_crc, 1470 .hash_func_init_val = 0, 1471 .socket_id = rte_socket_id(), 1472 }; 1473 1474 TAILQ_INIT(&l2_tn_info->l2_tn_list); 1475 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE, 1476 "l2_tn_%s", eth_dev->device->name); 1477 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params); 1478 if (!l2_tn_info->hash_handle) { 1479 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!"); 1480 return -EINVAL; 1481 } 1482 l2_tn_info->hash_map = rte_zmalloc("ixgbe", 1483 sizeof(struct ixgbe_l2_tn_filter *) * 1484 IXGBE_MAX_L2_TN_FILTER_NUM, 1485 0); 1486 if (!l2_tn_info->hash_map) { 1487 PMD_INIT_LOG(ERR, 1488 "Failed to allocate memory for L2 TN hash map!"); 1489 return -ENOMEM; 1490 } 1491 l2_tn_info->e_tag_en = FALSE; 1492 l2_tn_info->e_tag_fwd_en = FALSE; 1493 l2_tn_info->e_tag_ether_type = ETHER_TYPE_ETAG; 1494 1495 return 0; 1496 } 1497 /* 1498 * Negotiate mailbox API version with the PF. 1499 * After reset API version is always set to the basic one (ixgbe_mbox_api_10). 1500 * Then we try to negotiate starting with the most recent one. 1501 * If all negotiation attempts fail, then we will proceed with 1502 * the default one (ixgbe_mbox_api_10). 1503 */ 1504 static void 1505 ixgbevf_negotiate_api(struct ixgbe_hw *hw) 1506 { 1507 int32_t i; 1508 1509 /* start with highest supported, proceed down */ 1510 static const enum ixgbe_pfvf_api_rev sup_ver[] = { 1511 ixgbe_mbox_api_12, 1512 ixgbe_mbox_api_11, 1513 ixgbe_mbox_api_10, 1514 }; 1515 1516 for (i = 0; 1517 i != RTE_DIM(sup_ver) && 1518 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0; 1519 i++) 1520 ; 1521 } 1522 1523 static void 1524 generate_random_mac_addr(struct ether_addr *mac_addr) 1525 { 1526 uint64_t random; 1527 1528 /* Set Organizationally Unique Identifier (OUI) prefix. */ 1529 mac_addr->addr_bytes[0] = 0x00; 1530 mac_addr->addr_bytes[1] = 0x09; 1531 mac_addr->addr_bytes[2] = 0xC0; 1532 /* Force indication of locally assigned MAC address. */ 1533 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR; 1534 /* Generate the last 3 bytes of the MAC address with a random number. */ 1535 random = rte_rand(); 1536 memcpy(&mac_addr->addr_bytes[3], &random, 3); 1537 } 1538 1539 /* 1540 * Virtual Function device init 1541 */ 1542 static int 1543 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev) 1544 { 1545 int diag; 1546 uint32_t tc, tcs; 1547 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1548 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1549 struct ixgbe_hw *hw = 1550 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1551 struct ixgbe_vfta *shadow_vfta = 1552 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private); 1553 struct ixgbe_hwstrip *hwstrip = 1554 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private); 1555 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr; 1556 1557 PMD_INIT_FUNC_TRACE(); 1558 1559 eth_dev->dev_ops = &ixgbevf_eth_dev_ops; 1560 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts; 1561 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts; 1562 1563 /* for secondary processes, we don't initialise any further as primary 1564 * has already done this work. Only check we don't need a different 1565 * RX function 1566 */ 1567 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1568 struct ixgbe_tx_queue *txq; 1569 /* TX queue function in primary, set by last queue initialized 1570 * Tx queue may not initialized by primary process 1571 */ 1572 if (eth_dev->data->tx_queues) { 1573 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1]; 1574 ixgbe_set_tx_function(eth_dev, txq); 1575 } else { 1576 /* Use default TX function if we get here */ 1577 PMD_INIT_LOG(NOTICE, 1578 "No TX queues configured yet. Using default TX function."); 1579 } 1580 1581 ixgbe_set_rx_function(eth_dev); 1582 1583 return 0; 1584 } 1585 1586 rte_eth_copy_pci_info(eth_dev, pci_dev); 1587 1588 hw->device_id = pci_dev->id.device_id; 1589 hw->vendor_id = pci_dev->id.vendor_id; 1590 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; 1591 1592 /* initialize the vfta */ 1593 memset(shadow_vfta, 0, sizeof(*shadow_vfta)); 1594 1595 /* initialize the hw strip bitmap*/ 1596 memset(hwstrip, 0, sizeof(*hwstrip)); 1597 1598 /* Initialize the shared code (base driver) */ 1599 diag = ixgbe_init_shared_code(hw); 1600 if (diag != IXGBE_SUCCESS) { 1601 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag); 1602 return -EIO; 1603 } 1604 1605 /* init_mailbox_params */ 1606 hw->mbx.ops.init_params(hw); 1607 1608 /* Reset the hw statistics */ 1609 ixgbevf_dev_stats_reset(eth_dev); 1610 1611 /* Disable the interrupts for VF */ 1612 ixgbevf_intr_disable(eth_dev); 1613 1614 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ 1615 diag = hw->mac.ops.reset_hw(hw); 1616 1617 /* 1618 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when 1619 * the underlying PF driver has not assigned a MAC address to the VF. 1620 * In this case, assign a random MAC address. 1621 */ 1622 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) { 1623 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1624 /* 1625 * This error code will be propagated to the app by 1626 * rte_eth_dev_reset, so use a public error code rather than 1627 * the internal-only IXGBE_ERR_RESET_FAILED 1628 */ 1629 return -EAGAIN; 1630 } 1631 1632 /* negotiate mailbox API version to use with the PF. */ 1633 ixgbevf_negotiate_api(hw); 1634 1635 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */ 1636 ixgbevf_get_queues(hw, &tcs, &tc); 1637 1638 /* Allocate memory for storing MAC addresses */ 1639 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN * 1640 hw->mac.num_rar_entries, 0); 1641 if (eth_dev->data->mac_addrs == NULL) { 1642 PMD_INIT_LOG(ERR, 1643 "Failed to allocate %u bytes needed to store " 1644 "MAC addresses", 1645 ETHER_ADDR_LEN * hw->mac.num_rar_entries); 1646 return -ENOMEM; 1647 } 1648 1649 /* Generate a random MAC address, if none was assigned by PF. */ 1650 if (is_zero_ether_addr(perm_addr)) { 1651 generate_random_mac_addr(perm_addr); 1652 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1); 1653 if (diag) { 1654 rte_free(eth_dev->data->mac_addrs); 1655 eth_dev->data->mac_addrs = NULL; 1656 return diag; 1657 } 1658 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF"); 1659 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address " 1660 "%02x:%02x:%02x:%02x:%02x:%02x", 1661 perm_addr->addr_bytes[0], 1662 perm_addr->addr_bytes[1], 1663 perm_addr->addr_bytes[2], 1664 perm_addr->addr_bytes[3], 1665 perm_addr->addr_bytes[4], 1666 perm_addr->addr_bytes[5]); 1667 } 1668 1669 /* Copy the permanent MAC address */ 1670 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]); 1671 1672 /* reset the hardware with the new settings */ 1673 diag = hw->mac.ops.start_hw(hw); 1674 switch (diag) { 1675 case 0: 1676 break; 1677 1678 default: 1679 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag); 1680 return -EIO; 1681 } 1682 1683 rte_intr_callback_register(intr_handle, 1684 ixgbevf_dev_interrupt_handler, eth_dev); 1685 rte_intr_enable(intr_handle); 1686 ixgbevf_intr_enable(eth_dev); 1687 1688 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", 1689 eth_dev->data->port_id, pci_dev->id.vendor_id, 1690 pci_dev->id.device_id, "ixgbe_mac_82599_vf"); 1691 1692 return 0; 1693 } 1694 1695 /* Virtual Function device uninit */ 1696 1697 static int 1698 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev) 1699 { 1700 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1701 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1702 struct ixgbe_hw *hw; 1703 1704 PMD_INIT_FUNC_TRACE(); 1705 1706 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1707 return 0; 1708 1709 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 1710 1711 if (hw->adapter_stopped == 0) 1712 ixgbevf_dev_close(eth_dev); 1713 1714 eth_dev->dev_ops = NULL; 1715 eth_dev->rx_pkt_burst = NULL; 1716 eth_dev->tx_pkt_burst = NULL; 1717 1718 /* Disable the interrupts for VF */ 1719 ixgbevf_intr_disable(eth_dev); 1720 1721 rte_intr_disable(intr_handle); 1722 rte_intr_callback_unregister(intr_handle, 1723 ixgbevf_dev_interrupt_handler, eth_dev); 1724 1725 return 0; 1726 } 1727 1728 static int 1729 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1730 struct rte_pci_device *pci_dev) 1731 { 1732 char name[RTE_ETH_NAME_MAX_LEN]; 1733 struct rte_eth_dev *pf_ethdev; 1734 struct rte_eth_devargs eth_da; 1735 int i, retval; 1736 1737 if (pci_dev->device.devargs) { 1738 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args, 1739 ð_da); 1740 if (retval) 1741 return retval; 1742 } else 1743 memset(ð_da, 0, sizeof(eth_da)); 1744 1745 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 1746 sizeof(struct ixgbe_adapter), 1747 eth_dev_pci_specific_init, pci_dev, 1748 eth_ixgbe_dev_init, NULL); 1749 1750 if (retval || eth_da.nb_representor_ports < 1) 1751 return retval; 1752 1753 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1754 if (pf_ethdev == NULL) 1755 return -ENODEV; 1756 1757 /* probe VF representor ports */ 1758 for (i = 0; i < eth_da.nb_representor_ports; i++) { 1759 struct ixgbe_vf_info *vfinfo; 1760 struct ixgbe_vf_representor representor; 1761 1762 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA( 1763 pf_ethdev->data->dev_private); 1764 if (vfinfo == NULL) { 1765 PMD_DRV_LOG(ERR, 1766 "no virtual functions supported by PF"); 1767 break; 1768 } 1769 1770 representor.vf_id = eth_da.representor_ports[i]; 1771 representor.switch_domain_id = vfinfo->switch_domain_id; 1772 representor.pf_ethdev = pf_ethdev; 1773 1774 /* representor port net_bdf_port */ 1775 snprintf(name, sizeof(name), "net_%s_representor_%d", 1776 pci_dev->device.name, 1777 eth_da.representor_ports[i]); 1778 1779 retval = rte_eth_dev_create(&pci_dev->device, name, 1780 sizeof(struct ixgbe_vf_representor), NULL, NULL, 1781 ixgbe_vf_representor_init, &representor); 1782 1783 if (retval) 1784 PMD_DRV_LOG(ERR, "failed to create ixgbe vf " 1785 "representor %s.", name); 1786 } 1787 1788 return 0; 1789 } 1790 1791 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev) 1792 { 1793 struct rte_eth_dev *ethdev; 1794 1795 ethdev = rte_eth_dev_allocated(pci_dev->device.name); 1796 if (!ethdev) 1797 return -ENODEV; 1798 1799 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 1800 return rte_eth_dev_destroy(ethdev, ixgbe_vf_representor_uninit); 1801 else 1802 return rte_eth_dev_destroy(ethdev, eth_ixgbe_dev_uninit); 1803 } 1804 1805 static struct rte_pci_driver rte_ixgbe_pmd = { 1806 .id_table = pci_id_ixgbe_map, 1807 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 1808 RTE_PCI_DRV_IOVA_AS_VA, 1809 .probe = eth_ixgbe_pci_probe, 1810 .remove = eth_ixgbe_pci_remove, 1811 }; 1812 1813 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1814 struct rte_pci_device *pci_dev) 1815 { 1816 return rte_eth_dev_pci_generic_probe(pci_dev, 1817 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init); 1818 } 1819 1820 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev) 1821 { 1822 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit); 1823 } 1824 1825 /* 1826 * virtual function driver struct 1827 */ 1828 static struct rte_pci_driver rte_ixgbevf_pmd = { 1829 .id_table = pci_id_ixgbevf_map, 1830 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, 1831 .probe = eth_ixgbevf_pci_probe, 1832 .remove = eth_ixgbevf_pci_remove, 1833 }; 1834 1835 static int 1836 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 1837 { 1838 struct ixgbe_hw *hw = 1839 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1840 struct ixgbe_vfta *shadow_vfta = 1841 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1842 uint32_t vfta; 1843 uint32_t vid_idx; 1844 uint32_t vid_bit; 1845 1846 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 1847 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 1848 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx)); 1849 if (on) 1850 vfta |= vid_bit; 1851 else 1852 vfta &= ~vid_bit; 1853 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta); 1854 1855 /* update local VFTA copy */ 1856 shadow_vfta->vfta[vid_idx] = vfta; 1857 1858 return 0; 1859 } 1860 1861 static void 1862 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 1863 { 1864 if (on) 1865 ixgbe_vlan_hw_strip_enable(dev, queue); 1866 else 1867 ixgbe_vlan_hw_strip_disable(dev, queue); 1868 } 1869 1870 static int 1871 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1872 enum rte_vlan_type vlan_type, 1873 uint16_t tpid) 1874 { 1875 struct ixgbe_hw *hw = 1876 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1877 int ret = 0; 1878 uint32_t reg; 1879 uint32_t qinq; 1880 1881 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1882 qinq &= IXGBE_DMATXCTL_GDV; 1883 1884 switch (vlan_type) { 1885 case ETH_VLAN_TYPE_INNER: 1886 if (qinq) { 1887 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1888 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1889 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1890 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1891 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1892 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1893 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1894 } else { 1895 ret = -ENOTSUP; 1896 PMD_DRV_LOG(ERR, "Inner type is not supported" 1897 " by single VLAN"); 1898 } 1899 break; 1900 case ETH_VLAN_TYPE_OUTER: 1901 if (qinq) { 1902 /* Only the high 16-bits is valid */ 1903 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid << 1904 IXGBE_EXVET_VET_EXT_SHIFT); 1905 } else { 1906 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1907 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid; 1908 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg); 1909 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 1910 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK)) 1911 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT); 1912 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 1913 } 1914 1915 break; 1916 default: 1917 ret = -EINVAL; 1918 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type); 1919 break; 1920 } 1921 1922 return ret; 1923 } 1924 1925 void 1926 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev) 1927 { 1928 struct ixgbe_hw *hw = 1929 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1930 uint32_t vlnctrl; 1931 1932 PMD_INIT_FUNC_TRACE(); 1933 1934 /* Filter Table Disable */ 1935 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1936 vlnctrl &= ~IXGBE_VLNCTRL_VFE; 1937 1938 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1939 } 1940 1941 void 1942 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev) 1943 { 1944 struct ixgbe_hw *hw = 1945 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1946 struct ixgbe_vfta *shadow_vfta = 1947 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 1948 uint32_t vlnctrl; 1949 uint16_t i; 1950 1951 PMD_INIT_FUNC_TRACE(); 1952 1953 /* Filter Table Enable */ 1954 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 1955 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; 1956 vlnctrl |= IXGBE_VLNCTRL_VFE; 1957 1958 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); 1959 1960 /* write whatever is in local vfta copy */ 1961 for (i = 0; i < IXGBE_VFTA_SIZE; i++) 1962 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]); 1963 } 1964 1965 static void 1966 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on) 1967 { 1968 struct ixgbe_hwstrip *hwstrip = 1969 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private); 1970 struct ixgbe_rx_queue *rxq; 1971 1972 if (queue >= IXGBE_MAX_RX_QUEUE_NUM) 1973 return; 1974 1975 if (on) 1976 IXGBE_SET_HWSTRIP(hwstrip, queue); 1977 else 1978 IXGBE_CLEAR_HWSTRIP(hwstrip, queue); 1979 1980 if (queue >= dev->data->nb_rx_queues) 1981 return; 1982 1983 rxq = dev->data->rx_queues[queue]; 1984 1985 if (on) { 1986 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 1987 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 1988 } else { 1989 rxq->vlan_flags = PKT_RX_VLAN; 1990 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 1991 } 1992 } 1993 1994 static void 1995 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue) 1996 { 1997 struct ixgbe_hw *hw = 1998 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 1999 uint32_t ctrl; 2000 2001 PMD_INIT_FUNC_TRACE(); 2002 2003 if (hw->mac.type == ixgbe_mac_82598EB) { 2004 /* No queue level support */ 2005 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2006 return; 2007 } 2008 2009 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2010 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2011 ctrl &= ~IXGBE_RXDCTL_VME; 2012 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2013 2014 /* record those setting for HW strip per queue */ 2015 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0); 2016 } 2017 2018 static void 2019 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue) 2020 { 2021 struct ixgbe_hw *hw = 2022 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2023 uint32_t ctrl; 2024 2025 PMD_INIT_FUNC_TRACE(); 2026 2027 if (hw->mac.type == ixgbe_mac_82598EB) { 2028 /* No queue level supported */ 2029 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip"); 2030 return; 2031 } 2032 2033 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */ 2034 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 2035 ctrl |= IXGBE_RXDCTL_VME; 2036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 2037 2038 /* record those setting for HW strip per queue */ 2039 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1); 2040 } 2041 2042 static void 2043 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev) 2044 { 2045 struct ixgbe_hw *hw = 2046 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2047 uint32_t ctrl; 2048 2049 PMD_INIT_FUNC_TRACE(); 2050 2051 /* DMATXCTRL: Geric Double VLAN Disable */ 2052 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2053 ctrl &= ~IXGBE_DMATXCTL_GDV; 2054 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2055 2056 /* CTRL_EXT: Global Double VLAN Disable */ 2057 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2058 ctrl &= ~IXGBE_EXTENDED_VLAN; 2059 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2060 2061 } 2062 2063 static void 2064 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev) 2065 { 2066 struct ixgbe_hw *hw = 2067 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2068 uint32_t ctrl; 2069 2070 PMD_INIT_FUNC_TRACE(); 2071 2072 /* DMATXCTRL: Geric Double VLAN Enable */ 2073 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 2074 ctrl |= IXGBE_DMATXCTL_GDV; 2075 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl); 2076 2077 /* CTRL_EXT: Global Double VLAN Enable */ 2078 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 2079 ctrl |= IXGBE_EXTENDED_VLAN; 2080 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl); 2081 2082 /* Clear pooling mode of PFVTCTL. It's required by X550. */ 2083 if (hw->mac.type == ixgbe_mac_X550 || 2084 hw->mac.type == ixgbe_mac_X550EM_x || 2085 hw->mac.type == ixgbe_mac_X550EM_a) { 2086 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2087 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 2088 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 2089 } 2090 2091 /* 2092 * VET EXT field in the EXVET register = 0x8100 by default 2093 * So no need to change. Same to VT field of DMATXCTL register 2094 */ 2095 } 2096 2097 void 2098 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev) 2099 { 2100 struct ixgbe_hw *hw = 2101 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2102 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 2103 uint32_t ctrl; 2104 uint16_t i; 2105 struct ixgbe_rx_queue *rxq; 2106 bool on; 2107 2108 PMD_INIT_FUNC_TRACE(); 2109 2110 if (hw->mac.type == ixgbe_mac_82598EB) { 2111 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2112 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2113 ctrl |= IXGBE_VLNCTRL_VME; 2114 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2115 } else { 2116 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2117 ctrl &= ~IXGBE_VLNCTRL_VME; 2118 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl); 2119 } 2120 } else { 2121 /* 2122 * Other 10G NIC, the VLAN strip can be setup 2123 * per queue in RXDCTL 2124 */ 2125 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2126 rxq = dev->data->rx_queues[i]; 2127 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx)); 2128 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 2129 ctrl |= IXGBE_RXDCTL_VME; 2130 on = TRUE; 2131 } else { 2132 ctrl &= ~IXGBE_RXDCTL_VME; 2133 on = FALSE; 2134 } 2135 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl); 2136 2137 /* record those setting for HW strip per queue */ 2138 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on); 2139 } 2140 } 2141 } 2142 2143 static void 2144 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask) 2145 { 2146 uint16_t i; 2147 struct rte_eth_rxmode *rxmode; 2148 struct ixgbe_rx_queue *rxq; 2149 2150 if (mask & ETH_VLAN_STRIP_MASK) { 2151 rxmode = &dev->data->dev_conf.rxmode; 2152 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 2153 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2154 rxq = dev->data->rx_queues[i]; 2155 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 2156 } 2157 else 2158 for (i = 0; i < dev->data->nb_rx_queues; i++) { 2159 rxq = dev->data->rx_queues[i]; 2160 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 2161 } 2162 } 2163 } 2164 2165 static int 2166 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask) 2167 { 2168 struct rte_eth_rxmode *rxmode; 2169 rxmode = &dev->data->dev_conf.rxmode; 2170 2171 if (mask & ETH_VLAN_STRIP_MASK) { 2172 ixgbe_vlan_hw_strip_config(dev); 2173 } 2174 2175 if (mask & ETH_VLAN_FILTER_MASK) { 2176 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 2177 ixgbe_vlan_hw_filter_enable(dev); 2178 else 2179 ixgbe_vlan_hw_filter_disable(dev); 2180 } 2181 2182 if (mask & ETH_VLAN_EXTEND_MASK) { 2183 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2184 ixgbe_vlan_hw_extend_enable(dev); 2185 else 2186 ixgbe_vlan_hw_extend_disable(dev); 2187 } 2188 2189 return 0; 2190 } 2191 2192 static int 2193 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 2194 { 2195 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 2196 2197 ixgbe_vlan_offload_config(dev, mask); 2198 2199 return 0; 2200 } 2201 2202 static void 2203 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev) 2204 { 2205 struct ixgbe_hw *hw = 2206 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2207 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */ 2208 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); 2209 2210 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */ 2211 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl); 2212 } 2213 2214 static int 2215 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q) 2216 { 2217 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2218 2219 switch (nb_rx_q) { 2220 case 1: 2221 case 2: 2222 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS; 2223 break; 2224 case 4: 2225 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS; 2226 break; 2227 default: 2228 return -EINVAL; 2229 } 2230 2231 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 2232 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2233 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = 2234 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2235 return 0; 2236 } 2237 2238 static int 2239 ixgbe_check_mq_mode(struct rte_eth_dev *dev) 2240 { 2241 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 2242 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2243 uint16_t nb_rx_q = dev->data->nb_rx_queues; 2244 uint16_t nb_tx_q = dev->data->nb_tx_queues; 2245 2246 if (RTE_ETH_DEV_SRIOV(dev).active != 0) { 2247 /* check multi-queue mode */ 2248 switch (dev_conf->rxmode.mq_mode) { 2249 case ETH_MQ_RX_VMDQ_DCB: 2250 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV"); 2251 break; 2252 case ETH_MQ_RX_VMDQ_DCB_RSS: 2253 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */ 2254 PMD_INIT_LOG(ERR, "SRIOV active," 2255 " unsupported mq_mode rx %d.", 2256 dev_conf->rxmode.mq_mode); 2257 return -EINVAL; 2258 case ETH_MQ_RX_RSS: 2259 case ETH_MQ_RX_VMDQ_RSS: 2260 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS; 2261 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) 2262 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) { 2263 PMD_INIT_LOG(ERR, "SRIOV is active," 2264 " invalid queue number" 2265 " for VMDQ RSS, allowed" 2266 " value are 1, 2 or 4."); 2267 return -EINVAL; 2268 } 2269 break; 2270 case ETH_MQ_RX_VMDQ_ONLY: 2271 case ETH_MQ_RX_NONE: 2272 /* if nothing mq mode configure, use default scheme */ 2273 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY; 2274 break; 2275 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/ 2276 /* SRIOV only works in VMDq enable mode */ 2277 PMD_INIT_LOG(ERR, "SRIOV is active," 2278 " wrong mq_mode rx %d.", 2279 dev_conf->rxmode.mq_mode); 2280 return -EINVAL; 2281 } 2282 2283 switch (dev_conf->txmode.mq_mode) { 2284 case ETH_MQ_TX_VMDQ_DCB: 2285 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV"); 2286 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB; 2287 break; 2288 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */ 2289 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY; 2290 break; 2291 } 2292 2293 /* check valid queue number */ 2294 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) || 2295 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) { 2296 PMD_INIT_LOG(ERR, "SRIOV is active," 2297 " nb_rx_q=%d nb_tx_q=%d queue number" 2298 " must be less than or equal to %d.", 2299 nb_rx_q, nb_tx_q, 2300 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool); 2301 return -EINVAL; 2302 } 2303 } else { 2304 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) { 2305 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is" 2306 " not supported."); 2307 return -EINVAL; 2308 } 2309 /* check configuration for vmdb+dcb mode */ 2310 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) { 2311 const struct rte_eth_vmdq_dcb_conf *conf; 2312 2313 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2314 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.", 2315 IXGBE_VMDQ_DCB_NB_QUEUES); 2316 return -EINVAL; 2317 } 2318 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf; 2319 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2320 conf->nb_queue_pools == ETH_32_POOLS)) { 2321 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2322 " nb_queue_pools must be %d or %d.", 2323 ETH_16_POOLS, ETH_32_POOLS); 2324 return -EINVAL; 2325 } 2326 } 2327 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) { 2328 const struct rte_eth_vmdq_dcb_tx_conf *conf; 2329 2330 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) { 2331 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d", 2332 IXGBE_VMDQ_DCB_NB_QUEUES); 2333 return -EINVAL; 2334 } 2335 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf; 2336 if (!(conf->nb_queue_pools == ETH_16_POOLS || 2337 conf->nb_queue_pools == ETH_32_POOLS)) { 2338 PMD_INIT_LOG(ERR, "VMDQ+DCB selected," 2339 " nb_queue_pools != %d and" 2340 " nb_queue_pools != %d.", 2341 ETH_16_POOLS, ETH_32_POOLS); 2342 return -EINVAL; 2343 } 2344 } 2345 2346 /* For DCB mode check our configuration before we go further */ 2347 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) { 2348 const struct rte_eth_dcb_rx_conf *conf; 2349 2350 conf = &dev_conf->rx_adv_conf.dcb_rx_conf; 2351 if (!(conf->nb_tcs == ETH_4_TCS || 2352 conf->nb_tcs == ETH_8_TCS)) { 2353 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2354 " and nb_tcs != %d.", 2355 ETH_4_TCS, ETH_8_TCS); 2356 return -EINVAL; 2357 } 2358 } 2359 2360 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) { 2361 const struct rte_eth_dcb_tx_conf *conf; 2362 2363 conf = &dev_conf->tx_adv_conf.dcb_tx_conf; 2364 if (!(conf->nb_tcs == ETH_4_TCS || 2365 conf->nb_tcs == ETH_8_TCS)) { 2366 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d" 2367 " and nb_tcs != %d.", 2368 ETH_4_TCS, ETH_8_TCS); 2369 return -EINVAL; 2370 } 2371 } 2372 2373 /* 2374 * When DCB/VT is off, maximum number of queues changes, 2375 * except for 82598EB, which remains constant. 2376 */ 2377 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 2378 hw->mac.type != ixgbe_mac_82598EB) { 2379 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) { 2380 PMD_INIT_LOG(ERR, 2381 "Neither VT nor DCB are enabled, " 2382 "nb_tx_q > %d.", 2383 IXGBE_NONE_MODE_TX_NB_QUEUES); 2384 return -EINVAL; 2385 } 2386 } 2387 } 2388 return 0; 2389 } 2390 2391 static int 2392 ixgbe_dev_configure(struct rte_eth_dev *dev) 2393 { 2394 struct ixgbe_interrupt *intr = 2395 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2396 struct ixgbe_adapter *adapter = 2397 (struct ixgbe_adapter *)dev->data->dev_private; 2398 int ret; 2399 2400 PMD_INIT_FUNC_TRACE(); 2401 /* multipe queue mode checking */ 2402 ret = ixgbe_check_mq_mode(dev); 2403 if (ret != 0) { 2404 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.", 2405 ret); 2406 return ret; 2407 } 2408 2409 /* set flag to update link status after init */ 2410 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 2411 2412 /* 2413 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 2414 * allocation or vector Rx preconditions we will reset it. 2415 */ 2416 adapter->rx_bulk_alloc_allowed = true; 2417 adapter->rx_vec_allowed = true; 2418 2419 return 0; 2420 } 2421 2422 static void 2423 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev) 2424 { 2425 struct ixgbe_hw *hw = 2426 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2427 struct ixgbe_interrupt *intr = 2428 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 2429 uint32_t gpie; 2430 2431 /* only set up it on X550EM_X */ 2432 if (hw->mac.type == ixgbe_mac_X550EM_x) { 2433 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 2434 gpie |= IXGBE_SDP0_GPIEN_X550EM_x; 2435 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 2436 if (hw->phy.type == ixgbe_phy_x550em_ext_t) 2437 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x; 2438 } 2439 } 2440 2441 int 2442 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf, 2443 uint16_t tx_rate, uint64_t q_msk) 2444 { 2445 struct ixgbe_hw *hw; 2446 struct ixgbe_vf_info *vfinfo; 2447 struct rte_eth_link link; 2448 uint8_t nb_q_per_pool; 2449 uint32_t queue_stride; 2450 uint32_t queue_idx, idx = 0, vf_idx; 2451 uint32_t queue_end; 2452 uint16_t total_rate = 0; 2453 struct rte_pci_device *pci_dev; 2454 2455 pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2456 rte_eth_link_get_nowait(dev->data->port_id, &link); 2457 2458 if (vf >= pci_dev->max_vfs) 2459 return -EINVAL; 2460 2461 if (tx_rate > link.link_speed) 2462 return -EINVAL; 2463 2464 if (q_msk == 0) 2465 return 0; 2466 2467 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2468 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private)); 2469 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool; 2470 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active; 2471 queue_idx = vf * queue_stride; 2472 queue_end = queue_idx + nb_q_per_pool - 1; 2473 if (queue_end >= hw->mac.max_tx_queues) 2474 return -EINVAL; 2475 2476 if (vfinfo) { 2477 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) { 2478 if (vf_idx == vf) 2479 continue; 2480 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate); 2481 idx++) 2482 total_rate += vfinfo[vf_idx].tx_rate[idx]; 2483 } 2484 } else { 2485 return -EINVAL; 2486 } 2487 2488 /* Store tx_rate for this vf. */ 2489 for (idx = 0; idx < nb_q_per_pool; idx++) { 2490 if (((uint64_t)0x1 << idx) & q_msk) { 2491 if (vfinfo[vf].tx_rate[idx] != tx_rate) 2492 vfinfo[vf].tx_rate[idx] = tx_rate; 2493 total_rate += tx_rate; 2494 } 2495 } 2496 2497 if (total_rate > dev->data->dev_link.link_speed) { 2498 /* Reset stored TX rate of the VF if it causes exceed 2499 * link speed. 2500 */ 2501 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate)); 2502 return -EINVAL; 2503 } 2504 2505 /* Set RTTBCNRC of each queue/pool for vf X */ 2506 for (; queue_idx <= queue_end; queue_idx++) { 2507 if (0x1 & q_msk) 2508 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate); 2509 q_msk = q_msk >> 1; 2510 } 2511 2512 return 0; 2513 } 2514 2515 /* 2516 * Configure device link speed and setup link. 2517 * It returns 0 on success. 2518 */ 2519 static int 2520 ixgbe_dev_start(struct rte_eth_dev *dev) 2521 { 2522 struct ixgbe_hw *hw = 2523 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2524 struct ixgbe_vf_info *vfinfo = 2525 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2526 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2527 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2528 uint32_t intr_vector = 0; 2529 int err, link_up = 0, negotiate = 0; 2530 uint32_t speed = 0; 2531 uint32_t allowed_speeds = 0; 2532 int mask = 0; 2533 int status; 2534 uint16_t vf, idx; 2535 uint32_t *link_speeds; 2536 struct ixgbe_tm_conf *tm_conf = 2537 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2538 2539 PMD_INIT_FUNC_TRACE(); 2540 2541 /* IXGBE devices don't support: 2542 * - half duplex (checked afterwards for valid speeds) 2543 * - fixed speed: TODO implement 2544 */ 2545 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 2546 PMD_INIT_LOG(ERR, 2547 "Invalid link_speeds for port %u, fix speed not supported", 2548 dev->data->port_id); 2549 return -EINVAL; 2550 } 2551 2552 /* Stop the link setup handler before resetting the HW. */ 2553 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2554 2555 /* disable uio/vfio intr/eventfd mapping */ 2556 rte_intr_disable(intr_handle); 2557 2558 /* stop adapter */ 2559 hw->adapter_stopped = 0; 2560 ixgbe_stop_adapter(hw); 2561 2562 /* reinitialize adapter 2563 * this calls reset and start 2564 */ 2565 status = ixgbe_pf_reset_hw(hw); 2566 if (status != 0) 2567 return -1; 2568 hw->mac.ops.start_hw(hw); 2569 hw->mac.get_link_status = true; 2570 2571 /* configure PF module if SRIOV enabled */ 2572 ixgbe_pf_host_configure(dev); 2573 2574 ixgbe_dev_phy_intr_setup(dev); 2575 2576 /* check and configure queue intr-vector mapping */ 2577 if ((rte_intr_cap_multiple(intr_handle) || 2578 !RTE_ETH_DEV_SRIOV(dev).active) && 2579 dev->data->dev_conf.intr_conf.rxq != 0) { 2580 intr_vector = dev->data->nb_rx_queues; 2581 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) { 2582 PMD_INIT_LOG(ERR, "At most %d intr queues supported", 2583 IXGBE_MAX_INTR_QUEUE_NUM); 2584 return -ENOTSUP; 2585 } 2586 if (rte_intr_efd_enable(intr_handle, intr_vector)) 2587 return -1; 2588 } 2589 2590 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 2591 intr_handle->intr_vec = 2592 rte_zmalloc("intr_vec", 2593 dev->data->nb_rx_queues * sizeof(int), 0); 2594 if (intr_handle->intr_vec == NULL) { 2595 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 2596 " intr_vec", dev->data->nb_rx_queues); 2597 return -ENOMEM; 2598 } 2599 } 2600 2601 /* confiugre msix for sleep until rx interrupt */ 2602 ixgbe_configure_msix(dev); 2603 2604 /* initialize transmission unit */ 2605 ixgbe_dev_tx_init(dev); 2606 2607 /* This can fail when allocating mbufs for descriptor rings */ 2608 err = ixgbe_dev_rx_init(dev); 2609 if (err) { 2610 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware"); 2611 goto error; 2612 } 2613 2614 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 2615 ETH_VLAN_EXTEND_MASK; 2616 err = ixgbe_vlan_offload_config(dev, mask); 2617 if (err) { 2618 PMD_INIT_LOG(ERR, "Unable to set VLAN offload"); 2619 goto error; 2620 } 2621 2622 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) { 2623 /* Enable vlan filtering for VMDq */ 2624 ixgbe_vmdq_vlan_hw_filter_enable(dev); 2625 } 2626 2627 /* Configure DCB hw */ 2628 ixgbe_configure_dcb(dev); 2629 2630 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) { 2631 err = ixgbe_fdir_configure(dev); 2632 if (err) 2633 goto error; 2634 } 2635 2636 /* Restore vf rate limit */ 2637 if (vfinfo != NULL) { 2638 for (vf = 0; vf < pci_dev->max_vfs; vf++) 2639 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++) 2640 if (vfinfo[vf].tx_rate[idx] != 0) 2641 ixgbe_set_vf_rate_limit( 2642 dev, vf, 2643 vfinfo[vf].tx_rate[idx], 2644 1 << idx); 2645 } 2646 2647 ixgbe_restore_statistics_mapping(dev); 2648 2649 err = ixgbe_dev_rxtx_start(dev); 2650 if (err < 0) { 2651 PMD_INIT_LOG(ERR, "Unable to start rxtx queues"); 2652 goto error; 2653 } 2654 2655 /* Skip link setup if loopback mode is enabled for 82599. */ 2656 if (hw->mac.type == ixgbe_mac_82599EB && 2657 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX) 2658 goto skip_link_setup; 2659 2660 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) { 2661 err = hw->mac.ops.setup_sfp(hw); 2662 if (err) 2663 goto error; 2664 } 2665 2666 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2667 /* Turn on the copper */ 2668 ixgbe_set_phy_power(hw, true); 2669 } else { 2670 /* Turn on the laser */ 2671 ixgbe_enable_tx_laser(hw); 2672 } 2673 2674 err = ixgbe_check_link(hw, &speed, &link_up, 0); 2675 if (err) 2676 goto error; 2677 dev->data->dev_link.link_status = link_up; 2678 2679 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate); 2680 if (err) 2681 goto error; 2682 2683 switch (hw->mac.type) { 2684 case ixgbe_mac_X550: 2685 case ixgbe_mac_X550EM_x: 2686 case ixgbe_mac_X550EM_a: 2687 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2688 ETH_LINK_SPEED_2_5G | ETH_LINK_SPEED_5G | 2689 ETH_LINK_SPEED_10G; 2690 break; 2691 default: 2692 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G | 2693 ETH_LINK_SPEED_10G; 2694 } 2695 2696 link_speeds = &dev->data->dev_conf.link_speeds; 2697 if (*link_speeds & ~allowed_speeds) { 2698 PMD_INIT_LOG(ERR, "Invalid link setting"); 2699 goto error; 2700 } 2701 2702 speed = 0x0; 2703 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) { 2704 switch (hw->mac.type) { 2705 case ixgbe_mac_82598EB: 2706 speed = IXGBE_LINK_SPEED_82598_AUTONEG; 2707 break; 2708 case ixgbe_mac_82599EB: 2709 case ixgbe_mac_X540: 2710 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2711 break; 2712 case ixgbe_mac_X550: 2713 case ixgbe_mac_X550EM_x: 2714 case ixgbe_mac_X550EM_a: 2715 speed = IXGBE_LINK_SPEED_X550_AUTONEG; 2716 break; 2717 default: 2718 speed = IXGBE_LINK_SPEED_82599_AUTONEG; 2719 } 2720 } else { 2721 if (*link_speeds & ETH_LINK_SPEED_10G) 2722 speed |= IXGBE_LINK_SPEED_10GB_FULL; 2723 if (*link_speeds & ETH_LINK_SPEED_5G) 2724 speed |= IXGBE_LINK_SPEED_5GB_FULL; 2725 if (*link_speeds & ETH_LINK_SPEED_2_5G) 2726 speed |= IXGBE_LINK_SPEED_2_5GB_FULL; 2727 if (*link_speeds & ETH_LINK_SPEED_1G) 2728 speed |= IXGBE_LINK_SPEED_1GB_FULL; 2729 if (*link_speeds & ETH_LINK_SPEED_100M) 2730 speed |= IXGBE_LINK_SPEED_100_FULL; 2731 } 2732 2733 err = ixgbe_setup_link(hw, speed, link_up); 2734 if (err) 2735 goto error; 2736 2737 skip_link_setup: 2738 2739 if (rte_intr_allow_others(intr_handle)) { 2740 /* check if lsc interrupt is enabled */ 2741 if (dev->data->dev_conf.intr_conf.lsc != 0) 2742 ixgbe_dev_lsc_interrupt_setup(dev, TRUE); 2743 else 2744 ixgbe_dev_lsc_interrupt_setup(dev, FALSE); 2745 ixgbe_dev_macsec_interrupt_setup(dev); 2746 } else { 2747 rte_intr_callback_unregister(intr_handle, 2748 ixgbe_dev_interrupt_handler, dev); 2749 if (dev->data->dev_conf.intr_conf.lsc != 0) 2750 PMD_INIT_LOG(INFO, "lsc won't enable because of" 2751 " no intr multiplex"); 2752 } 2753 2754 /* check if rxq interrupt is enabled */ 2755 if (dev->data->dev_conf.intr_conf.rxq != 0 && 2756 rte_intr_dp_is_en(intr_handle)) 2757 ixgbe_dev_rxq_interrupt_setup(dev); 2758 2759 /* enable uio/vfio intr/eventfd mapping */ 2760 rte_intr_enable(intr_handle); 2761 2762 /* resume enabled intr since hw reset */ 2763 ixgbe_enable_intr(dev); 2764 ixgbe_l2_tunnel_conf(dev); 2765 ixgbe_filter_restore(dev); 2766 2767 if (tm_conf->root && !tm_conf->committed) 2768 PMD_DRV_LOG(WARNING, 2769 "please call hierarchy_commit() " 2770 "before starting the port"); 2771 2772 /* 2773 * Update link status right before return, because it may 2774 * start link configuration process in a separate thread. 2775 */ 2776 ixgbe_dev_link_update(dev, 0); 2777 2778 return 0; 2779 2780 error: 2781 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err); 2782 ixgbe_dev_clear_queues(dev); 2783 return -EIO; 2784 } 2785 2786 /* 2787 * Stop device: disable rx and tx functions to allow for reconfiguring. 2788 */ 2789 static void 2790 ixgbe_dev_stop(struct rte_eth_dev *dev) 2791 { 2792 struct rte_eth_link link; 2793 struct ixgbe_hw *hw = 2794 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2795 struct ixgbe_vf_info *vfinfo = 2796 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); 2797 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 2798 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 2799 int vf; 2800 struct ixgbe_tm_conf *tm_conf = 2801 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); 2802 2803 PMD_INIT_FUNC_TRACE(); 2804 2805 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 2806 2807 /* disable interrupts */ 2808 ixgbe_disable_intr(hw); 2809 2810 /* reset the NIC */ 2811 ixgbe_pf_reset_hw(hw); 2812 hw->adapter_stopped = 0; 2813 2814 /* stop adapter */ 2815 ixgbe_stop_adapter(hw); 2816 2817 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++) 2818 vfinfo[vf].clear_to_send = false; 2819 2820 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2821 /* Turn off the copper */ 2822 ixgbe_set_phy_power(hw, false); 2823 } else { 2824 /* Turn off the laser */ 2825 ixgbe_disable_tx_laser(hw); 2826 } 2827 2828 ixgbe_dev_clear_queues(dev); 2829 2830 /* Clear stored conf */ 2831 dev->data->scattered_rx = 0; 2832 dev->data->lro = 0; 2833 2834 /* Clear recorded link status */ 2835 memset(&link, 0, sizeof(link)); 2836 rte_eth_linkstatus_set(dev, &link); 2837 2838 if (!rte_intr_allow_others(intr_handle)) 2839 /* resume to the default handler */ 2840 rte_intr_callback_register(intr_handle, 2841 ixgbe_dev_interrupt_handler, 2842 (void *)dev); 2843 2844 /* Clean datapath event and queue/vec mapping */ 2845 rte_intr_efd_disable(intr_handle); 2846 if (intr_handle->intr_vec != NULL) { 2847 rte_free(intr_handle->intr_vec); 2848 intr_handle->intr_vec = NULL; 2849 } 2850 2851 /* reset hierarchy commit */ 2852 tm_conf->committed = false; 2853 } 2854 2855 /* 2856 * Set device link up: enable tx. 2857 */ 2858 static int 2859 ixgbe_dev_set_link_up(struct rte_eth_dev *dev) 2860 { 2861 struct ixgbe_hw *hw = 2862 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2863 if (hw->mac.type == ixgbe_mac_82599EB) { 2864 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2865 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2866 /* Not suported in bypass mode */ 2867 PMD_INIT_LOG(ERR, "Set link up is not supported " 2868 "by device id 0x%x", hw->device_id); 2869 return -ENOTSUP; 2870 } 2871 #endif 2872 } 2873 2874 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2875 /* Turn on the copper */ 2876 ixgbe_set_phy_power(hw, true); 2877 } else { 2878 /* Turn on the laser */ 2879 ixgbe_enable_tx_laser(hw); 2880 } 2881 2882 return 0; 2883 } 2884 2885 /* 2886 * Set device link down: disable tx. 2887 */ 2888 static int 2889 ixgbe_dev_set_link_down(struct rte_eth_dev *dev) 2890 { 2891 struct ixgbe_hw *hw = 2892 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2893 if (hw->mac.type == ixgbe_mac_82599EB) { 2894 #ifdef RTE_LIBRTE_IXGBE_BYPASS 2895 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) { 2896 /* Not suported in bypass mode */ 2897 PMD_INIT_LOG(ERR, "Set link down is not supported " 2898 "by device id 0x%x", hw->device_id); 2899 return -ENOTSUP; 2900 } 2901 #endif 2902 } 2903 2904 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) { 2905 /* Turn off the copper */ 2906 ixgbe_set_phy_power(hw, false); 2907 } else { 2908 /* Turn off the laser */ 2909 ixgbe_disable_tx_laser(hw); 2910 } 2911 2912 return 0; 2913 } 2914 2915 /* 2916 * Reset and stop device. 2917 */ 2918 static void 2919 ixgbe_dev_close(struct rte_eth_dev *dev) 2920 { 2921 struct ixgbe_hw *hw = 2922 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 2923 2924 PMD_INIT_FUNC_TRACE(); 2925 2926 ixgbe_pf_reset_hw(hw); 2927 2928 ixgbe_dev_stop(dev); 2929 hw->adapter_stopped = 1; 2930 2931 ixgbe_dev_free_queues(dev); 2932 2933 ixgbe_disable_pcie_master(hw); 2934 2935 /* reprogram the RAR[0] in case user changed it. */ 2936 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2937 } 2938 2939 /* 2940 * Reset PF device. 2941 */ 2942 static int 2943 ixgbe_dev_reset(struct rte_eth_dev *dev) 2944 { 2945 int ret; 2946 2947 /* When a DPDK PMD PF begin to reset PF port, it should notify all 2948 * its VF to make them align with it. The detailed notification 2949 * mechanism is PMD specific. As to ixgbe PF, it is rather complex. 2950 * To avoid unexpected behavior in VF, currently reset of PF with 2951 * SR-IOV activation is not supported. It might be supported later. 2952 */ 2953 if (dev->data->sriov.active) 2954 return -ENOTSUP; 2955 2956 ret = eth_ixgbe_dev_uninit(dev); 2957 if (ret) 2958 return ret; 2959 2960 ret = eth_ixgbe_dev_init(dev, NULL); 2961 2962 return ret; 2963 } 2964 2965 static void 2966 ixgbe_read_stats_registers(struct ixgbe_hw *hw, 2967 struct ixgbe_hw_stats *hw_stats, 2968 struct ixgbe_macsec_stats *macsec_stats, 2969 uint64_t *total_missed_rx, uint64_t *total_qbrc, 2970 uint64_t *total_qprc, uint64_t *total_qprdc) 2971 { 2972 uint32_t bprc, lxon, lxoff, total; 2973 uint32_t delta_gprc = 0; 2974 unsigned i; 2975 /* Workaround for RX byte count not including CRC bytes when CRC 2976 * strip is enabled. CRC bytes are removed from counters when crc_strip 2977 * is disabled. 2978 */ 2979 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) & 2980 IXGBE_HLREG0_RXCRCSTRP); 2981 2982 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); 2983 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC); 2984 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC); 2985 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC); 2986 2987 for (i = 0; i < 8; i++) { 2988 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i)); 2989 2990 /* global total per queue */ 2991 hw_stats->mpc[i] += mp; 2992 /* Running comprehensive total for stats display */ 2993 *total_missed_rx += hw_stats->mpc[i]; 2994 if (hw->mac.type == ixgbe_mac_82598EB) { 2995 hw_stats->rnbc[i] += 2996 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 2997 hw_stats->pxonrxc[i] += 2998 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 2999 hw_stats->pxoffrxc[i] += 3000 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 3001 } else { 3002 hw_stats->pxonrxc[i] += 3003 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 3004 hw_stats->pxoffrxc[i] += 3005 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 3006 hw_stats->pxon2offc[i] += 3007 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 3008 } 3009 hw_stats->pxontxc[i] += 3010 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 3011 hw_stats->pxofftxc[i] += 3012 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 3013 } 3014 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3015 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 3016 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 3017 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 3018 3019 delta_gprc += delta_qprc; 3020 3021 hw_stats->qprc[i] += delta_qprc; 3022 hw_stats->qptc[i] += delta_qptc; 3023 3024 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 3025 hw_stats->qbrc[i] += 3026 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32); 3027 if (crc_strip == 0) 3028 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN; 3029 3030 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 3031 hw_stats->qbtc[i] += 3032 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32); 3033 3034 hw_stats->qprdc[i] += delta_qprdc; 3035 *total_qprdc += hw_stats->qprdc[i]; 3036 3037 *total_qprc += hw_stats->qprc[i]; 3038 *total_qbrc += hw_stats->qbrc[i]; 3039 } 3040 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC); 3041 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC); 3042 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); 3043 3044 /* 3045 * An errata states that gprc actually counts good + missed packets: 3046 * Workaround to set gprc to summated queue packet receives 3047 */ 3048 hw_stats->gprc = *total_qprc; 3049 3050 if (hw->mac.type != ixgbe_mac_82598EB) { 3051 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); 3052 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32); 3053 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); 3054 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32); 3055 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); 3056 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32); 3057 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 3058 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 3059 } else { 3060 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); 3061 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 3062 /* 82598 only has a counter in the high register */ 3063 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); 3064 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); 3065 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); 3066 } 3067 uint64_t old_tpr = hw_stats->tpr; 3068 3069 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); 3070 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT); 3071 3072 if (crc_strip == 0) 3073 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN; 3074 3075 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC); 3076 hw_stats->gptc += delta_gptc; 3077 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN; 3078 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN; 3079 3080 /* 3081 * Workaround: mprc hardware is incorrectly counting 3082 * broadcasts, so for now we subtract those. 3083 */ 3084 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); 3085 hw_stats->bprc += bprc; 3086 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); 3087 if (hw->mac.type == ixgbe_mac_82598EB) 3088 hw_stats->mprc -= bprc; 3089 3090 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); 3091 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); 3092 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); 3093 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); 3094 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); 3095 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); 3096 3097 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); 3098 hw_stats->lxontxc += lxon; 3099 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 3100 hw_stats->lxofftxc += lxoff; 3101 total = lxon + lxoff; 3102 3103 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); 3104 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); 3105 hw_stats->gptc -= total; 3106 hw_stats->mptc -= total; 3107 hw_stats->ptc64 -= total; 3108 hw_stats->gotc -= total * ETHER_MIN_LEN; 3109 3110 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); 3111 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); 3112 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); 3113 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); 3114 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC); 3115 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC); 3116 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC); 3117 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); 3118 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); 3119 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); 3120 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); 3121 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); 3122 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); 3123 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC); 3124 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); 3125 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST); 3126 /* Only read FCOE on 82599 */ 3127 if (hw->mac.type != ixgbe_mac_82598EB) { 3128 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); 3129 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); 3130 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); 3131 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); 3132 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); 3133 } 3134 3135 /* Flow Director Stats registers */ 3136 if (hw->mac.type != ixgbe_mac_82598EB) { 3137 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); 3138 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); 3139 hw_stats->fdirustat_add += IXGBE_READ_REG(hw, 3140 IXGBE_FDIRUSTAT) & 0xFFFF; 3141 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw, 3142 IXGBE_FDIRUSTAT) >> 16) & 0xFFFF; 3143 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw, 3144 IXGBE_FDIRFSTAT) & 0xFFFF; 3145 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw, 3146 IXGBE_FDIRFSTAT) >> 16) & 0xFFFF; 3147 } 3148 /* MACsec Stats registers */ 3149 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT); 3150 macsec_stats->out_pkts_encrypted += 3151 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE); 3152 macsec_stats->out_pkts_protected += 3153 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP); 3154 macsec_stats->out_octets_encrypted += 3155 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE); 3156 macsec_stats->out_octets_protected += 3157 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP); 3158 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT); 3159 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD); 3160 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI); 3161 macsec_stats->in_pkts_unknownsci += 3162 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI); 3163 macsec_stats->in_octets_decrypted += 3164 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD); 3165 macsec_stats->in_octets_validated += 3166 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV); 3167 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH); 3168 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY); 3169 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE); 3170 for (i = 0; i < 2; i++) { 3171 macsec_stats->in_pkts_ok += 3172 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i)); 3173 macsec_stats->in_pkts_invalid += 3174 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i)); 3175 macsec_stats->in_pkts_notvalid += 3176 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i)); 3177 } 3178 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA); 3179 macsec_stats->in_pkts_notusingsa += 3180 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA); 3181 } 3182 3183 /* 3184 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c 3185 */ 3186 static int 3187 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3188 { 3189 struct ixgbe_hw *hw = 3190 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3191 struct ixgbe_hw_stats *hw_stats = 3192 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3193 struct ixgbe_macsec_stats *macsec_stats = 3194 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3195 dev->data->dev_private); 3196 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3197 unsigned i; 3198 3199 total_missed_rx = 0; 3200 total_qbrc = 0; 3201 total_qprc = 0; 3202 total_qprdc = 0; 3203 3204 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3205 &total_qbrc, &total_qprc, &total_qprdc); 3206 3207 if (stats == NULL) 3208 return -EINVAL; 3209 3210 /* Fill out the rte_eth_stats statistics structure */ 3211 stats->ipackets = total_qprc; 3212 stats->ibytes = total_qbrc; 3213 stats->opackets = hw_stats->gptc; 3214 stats->obytes = hw_stats->gotc; 3215 3216 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) { 3217 stats->q_ipackets[i] = hw_stats->qprc[i]; 3218 stats->q_opackets[i] = hw_stats->qptc[i]; 3219 stats->q_ibytes[i] = hw_stats->qbrc[i]; 3220 stats->q_obytes[i] = hw_stats->qbtc[i]; 3221 stats->q_errors[i] = hw_stats->qprdc[i]; 3222 } 3223 3224 /* Rx Errors */ 3225 stats->imissed = total_missed_rx; 3226 stats->ierrors = hw_stats->crcerrs + 3227 hw_stats->mspdc + 3228 hw_stats->rlec + 3229 hw_stats->ruc + 3230 hw_stats->roc + 3231 hw_stats->illerrc + 3232 hw_stats->errbc + 3233 hw_stats->rfc + 3234 hw_stats->fccrc + 3235 hw_stats->fclast; 3236 3237 /* Tx Errors */ 3238 stats->oerrors = 0; 3239 return 0; 3240 } 3241 3242 static void 3243 ixgbe_dev_stats_reset(struct rte_eth_dev *dev) 3244 { 3245 struct ixgbe_hw_stats *stats = 3246 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3247 3248 /* HW registers are cleared on read */ 3249 ixgbe_dev_stats_get(dev, NULL); 3250 3251 /* Reset software totals */ 3252 memset(stats, 0, sizeof(*stats)); 3253 } 3254 3255 /* This function calculates the number of xstats based on the current config */ 3256 static unsigned 3257 ixgbe_xstats_calc_num(void) { 3258 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS + 3259 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) + 3260 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES); 3261 } 3262 3263 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3264 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size) 3265 { 3266 const unsigned cnt_stats = ixgbe_xstats_calc_num(); 3267 unsigned stat, i, count; 3268 3269 if (xstats_names != NULL) { 3270 count = 0; 3271 3272 /* Note: limit >= cnt_stats checked upstream 3273 * in rte_eth_xstats_names() 3274 */ 3275 3276 /* Extended stats from ixgbe_hw_stats */ 3277 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3278 snprintf(xstats_names[count].name, 3279 sizeof(xstats_names[count].name), 3280 "%s", 3281 rte_ixgbe_stats_strings[i].name); 3282 count++; 3283 } 3284 3285 /* MACsec Stats */ 3286 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3287 snprintf(xstats_names[count].name, 3288 sizeof(xstats_names[count].name), 3289 "%s", 3290 rte_ixgbe_macsec_strings[i].name); 3291 count++; 3292 } 3293 3294 /* RX Priority Stats */ 3295 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3296 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3297 snprintf(xstats_names[count].name, 3298 sizeof(xstats_names[count].name), 3299 "rx_priority%u_%s", i, 3300 rte_ixgbe_rxq_strings[stat].name); 3301 count++; 3302 } 3303 } 3304 3305 /* TX Priority Stats */ 3306 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3307 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3308 snprintf(xstats_names[count].name, 3309 sizeof(xstats_names[count].name), 3310 "tx_priority%u_%s", i, 3311 rte_ixgbe_txq_strings[stat].name); 3312 count++; 3313 } 3314 } 3315 } 3316 return cnt_stats; 3317 } 3318 3319 static int ixgbe_dev_xstats_get_names_by_id( 3320 struct rte_eth_dev *dev, 3321 struct rte_eth_xstat_name *xstats_names, 3322 const uint64_t *ids, 3323 unsigned int limit) 3324 { 3325 if (!ids) { 3326 const unsigned int cnt_stats = ixgbe_xstats_calc_num(); 3327 unsigned int stat, i, count; 3328 3329 if (xstats_names != NULL) { 3330 count = 0; 3331 3332 /* Note: limit >= cnt_stats checked upstream 3333 * in rte_eth_xstats_names() 3334 */ 3335 3336 /* Extended stats from ixgbe_hw_stats */ 3337 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3338 snprintf(xstats_names[count].name, 3339 sizeof(xstats_names[count].name), 3340 "%s", 3341 rte_ixgbe_stats_strings[i].name); 3342 count++; 3343 } 3344 3345 /* MACsec Stats */ 3346 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3347 snprintf(xstats_names[count].name, 3348 sizeof(xstats_names[count].name), 3349 "%s", 3350 rte_ixgbe_macsec_strings[i].name); 3351 count++; 3352 } 3353 3354 /* RX Priority Stats */ 3355 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3356 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3357 snprintf(xstats_names[count].name, 3358 sizeof(xstats_names[count].name), 3359 "rx_priority%u_%s", i, 3360 rte_ixgbe_rxq_strings[stat].name); 3361 count++; 3362 } 3363 } 3364 3365 /* TX Priority Stats */ 3366 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3367 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3368 snprintf(xstats_names[count].name, 3369 sizeof(xstats_names[count].name), 3370 "tx_priority%u_%s", i, 3371 rte_ixgbe_txq_strings[stat].name); 3372 count++; 3373 } 3374 } 3375 } 3376 return cnt_stats; 3377 } 3378 3379 uint16_t i; 3380 uint16_t size = ixgbe_xstats_calc_num(); 3381 struct rte_eth_xstat_name xstats_names_copy[size]; 3382 3383 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL, 3384 size); 3385 3386 for (i = 0; i < limit; i++) { 3387 if (ids[i] >= size) { 3388 PMD_INIT_LOG(ERR, "id value isn't valid"); 3389 return -1; 3390 } 3391 strcpy(xstats_names[i].name, 3392 xstats_names_copy[ids[i]].name); 3393 } 3394 return limit; 3395 } 3396 3397 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 3398 struct rte_eth_xstat_name *xstats_names, unsigned limit) 3399 { 3400 unsigned i; 3401 3402 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL) 3403 return -ENOMEM; 3404 3405 if (xstats_names != NULL) 3406 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) 3407 snprintf(xstats_names[i].name, 3408 sizeof(xstats_names[i].name), 3409 "%s", rte_ixgbevf_stats_strings[i].name); 3410 return IXGBEVF_NB_XSTATS; 3411 } 3412 3413 static int 3414 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3415 unsigned n) 3416 { 3417 struct ixgbe_hw *hw = 3418 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3419 struct ixgbe_hw_stats *hw_stats = 3420 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3421 struct ixgbe_macsec_stats *macsec_stats = 3422 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3423 dev->data->dev_private); 3424 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3425 unsigned i, stat, count = 0; 3426 3427 count = ixgbe_xstats_calc_num(); 3428 3429 if (n < count) 3430 return count; 3431 3432 total_missed_rx = 0; 3433 total_qbrc = 0; 3434 total_qprc = 0; 3435 total_qprdc = 0; 3436 3437 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx, 3438 &total_qbrc, &total_qprc, &total_qprdc); 3439 3440 /* If this is a reset xstats is NULL, and we have cleared the 3441 * registers by reading them. 3442 */ 3443 if (!xstats) 3444 return 0; 3445 3446 /* Extended stats from ixgbe_hw_stats */ 3447 count = 0; 3448 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3449 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3450 rte_ixgbe_stats_strings[i].offset); 3451 xstats[count].id = count; 3452 count++; 3453 } 3454 3455 /* MACsec Stats */ 3456 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3457 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) + 3458 rte_ixgbe_macsec_strings[i].offset); 3459 xstats[count].id = count; 3460 count++; 3461 } 3462 3463 /* RX Priority Stats */ 3464 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3465 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3466 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3467 rte_ixgbe_rxq_strings[stat].offset + 3468 (sizeof(uint64_t) * i)); 3469 xstats[count].id = count; 3470 count++; 3471 } 3472 } 3473 3474 /* TX Priority Stats */ 3475 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3476 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3477 xstats[count].value = *(uint64_t *)(((char *)hw_stats) + 3478 rte_ixgbe_txq_strings[stat].offset + 3479 (sizeof(uint64_t) * i)); 3480 xstats[count].id = count; 3481 count++; 3482 } 3483 } 3484 return count; 3485 } 3486 3487 static int 3488 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 3489 uint64_t *values, unsigned int n) 3490 { 3491 if (!ids) { 3492 struct ixgbe_hw *hw = 3493 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3494 struct ixgbe_hw_stats *hw_stats = 3495 IXGBE_DEV_PRIVATE_TO_STATS( 3496 dev->data->dev_private); 3497 struct ixgbe_macsec_stats *macsec_stats = 3498 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3499 dev->data->dev_private); 3500 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc; 3501 unsigned int i, stat, count = 0; 3502 3503 count = ixgbe_xstats_calc_num(); 3504 3505 if (!ids && n < count) 3506 return count; 3507 3508 total_missed_rx = 0; 3509 total_qbrc = 0; 3510 total_qprc = 0; 3511 total_qprdc = 0; 3512 3513 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, 3514 &total_missed_rx, &total_qbrc, &total_qprc, 3515 &total_qprdc); 3516 3517 /* If this is a reset xstats is NULL, and we have cleared the 3518 * registers by reading them. 3519 */ 3520 if (!ids && !values) 3521 return 0; 3522 3523 /* Extended stats from ixgbe_hw_stats */ 3524 count = 0; 3525 for (i = 0; i < IXGBE_NB_HW_STATS; i++) { 3526 values[count] = *(uint64_t *)(((char *)hw_stats) + 3527 rte_ixgbe_stats_strings[i].offset); 3528 count++; 3529 } 3530 3531 /* MACsec Stats */ 3532 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) { 3533 values[count] = *(uint64_t *)(((char *)macsec_stats) + 3534 rte_ixgbe_macsec_strings[i].offset); 3535 count++; 3536 } 3537 3538 /* RX Priority Stats */ 3539 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) { 3540 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) { 3541 values[count] = 3542 *(uint64_t *)(((char *)hw_stats) + 3543 rte_ixgbe_rxq_strings[stat].offset + 3544 (sizeof(uint64_t) * i)); 3545 count++; 3546 } 3547 } 3548 3549 /* TX Priority Stats */ 3550 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) { 3551 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) { 3552 values[count] = 3553 *(uint64_t *)(((char *)hw_stats) + 3554 rte_ixgbe_txq_strings[stat].offset + 3555 (sizeof(uint64_t) * i)); 3556 count++; 3557 } 3558 } 3559 return count; 3560 } 3561 3562 uint16_t i; 3563 uint16_t size = ixgbe_xstats_calc_num(); 3564 uint64_t values_copy[size]; 3565 3566 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size); 3567 3568 for (i = 0; i < n; i++) { 3569 if (ids[i] >= size) { 3570 PMD_INIT_LOG(ERR, "id value isn't valid"); 3571 return -1; 3572 } 3573 values[i] = values_copy[ids[i]]; 3574 } 3575 return n; 3576 } 3577 3578 static void 3579 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev) 3580 { 3581 struct ixgbe_hw_stats *stats = 3582 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3583 struct ixgbe_macsec_stats *macsec_stats = 3584 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS( 3585 dev->data->dev_private); 3586 3587 unsigned count = ixgbe_xstats_calc_num(); 3588 3589 /* HW registers are cleared on read */ 3590 ixgbe_dev_xstats_get(dev, NULL, count); 3591 3592 /* Reset software totals */ 3593 memset(stats, 0, sizeof(*stats)); 3594 memset(macsec_stats, 0, sizeof(*macsec_stats)); 3595 } 3596 3597 static void 3598 ixgbevf_update_stats(struct rte_eth_dev *dev) 3599 { 3600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3601 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3602 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3603 3604 /* Good Rx packet, include VF loopback */ 3605 UPDATE_VF_STAT(IXGBE_VFGPRC, 3606 hw_stats->last_vfgprc, hw_stats->vfgprc); 3607 3608 /* Good Rx octets, include VF loopback */ 3609 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB, 3610 hw_stats->last_vfgorc, hw_stats->vfgorc); 3611 3612 /* Good Tx packet, include VF loopback */ 3613 UPDATE_VF_STAT(IXGBE_VFGPTC, 3614 hw_stats->last_vfgptc, hw_stats->vfgptc); 3615 3616 /* Good Tx octets, include VF loopback */ 3617 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB, 3618 hw_stats->last_vfgotc, hw_stats->vfgotc); 3619 3620 /* Rx Multicst Packet */ 3621 UPDATE_VF_STAT(IXGBE_VFMPRC, 3622 hw_stats->last_vfmprc, hw_stats->vfmprc); 3623 } 3624 3625 static int 3626 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 3627 unsigned n) 3628 { 3629 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3630 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3631 unsigned i; 3632 3633 if (n < IXGBEVF_NB_XSTATS) 3634 return IXGBEVF_NB_XSTATS; 3635 3636 ixgbevf_update_stats(dev); 3637 3638 if (!xstats) 3639 return 0; 3640 3641 /* Extended stats */ 3642 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) { 3643 xstats[i].id = i; 3644 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + 3645 rte_ixgbevf_stats_strings[i].offset); 3646 } 3647 3648 return IXGBEVF_NB_XSTATS; 3649 } 3650 3651 static int 3652 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) 3653 { 3654 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3655 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3656 3657 ixgbevf_update_stats(dev); 3658 3659 if (stats == NULL) 3660 return -EINVAL; 3661 3662 stats->ipackets = hw_stats->vfgprc; 3663 stats->ibytes = hw_stats->vfgorc; 3664 stats->opackets = hw_stats->vfgptc; 3665 stats->obytes = hw_stats->vfgotc; 3666 return 0; 3667 } 3668 3669 static void 3670 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev) 3671 { 3672 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *) 3673 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private); 3674 3675 /* Sync HW register to the last stats */ 3676 ixgbevf_dev_stats_get(dev, NULL); 3677 3678 /* reset HW current stats*/ 3679 hw_stats->vfgprc = 0; 3680 hw_stats->vfgorc = 0; 3681 hw_stats->vfgptc = 0; 3682 hw_stats->vfgotc = 0; 3683 } 3684 3685 static int 3686 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 3687 { 3688 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3689 u16 eeprom_verh, eeprom_verl; 3690 u32 etrack_id; 3691 int ret; 3692 3693 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh); 3694 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl); 3695 3696 etrack_id = (eeprom_verh << 16) | eeprom_verl; 3697 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id); 3698 3699 ret += 1; /* add the size of '\0' */ 3700 if (fw_size < (u32)ret) 3701 return ret; 3702 else 3703 return 0; 3704 } 3705 3706 static void 3707 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 3708 { 3709 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3710 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3711 struct rte_eth_conf *dev_conf = &dev->data->dev_conf; 3712 3713 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3714 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3715 if (RTE_ETH_DEV_SRIOV(dev).active == 0) { 3716 /* 3717 * When DCB/VT is off, maximum number of queues changes, 3718 * except for 82598EB, which remains constant. 3719 */ 3720 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE && 3721 hw->mac.type != ixgbe_mac_82598EB) 3722 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES; 3723 } 3724 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */ 3725 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */ 3726 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3727 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3728 dev_info->max_vfs = pci_dev->max_vfs; 3729 if (hw->mac.type == ixgbe_mac_82598EB) 3730 dev_info->max_vmdq_pools = ETH_16_POOLS; 3731 else 3732 dev_info->max_vmdq_pools = ETH_64_POOLS; 3733 dev_info->vmdq_queue_num = dev_info->max_rx_queues; 3734 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3735 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3736 dev_info->rx_queue_offload_capa); 3737 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3738 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3739 3740 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3741 .rx_thresh = { 3742 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3743 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3744 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3745 }, 3746 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3747 .rx_drop_en = 0, 3748 .offloads = 0, 3749 }; 3750 3751 dev_info->default_txconf = (struct rte_eth_txconf) { 3752 .tx_thresh = { 3753 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3754 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3755 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3756 }, 3757 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3758 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3759 .offloads = 0, 3760 }; 3761 3762 dev_info->rx_desc_lim = rx_desc_lim; 3763 dev_info->tx_desc_lim = tx_desc_lim; 3764 3765 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t); 3766 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type); 3767 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL; 3768 3769 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G; 3770 if (hw->mac.type == ixgbe_mac_X540 || 3771 hw->mac.type == ixgbe_mac_X540_vf || 3772 hw->mac.type == ixgbe_mac_X550 || 3773 hw->mac.type == ixgbe_mac_X550_vf) { 3774 dev_info->speed_capa |= ETH_LINK_SPEED_100M; 3775 } 3776 if (hw->mac.type == ixgbe_mac_X550) { 3777 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G; 3778 dev_info->speed_capa |= ETH_LINK_SPEED_5G; 3779 } 3780 3781 /* Driver-preferred Rx/Tx parameters */ 3782 dev_info->default_rxportconf.burst_size = 32; 3783 dev_info->default_txportconf.burst_size = 32; 3784 dev_info->default_rxportconf.nb_queues = 1; 3785 dev_info->default_txportconf.nb_queues = 1; 3786 dev_info->default_rxportconf.ring_size = 256; 3787 dev_info->default_txportconf.ring_size = 256; 3788 } 3789 3790 static const uint32_t * 3791 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 3792 { 3793 static const uint32_t ptypes[] = { 3794 /* For non-vec functions, 3795 * refers to ixgbe_rxd_pkt_info_to_pkt_type(); 3796 * for vec functions, 3797 * refers to _recv_raw_pkts_vec(). 3798 */ 3799 RTE_PTYPE_L2_ETHER, 3800 RTE_PTYPE_L3_IPV4, 3801 RTE_PTYPE_L3_IPV4_EXT, 3802 RTE_PTYPE_L3_IPV6, 3803 RTE_PTYPE_L3_IPV6_EXT, 3804 RTE_PTYPE_L4_SCTP, 3805 RTE_PTYPE_L4_TCP, 3806 RTE_PTYPE_L4_UDP, 3807 RTE_PTYPE_TUNNEL_IP, 3808 RTE_PTYPE_INNER_L3_IPV6, 3809 RTE_PTYPE_INNER_L3_IPV6_EXT, 3810 RTE_PTYPE_INNER_L4_TCP, 3811 RTE_PTYPE_INNER_L4_UDP, 3812 RTE_PTYPE_UNKNOWN 3813 }; 3814 3815 if (dev->rx_pkt_burst == ixgbe_recv_pkts || 3816 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc || 3817 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc || 3818 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc) 3819 return ptypes; 3820 3821 #if defined(RTE_ARCH_X86) 3822 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec || 3823 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec) 3824 return ptypes; 3825 #endif 3826 return NULL; 3827 } 3828 3829 static void 3830 ixgbevf_dev_info_get(struct rte_eth_dev *dev, 3831 struct rte_eth_dev_info *dev_info) 3832 { 3833 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 3834 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3835 3836 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues; 3837 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues; 3838 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */ 3839 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */ 3840 dev_info->max_mac_addrs = hw->mac.num_rar_entries; 3841 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC; 3842 dev_info->max_vfs = pci_dev->max_vfs; 3843 if (hw->mac.type == ixgbe_mac_82598EB) 3844 dev_info->max_vmdq_pools = ETH_16_POOLS; 3845 else 3846 dev_info->max_vmdq_pools = ETH_64_POOLS; 3847 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev); 3848 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) | 3849 dev_info->rx_queue_offload_capa); 3850 dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev); 3851 dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev); 3852 3853 dev_info->default_rxconf = (struct rte_eth_rxconf) { 3854 .rx_thresh = { 3855 .pthresh = IXGBE_DEFAULT_RX_PTHRESH, 3856 .hthresh = IXGBE_DEFAULT_RX_HTHRESH, 3857 .wthresh = IXGBE_DEFAULT_RX_WTHRESH, 3858 }, 3859 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH, 3860 .rx_drop_en = 0, 3861 .offloads = 0, 3862 }; 3863 3864 dev_info->default_txconf = (struct rte_eth_txconf) { 3865 .tx_thresh = { 3866 .pthresh = IXGBE_DEFAULT_TX_PTHRESH, 3867 .hthresh = IXGBE_DEFAULT_TX_HTHRESH, 3868 .wthresh = IXGBE_DEFAULT_TX_WTHRESH, 3869 }, 3870 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH, 3871 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH, 3872 .offloads = 0, 3873 }; 3874 3875 dev_info->rx_desc_lim = rx_desc_lim; 3876 dev_info->tx_desc_lim = tx_desc_lim; 3877 } 3878 3879 static int 3880 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3881 int *link_up, int wait_to_complete) 3882 { 3883 struct ixgbe_mbx_info *mbx = &hw->mbx; 3884 struct ixgbe_mac_info *mac = &hw->mac; 3885 uint32_t links_reg, in_msg; 3886 int ret_val = 0; 3887 3888 /* If we were hit with a reset drop the link */ 3889 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 3890 mac->get_link_status = true; 3891 3892 if (!mac->get_link_status) 3893 goto out; 3894 3895 /* if link status is down no point in checking to see if pf is up */ 3896 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3897 if (!(links_reg & IXGBE_LINKS_UP)) 3898 goto out; 3899 3900 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 3901 * before the link status is correct 3902 */ 3903 if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) { 3904 int i; 3905 3906 for (i = 0; i < 5; i++) { 3907 rte_delay_us(100); 3908 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 3909 3910 if (!(links_reg & IXGBE_LINKS_UP)) 3911 goto out; 3912 } 3913 } 3914 3915 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 3916 case IXGBE_LINKS_SPEED_10G_82599: 3917 *speed = IXGBE_LINK_SPEED_10GB_FULL; 3918 if (hw->mac.type >= ixgbe_mac_X550) { 3919 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 3920 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 3921 } 3922 break; 3923 case IXGBE_LINKS_SPEED_1G_82599: 3924 *speed = IXGBE_LINK_SPEED_1GB_FULL; 3925 break; 3926 case IXGBE_LINKS_SPEED_100_82599: 3927 *speed = IXGBE_LINK_SPEED_100_FULL; 3928 if (hw->mac.type == ixgbe_mac_X550) { 3929 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 3930 *speed = IXGBE_LINK_SPEED_5GB_FULL; 3931 } 3932 break; 3933 case IXGBE_LINKS_SPEED_10_X550EM_A: 3934 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3935 /* Since Reserved in older MAC's */ 3936 if (hw->mac.type >= ixgbe_mac_X550) 3937 *speed = IXGBE_LINK_SPEED_10_FULL; 3938 break; 3939 default: 3940 *speed = IXGBE_LINK_SPEED_UNKNOWN; 3941 } 3942 3943 /* if the read failed it could just be a mailbox collision, best wait 3944 * until we are called again and don't report an error 3945 */ 3946 if (mbx->ops.read(hw, &in_msg, 1, 0)) 3947 goto out; 3948 3949 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 3950 /* msg is not CTS and is NACK we must have lost CTS status */ 3951 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 3952 mac->get_link_status = false; 3953 goto out; 3954 } 3955 3956 /* the pf is talking, if we timed out in the past we reinit */ 3957 if (!mbx->timeout) { 3958 ret_val = -1; 3959 goto out; 3960 } 3961 3962 /* if we passed all the tests above then the link is up and we no 3963 * longer need to check for link 3964 */ 3965 mac->get_link_status = false; 3966 3967 out: 3968 *link_up = !mac->get_link_status; 3969 return ret_val; 3970 } 3971 3972 static void 3973 ixgbe_dev_setup_link_alarm_handler(void *param) 3974 { 3975 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 3976 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3977 struct ixgbe_interrupt *intr = 3978 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 3979 u32 speed; 3980 bool autoneg = false; 3981 3982 speed = hw->phy.autoneg_advertised; 3983 if (!speed) 3984 ixgbe_get_link_capabilities(hw, &speed, &autoneg); 3985 3986 ixgbe_setup_link(hw, speed, true); 3987 3988 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; 3989 } 3990 3991 /* return 0 means link status changed, -1 means not changed */ 3992 int 3993 ixgbe_dev_link_update_share(struct rte_eth_dev *dev, 3994 int wait_to_complete, int vf) 3995 { 3996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 3997 struct rte_eth_link link; 3998 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 3999 struct ixgbe_interrupt *intr = 4000 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4001 int link_up; 4002 int diag; 4003 int wait = 1; 4004 4005 memset(&link, 0, sizeof(link)); 4006 link.link_status = ETH_LINK_DOWN; 4007 link.link_speed = ETH_SPEED_NUM_NONE; 4008 link.link_duplex = ETH_LINK_HALF_DUPLEX; 4009 link.link_autoneg = ETH_LINK_AUTONEG; 4010 4011 hw->mac.get_link_status = true; 4012 4013 if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) 4014 return rte_eth_linkstatus_set(dev, &link); 4015 4016 /* check if it needs to wait to complete, if lsc interrupt is enabled */ 4017 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0) 4018 wait = 0; 4019 4020 if (vf) 4021 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait); 4022 else 4023 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait); 4024 4025 if (diag != 0) { 4026 link.link_speed = ETH_SPEED_NUM_100M; 4027 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4028 return rte_eth_linkstatus_set(dev, &link); 4029 } 4030 4031 if (link_up == 0) { 4032 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) { 4033 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; 4034 rte_eal_alarm_set(10, 4035 ixgbe_dev_setup_link_alarm_handler, dev); 4036 } 4037 return rte_eth_linkstatus_set(dev, &link); 4038 } 4039 4040 link.link_status = ETH_LINK_UP; 4041 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4042 4043 switch (link_speed) { 4044 default: 4045 case IXGBE_LINK_SPEED_UNKNOWN: 4046 link.link_duplex = ETH_LINK_FULL_DUPLEX; 4047 link.link_speed = ETH_SPEED_NUM_100M; 4048 break; 4049 4050 case IXGBE_LINK_SPEED_100_FULL: 4051 link.link_speed = ETH_SPEED_NUM_100M; 4052 break; 4053 4054 case IXGBE_LINK_SPEED_1GB_FULL: 4055 link.link_speed = ETH_SPEED_NUM_1G; 4056 break; 4057 4058 case IXGBE_LINK_SPEED_2_5GB_FULL: 4059 link.link_speed = ETH_SPEED_NUM_2_5G; 4060 break; 4061 4062 case IXGBE_LINK_SPEED_5GB_FULL: 4063 link.link_speed = ETH_SPEED_NUM_5G; 4064 break; 4065 4066 case IXGBE_LINK_SPEED_10GB_FULL: 4067 link.link_speed = ETH_SPEED_NUM_10G; 4068 break; 4069 } 4070 4071 return rte_eth_linkstatus_set(dev, &link); 4072 } 4073 4074 static int 4075 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4076 { 4077 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0); 4078 } 4079 4080 static int 4081 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete) 4082 { 4083 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1); 4084 } 4085 4086 static void 4087 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 4088 { 4089 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4090 uint32_t fctrl; 4091 4092 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4093 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); 4094 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4095 } 4096 4097 static void 4098 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 4099 { 4100 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4101 uint32_t fctrl; 4102 4103 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4104 fctrl &= (~IXGBE_FCTRL_UPE); 4105 if (dev->data->all_multicast == 1) 4106 fctrl |= IXGBE_FCTRL_MPE; 4107 else 4108 fctrl &= (~IXGBE_FCTRL_MPE); 4109 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4110 } 4111 4112 static void 4113 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 4114 { 4115 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4116 uint32_t fctrl; 4117 4118 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4119 fctrl |= IXGBE_FCTRL_MPE; 4120 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4121 } 4122 4123 static void 4124 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 4125 { 4126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4127 uint32_t fctrl; 4128 4129 if (dev->data->promiscuous == 1) 4130 return; /* must remain in all_multicast mode */ 4131 4132 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 4133 fctrl &= (~IXGBE_FCTRL_MPE); 4134 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 4135 } 4136 4137 /** 4138 * It clears the interrupt causes and enables the interrupt. 4139 * It will be called once only during nic initialized. 4140 * 4141 * @param dev 4142 * Pointer to struct rte_eth_dev. 4143 * @param on 4144 * Enable or Disable. 4145 * 4146 * @return 4147 * - On success, zero. 4148 * - On failure, a negative value. 4149 */ 4150 static int 4151 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on) 4152 { 4153 struct ixgbe_interrupt *intr = 4154 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4155 4156 ixgbe_dev_link_status_print(dev); 4157 if (on) 4158 intr->mask |= IXGBE_EICR_LSC; 4159 else 4160 intr->mask &= ~IXGBE_EICR_LSC; 4161 4162 return 0; 4163 } 4164 4165 /** 4166 * It clears the interrupt causes and enables the interrupt. 4167 * It will be called once only during nic initialized. 4168 * 4169 * @param dev 4170 * Pointer to struct rte_eth_dev. 4171 * 4172 * @return 4173 * - On success, zero. 4174 * - On failure, a negative value. 4175 */ 4176 static int 4177 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev) 4178 { 4179 struct ixgbe_interrupt *intr = 4180 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4181 4182 intr->mask |= IXGBE_EICR_RTX_QUEUE; 4183 4184 return 0; 4185 } 4186 4187 /** 4188 * It clears the interrupt causes and enables the interrupt. 4189 * It will be called once only during nic initialized. 4190 * 4191 * @param dev 4192 * Pointer to struct rte_eth_dev. 4193 * 4194 * @return 4195 * - On success, zero. 4196 * - On failure, a negative value. 4197 */ 4198 static int 4199 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev) 4200 { 4201 struct ixgbe_interrupt *intr = 4202 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4203 4204 intr->mask |= IXGBE_EICR_LINKSEC; 4205 4206 return 0; 4207 } 4208 4209 /* 4210 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update. 4211 * 4212 * @param dev 4213 * Pointer to struct rte_eth_dev. 4214 * 4215 * @return 4216 * - On success, zero. 4217 * - On failure, a negative value. 4218 */ 4219 static int 4220 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev) 4221 { 4222 uint32_t eicr; 4223 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4224 struct ixgbe_interrupt *intr = 4225 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4226 4227 /* clear all cause mask */ 4228 ixgbe_disable_intr(hw); 4229 4230 /* read-on-clear nic registers here */ 4231 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4232 PMD_DRV_LOG(DEBUG, "eicr %x", eicr); 4233 4234 intr->flags = 0; 4235 4236 /* set flag for async link update */ 4237 if (eicr & IXGBE_EICR_LSC) 4238 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; 4239 4240 if (eicr & IXGBE_EICR_MAILBOX) 4241 intr->flags |= IXGBE_FLAG_MAILBOX; 4242 4243 if (eicr & IXGBE_EICR_LINKSEC) 4244 intr->flags |= IXGBE_FLAG_MACSEC; 4245 4246 if (hw->mac.type == ixgbe_mac_X550EM_x && 4247 hw->phy.type == ixgbe_phy_x550em_ext_t && 4248 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x)) 4249 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT; 4250 4251 return 0; 4252 } 4253 4254 /** 4255 * It gets and then prints the link status. 4256 * 4257 * @param dev 4258 * Pointer to struct rte_eth_dev. 4259 * 4260 * @return 4261 * - On success, zero. 4262 * - On failure, a negative value. 4263 */ 4264 static void 4265 ixgbe_dev_link_status_print(struct rte_eth_dev *dev) 4266 { 4267 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4268 struct rte_eth_link link; 4269 4270 rte_eth_linkstatus_get(dev, &link); 4271 4272 if (link.link_status) { 4273 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s", 4274 (int)(dev->data->port_id), 4275 (unsigned)link.link_speed, 4276 link.link_duplex == ETH_LINK_FULL_DUPLEX ? 4277 "full-duplex" : "half-duplex"); 4278 } else { 4279 PMD_INIT_LOG(INFO, " Port %d: Link Down", 4280 (int)(dev->data->port_id)); 4281 } 4282 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT, 4283 pci_dev->addr.domain, 4284 pci_dev->addr.bus, 4285 pci_dev->addr.devid, 4286 pci_dev->addr.function); 4287 } 4288 4289 /* 4290 * It executes link_update after knowing an interrupt occurred. 4291 * 4292 * @param dev 4293 * Pointer to struct rte_eth_dev. 4294 * 4295 * @return 4296 * - On success, zero. 4297 * - On failure, a negative value. 4298 */ 4299 static int 4300 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev) 4301 { 4302 struct ixgbe_interrupt *intr = 4303 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4304 int64_t timeout; 4305 struct ixgbe_hw *hw = 4306 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4307 4308 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags); 4309 4310 if (intr->flags & IXGBE_FLAG_MAILBOX) { 4311 ixgbe_pf_mbx_process(dev); 4312 intr->flags &= ~IXGBE_FLAG_MAILBOX; 4313 } 4314 4315 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4316 ixgbe_handle_lasi(hw); 4317 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4318 } 4319 4320 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4321 struct rte_eth_link link; 4322 4323 /* get the link status before link update, for predicting later */ 4324 rte_eth_linkstatus_get(dev, &link); 4325 4326 ixgbe_dev_link_update(dev, 0); 4327 4328 /* likely to up */ 4329 if (!link.link_status) 4330 /* handle it 1 sec later, wait it being stable */ 4331 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT; 4332 /* likely to down */ 4333 else 4334 /* handle it 4 sec later, wait it being stable */ 4335 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT; 4336 4337 ixgbe_dev_link_status_print(dev); 4338 if (rte_eal_alarm_set(timeout * 1000, 4339 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0) 4340 PMD_DRV_LOG(ERR, "Error setting alarm"); 4341 else { 4342 /* remember original mask */ 4343 intr->mask_original = intr->mask; 4344 /* only disable lsc interrupt */ 4345 intr->mask &= ~IXGBE_EIMS_LSC; 4346 } 4347 } 4348 4349 PMD_DRV_LOG(DEBUG, "enable intr immediately"); 4350 ixgbe_enable_intr(dev); 4351 4352 return 0; 4353 } 4354 4355 /** 4356 * Interrupt handler which shall be registered for alarm callback for delayed 4357 * handling specific interrupt to wait for the stable nic state. As the 4358 * NIC interrupt state is not stable for ixgbe after link is just down, 4359 * it needs to wait 4 seconds to get the stable status. 4360 * 4361 * @param handle 4362 * Pointer to interrupt handle. 4363 * @param param 4364 * The address of parameter (struct rte_eth_dev *) regsitered before. 4365 * 4366 * @return 4367 * void 4368 */ 4369 static void 4370 ixgbe_dev_interrupt_delayed_handler(void *param) 4371 { 4372 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4373 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4374 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 4375 struct ixgbe_interrupt *intr = 4376 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4377 struct ixgbe_hw *hw = 4378 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4379 uint32_t eicr; 4380 4381 ixgbe_disable_intr(hw); 4382 4383 eicr = IXGBE_READ_REG(hw, IXGBE_EICR); 4384 if (eicr & IXGBE_EICR_MAILBOX) 4385 ixgbe_pf_mbx_process(dev); 4386 4387 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) { 4388 ixgbe_handle_lasi(hw); 4389 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT; 4390 } 4391 4392 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { 4393 ixgbe_dev_link_update(dev, 0); 4394 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; 4395 ixgbe_dev_link_status_print(dev); 4396 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 4397 NULL); 4398 } 4399 4400 if (intr->flags & IXGBE_FLAG_MACSEC) { 4401 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, 4402 NULL); 4403 intr->flags &= ~IXGBE_FLAG_MACSEC; 4404 } 4405 4406 /* restore original mask */ 4407 intr->mask = intr->mask_original; 4408 intr->mask_original = 0; 4409 4410 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr); 4411 ixgbe_enable_intr(dev); 4412 rte_intr_enable(intr_handle); 4413 } 4414 4415 /** 4416 * Interrupt handler triggered by NIC for handling 4417 * specific interrupt. 4418 * 4419 * @param handle 4420 * Pointer to interrupt handle. 4421 * @param param 4422 * The address of parameter (struct rte_eth_dev *) regsitered before. 4423 * 4424 * @return 4425 * void 4426 */ 4427 static void 4428 ixgbe_dev_interrupt_handler(void *param) 4429 { 4430 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 4431 4432 ixgbe_dev_interrupt_get_status(dev); 4433 ixgbe_dev_interrupt_action(dev); 4434 } 4435 4436 static int 4437 ixgbe_dev_led_on(struct rte_eth_dev *dev) 4438 { 4439 struct ixgbe_hw *hw; 4440 4441 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4442 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4443 } 4444 4445 static int 4446 ixgbe_dev_led_off(struct rte_eth_dev *dev) 4447 { 4448 struct ixgbe_hw *hw; 4449 4450 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4451 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP; 4452 } 4453 4454 static int 4455 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4456 { 4457 struct ixgbe_hw *hw; 4458 uint32_t mflcn_reg; 4459 uint32_t fccfg_reg; 4460 int rx_pause; 4461 int tx_pause; 4462 4463 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4464 4465 fc_conf->pause_time = hw->fc.pause_time; 4466 fc_conf->high_water = hw->fc.high_water[0]; 4467 fc_conf->low_water = hw->fc.low_water[0]; 4468 fc_conf->send_xon = hw->fc.send_xon; 4469 fc_conf->autoneg = !hw->fc.disable_fc_autoneg; 4470 4471 /* 4472 * Return rx_pause status according to actual setting of 4473 * MFLCN register. 4474 */ 4475 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4476 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE)) 4477 rx_pause = 1; 4478 else 4479 rx_pause = 0; 4480 4481 /* 4482 * Return tx_pause status according to actual setting of 4483 * FCCFG register. 4484 */ 4485 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4486 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY)) 4487 tx_pause = 1; 4488 else 4489 tx_pause = 0; 4490 4491 if (rx_pause && tx_pause) 4492 fc_conf->mode = RTE_FC_FULL; 4493 else if (rx_pause) 4494 fc_conf->mode = RTE_FC_RX_PAUSE; 4495 else if (tx_pause) 4496 fc_conf->mode = RTE_FC_TX_PAUSE; 4497 else 4498 fc_conf->mode = RTE_FC_NONE; 4499 4500 return 0; 4501 } 4502 4503 static int 4504 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 4505 { 4506 struct ixgbe_hw *hw; 4507 int err; 4508 uint32_t rx_buf_size; 4509 uint32_t max_high_water; 4510 uint32_t mflcn; 4511 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4512 ixgbe_fc_none, 4513 ixgbe_fc_rx_pause, 4514 ixgbe_fc_tx_pause, 4515 ixgbe_fc_full 4516 }; 4517 4518 PMD_INIT_FUNC_TRACE(); 4519 4520 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4521 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)); 4522 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4523 4524 /* 4525 * At least reserve one Ethernet frame for watermark 4526 * high_water/low_water in kilo bytes for ixgbe 4527 */ 4528 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4529 if ((fc_conf->high_water > max_high_water) || 4530 (fc_conf->high_water < fc_conf->low_water)) { 4531 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4532 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4533 return -EINVAL; 4534 } 4535 4536 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode]; 4537 hw->fc.pause_time = fc_conf->pause_time; 4538 hw->fc.high_water[0] = fc_conf->high_water; 4539 hw->fc.low_water[0] = fc_conf->low_water; 4540 hw->fc.send_xon = fc_conf->send_xon; 4541 hw->fc.disable_fc_autoneg = !fc_conf->autoneg; 4542 4543 err = ixgbe_fc_enable(hw); 4544 4545 /* Not negotiated is not an error case */ 4546 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) { 4547 4548 /* check if we want to forward MAC frames - driver doesn't have native 4549 * capability to do that, so we'll write the registers ourselves */ 4550 4551 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4552 4553 /* set or clear MFLCN.PMCF bit depending on configuration */ 4554 if (fc_conf->mac_ctrl_frame_fwd != 0) 4555 mflcn |= IXGBE_MFLCN_PMCF; 4556 else 4557 mflcn &= ~IXGBE_MFLCN_PMCF; 4558 4559 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); 4560 IXGBE_WRITE_FLUSH(hw); 4561 4562 return 0; 4563 } 4564 4565 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err); 4566 return -EIO; 4567 } 4568 4569 /** 4570 * ixgbe_pfc_enable_generic - Enable flow control 4571 * @hw: pointer to hardware structure 4572 * @tc_num: traffic class number 4573 * Enable flow control according to the current settings. 4574 */ 4575 static int 4576 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num) 4577 { 4578 int ret_val = 0; 4579 uint32_t mflcn_reg, fccfg_reg; 4580 uint32_t reg; 4581 uint32_t fcrtl, fcrth; 4582 uint8_t i; 4583 uint8_t nb_rx_en; 4584 4585 /* Validate the water mark configuration */ 4586 if (!hw->fc.pause_time) { 4587 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4588 goto out; 4589 } 4590 4591 /* Low water mark of zero causes XOFF floods */ 4592 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 4593 /* High/Low water can not be 0 */ 4594 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) { 4595 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4596 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4597 goto out; 4598 } 4599 4600 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) { 4601 PMD_INIT_LOG(ERR, "Invalid water mark configuration"); 4602 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 4603 goto out; 4604 } 4605 } 4606 /* Negotiate the fc mode to use */ 4607 ixgbe_fc_autoneg(hw); 4608 4609 /* Disable any previous flow control settings */ 4610 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 4611 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE); 4612 4613 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 4614 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 4615 4616 switch (hw->fc.current_mode) { 4617 case ixgbe_fc_none: 4618 /* 4619 * If the count of enabled RX Priority Flow control >1, 4620 * and the TX pause can not be disabled 4621 */ 4622 nb_rx_en = 0; 4623 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4624 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4625 if (reg & IXGBE_FCRTH_FCEN) 4626 nb_rx_en++; 4627 } 4628 if (nb_rx_en > 1) 4629 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4630 break; 4631 case ixgbe_fc_rx_pause: 4632 /* 4633 * Rx Flow control is enabled and Tx Flow control is 4634 * disabled by software override. Since there really 4635 * isn't a way to advertise that we are capable of RX 4636 * Pause ONLY, we will advertise that we support both 4637 * symmetric and asymmetric Rx PAUSE. Later, we will 4638 * disable the adapter's ability to send PAUSE frames. 4639 */ 4640 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4641 /* 4642 * If the count of enabled RX Priority Flow control >1, 4643 * and the TX pause can not be disabled 4644 */ 4645 nb_rx_en = 0; 4646 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 4647 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i)); 4648 if (reg & IXGBE_FCRTH_FCEN) 4649 nb_rx_en++; 4650 } 4651 if (nb_rx_en > 1) 4652 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4653 break; 4654 case ixgbe_fc_tx_pause: 4655 /* 4656 * Tx Flow control is enabled, and Rx Flow control is 4657 * disabled by software override. 4658 */ 4659 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4660 break; 4661 case ixgbe_fc_full: 4662 /* Flow control (both Rx and Tx) is enabled by SW override. */ 4663 mflcn_reg |= IXGBE_MFLCN_RPFCE; 4664 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY; 4665 break; 4666 default: 4667 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly"); 4668 ret_val = IXGBE_ERR_CONFIG; 4669 goto out; 4670 } 4671 4672 /* Set 802.3x based flow control settings. */ 4673 mflcn_reg |= IXGBE_MFLCN_DPF; 4674 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 4675 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 4676 4677 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 4678 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 4679 hw->fc.high_water[tc_num]) { 4680 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE; 4681 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl); 4682 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN; 4683 } else { 4684 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0); 4685 /* 4686 * In order to prevent Tx hangs when the internal Tx 4687 * switch is enabled we must set the high water mark 4688 * to the maximum FCRTH value. This allows the Tx 4689 * switch to function even under heavy Rx workloads. 4690 */ 4691 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32; 4692 } 4693 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth); 4694 4695 /* Configure pause time (2 TCs per register) */ 4696 reg = hw->fc.pause_time * 0x00010001; 4697 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 4698 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 4699 4700 /* Configure flow control refresh threshold value */ 4701 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 4702 4703 out: 4704 return ret_val; 4705 } 4706 4707 static int 4708 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num) 4709 { 4710 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4711 int32_t ret_val = IXGBE_NOT_IMPLEMENTED; 4712 4713 if (hw->mac.type != ixgbe_mac_82598EB) { 4714 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num); 4715 } 4716 return ret_val; 4717 } 4718 4719 static int 4720 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf) 4721 { 4722 int err; 4723 uint32_t rx_buf_size; 4724 uint32_t max_high_water; 4725 uint8_t tc_num; 4726 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 }; 4727 struct ixgbe_hw *hw = 4728 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4729 struct ixgbe_dcb_config *dcb_config = 4730 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 4731 4732 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = { 4733 ixgbe_fc_none, 4734 ixgbe_fc_rx_pause, 4735 ixgbe_fc_tx_pause, 4736 ixgbe_fc_full 4737 }; 4738 4739 PMD_INIT_FUNC_TRACE(); 4740 4741 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map); 4742 tc_num = map[pfc_conf->priority]; 4743 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)); 4744 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size); 4745 /* 4746 * At least reserve one Ethernet frame for watermark 4747 * high_water/low_water in kilo bytes for ixgbe 4748 */ 4749 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT; 4750 if ((pfc_conf->fc.high_water > max_high_water) || 4751 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) { 4752 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB"); 4753 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water); 4754 return -EINVAL; 4755 } 4756 4757 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode]; 4758 hw->fc.pause_time = pfc_conf->fc.pause_time; 4759 hw->fc.send_xon = pfc_conf->fc.send_xon; 4760 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water; 4761 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water; 4762 4763 err = ixgbe_dcb_pfc_enable(dev, tc_num); 4764 4765 /* Not negotiated is not an error case */ 4766 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) 4767 return 0; 4768 4769 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err); 4770 return -EIO; 4771 } 4772 4773 static int 4774 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 4775 struct rte_eth_rss_reta_entry64 *reta_conf, 4776 uint16_t reta_size) 4777 { 4778 uint16_t i, sp_reta_size; 4779 uint8_t j, mask; 4780 uint32_t reta, r; 4781 uint16_t idx, shift; 4782 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4783 uint32_t reta_reg; 4784 4785 PMD_INIT_FUNC_TRACE(); 4786 4787 if (!ixgbe_rss_update_sp(hw->mac.type)) { 4788 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this " 4789 "NIC."); 4790 return -ENOTSUP; 4791 } 4792 4793 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4794 if (reta_size != sp_reta_size) { 4795 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4796 "(%d) doesn't match the number hardware can supported " 4797 "(%d)", reta_size, sp_reta_size); 4798 return -EINVAL; 4799 } 4800 4801 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4802 idx = i / RTE_RETA_GROUP_SIZE; 4803 shift = i % RTE_RETA_GROUP_SIZE; 4804 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4805 IXGBE_4_BIT_MASK); 4806 if (!mask) 4807 continue; 4808 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4809 if (mask == IXGBE_4_BIT_MASK) 4810 r = 0; 4811 else 4812 r = IXGBE_READ_REG(hw, reta_reg); 4813 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4814 if (mask & (0x1 << j)) 4815 reta |= reta_conf[idx].reta[shift + j] << 4816 (CHAR_BIT * j); 4817 else 4818 reta |= r & (IXGBE_8_BIT_MASK << 4819 (CHAR_BIT * j)); 4820 } 4821 IXGBE_WRITE_REG(hw, reta_reg, reta); 4822 } 4823 4824 return 0; 4825 } 4826 4827 static int 4828 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 4829 struct rte_eth_rss_reta_entry64 *reta_conf, 4830 uint16_t reta_size) 4831 { 4832 uint16_t i, sp_reta_size; 4833 uint8_t j, mask; 4834 uint32_t reta; 4835 uint16_t idx, shift; 4836 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4837 uint32_t reta_reg; 4838 4839 PMD_INIT_FUNC_TRACE(); 4840 sp_reta_size = ixgbe_reta_size_get(hw->mac.type); 4841 if (reta_size != sp_reta_size) { 4842 PMD_DRV_LOG(ERR, "The size of hash lookup table configured " 4843 "(%d) doesn't match the number hardware can supported " 4844 "(%d)", reta_size, sp_reta_size); 4845 return -EINVAL; 4846 } 4847 4848 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) { 4849 idx = i / RTE_RETA_GROUP_SIZE; 4850 shift = i % RTE_RETA_GROUP_SIZE; 4851 mask = (uint8_t)((reta_conf[idx].mask >> shift) & 4852 IXGBE_4_BIT_MASK); 4853 if (!mask) 4854 continue; 4855 4856 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i); 4857 reta = IXGBE_READ_REG(hw, reta_reg); 4858 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) { 4859 if (mask & (0x1 << j)) 4860 reta_conf[idx].reta[shift + j] = 4861 ((reta >> (CHAR_BIT * j)) & 4862 IXGBE_8_BIT_MASK); 4863 } 4864 } 4865 4866 return 0; 4867 } 4868 4869 static int 4870 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 4871 uint32_t index, uint32_t pool) 4872 { 4873 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4874 uint32_t enable_addr = 1; 4875 4876 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes, 4877 pool, enable_addr); 4878 } 4879 4880 static void 4881 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index) 4882 { 4883 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4884 4885 ixgbe_clear_rar(hw, index); 4886 } 4887 4888 static int 4889 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) 4890 { 4891 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 4892 4893 ixgbe_remove_rar(dev, 0); 4894 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs); 4895 4896 return 0; 4897 } 4898 4899 static bool 4900 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4901 { 4902 if (strcmp(dev->device->driver->name, drv->driver.name)) 4903 return false; 4904 4905 return true; 4906 } 4907 4908 bool 4909 is_ixgbe_supported(struct rte_eth_dev *dev) 4910 { 4911 return is_device_supported(dev, &rte_ixgbe_pmd); 4912 } 4913 4914 static int 4915 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 4916 { 4917 uint32_t hlreg0; 4918 uint32_t maxfrs; 4919 struct ixgbe_hw *hw; 4920 struct rte_eth_dev_info dev_info; 4921 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 4922 struct rte_eth_dev_data *dev_data = dev->data; 4923 4924 ixgbe_dev_info_get(dev, &dev_info); 4925 4926 /* check that mtu is within the allowed range */ 4927 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) 4928 return -EINVAL; 4929 4930 /* If device is started, refuse mtu that requires the support of 4931 * scattered packets when this feature has not been enabled before. 4932 */ 4933 if (dev_data->dev_started && !dev_data->scattered_rx && 4934 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE > 4935 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 4936 PMD_INIT_LOG(ERR, "Stop port first."); 4937 return -EINVAL; 4938 } 4939 4940 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4941 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4942 4943 /* switch to jumbo mode if needed */ 4944 if (frame_size > ETHER_MAX_LEN) { 4945 dev->data->dev_conf.rxmode.offloads |= 4946 DEV_RX_OFFLOAD_JUMBO_FRAME; 4947 hlreg0 |= IXGBE_HLREG0_JUMBOEN; 4948 } else { 4949 dev->data->dev_conf.rxmode.offloads &= 4950 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 4951 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN; 4952 } 4953 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4954 4955 /* update max frame size */ 4956 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 4957 4958 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS); 4959 maxfrs &= 0x0000FFFF; 4960 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16); 4961 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs); 4962 4963 return 0; 4964 } 4965 4966 /* 4967 * Virtual Function operations 4968 */ 4969 static void 4970 ixgbevf_intr_disable(struct rte_eth_dev *dev) 4971 { 4972 struct ixgbe_interrupt *intr = 4973 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4974 struct ixgbe_hw *hw = 4975 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4976 4977 PMD_INIT_FUNC_TRACE(); 4978 4979 /* Clear interrupt mask to stop from interrupts being generated */ 4980 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 4981 4982 IXGBE_WRITE_FLUSH(hw); 4983 4984 /* Clear mask value. */ 4985 intr->mask = 0; 4986 } 4987 4988 static void 4989 ixgbevf_intr_enable(struct rte_eth_dev *dev) 4990 { 4991 struct ixgbe_interrupt *intr = 4992 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 4993 struct ixgbe_hw *hw = 4994 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 4995 4996 PMD_INIT_FUNC_TRACE(); 4997 4998 /* VF enable interrupt autoclean */ 4999 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK); 5000 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK); 5001 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); 5002 5003 IXGBE_WRITE_FLUSH(hw); 5004 5005 /* Save IXGBE_VTEIMS value to mask. */ 5006 intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; 5007 } 5008 5009 static int 5010 ixgbevf_dev_configure(struct rte_eth_dev *dev) 5011 { 5012 struct rte_eth_conf *conf = &dev->data->dev_conf; 5013 struct ixgbe_adapter *adapter = 5014 (struct ixgbe_adapter *)dev->data->dev_private; 5015 5016 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d", 5017 dev->data->port_id); 5018 5019 /* 5020 * VF has no ability to enable/disable HW CRC 5021 * Keep the persistent behavior the same as Host PF 5022 */ 5023 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC 5024 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 5025 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip"); 5026 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC; 5027 } 5028 #else 5029 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) { 5030 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip"); 5031 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC; 5032 } 5033 #endif 5034 5035 /* 5036 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk 5037 * allocation or vector Rx preconditions we will reset it. 5038 */ 5039 adapter->rx_bulk_alloc_allowed = true; 5040 adapter->rx_vec_allowed = true; 5041 5042 return 0; 5043 } 5044 5045 static int 5046 ixgbevf_dev_start(struct rte_eth_dev *dev) 5047 { 5048 struct ixgbe_hw *hw = 5049 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5050 uint32_t intr_vector = 0; 5051 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5052 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5053 5054 int err, mask = 0; 5055 5056 PMD_INIT_FUNC_TRACE(); 5057 5058 /* Stop the link setup handler before resetting the HW. */ 5059 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5060 5061 err = hw->mac.ops.reset_hw(hw); 5062 if (err) { 5063 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err); 5064 return err; 5065 } 5066 hw->mac.get_link_status = true; 5067 5068 /* negotiate mailbox API version to use with the PF. */ 5069 ixgbevf_negotiate_api(hw); 5070 5071 ixgbevf_dev_tx_init(dev); 5072 5073 /* This can fail when allocating mbufs for descriptor rings */ 5074 err = ixgbevf_dev_rx_init(dev); 5075 if (err) { 5076 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err); 5077 ixgbe_dev_clear_queues(dev); 5078 return err; 5079 } 5080 5081 /* Set vfta */ 5082 ixgbevf_set_vfta_all(dev, 1); 5083 5084 /* Set HW strip */ 5085 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | 5086 ETH_VLAN_EXTEND_MASK; 5087 err = ixgbevf_vlan_offload_config(dev, mask); 5088 if (err) { 5089 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err); 5090 ixgbe_dev_clear_queues(dev); 5091 return err; 5092 } 5093 5094 ixgbevf_dev_rxtx_start(dev); 5095 5096 /* check and configure queue intr-vector mapping */ 5097 if (rte_intr_cap_multiple(intr_handle) && 5098 dev->data->dev_conf.intr_conf.rxq) { 5099 /* According to datasheet, only vector 0/1/2 can be used, 5100 * now only one vector is used for Rx queue 5101 */ 5102 intr_vector = 1; 5103 if (rte_intr_efd_enable(intr_handle, intr_vector)) 5104 return -1; 5105 } 5106 5107 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 5108 intr_handle->intr_vec = 5109 rte_zmalloc("intr_vec", 5110 dev->data->nb_rx_queues * sizeof(int), 0); 5111 if (intr_handle->intr_vec == NULL) { 5112 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues" 5113 " intr_vec", dev->data->nb_rx_queues); 5114 return -ENOMEM; 5115 } 5116 } 5117 ixgbevf_configure_msix(dev); 5118 5119 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt 5120 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ). 5121 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( ) 5122 * is not cleared, it will fail when following rte_intr_enable( ) tries 5123 * to map Rx queue interrupt to other VFIO vectors. 5124 * So clear uio/vfio intr/evevnfd first to avoid failure. 5125 */ 5126 rte_intr_disable(intr_handle); 5127 5128 rte_intr_enable(intr_handle); 5129 5130 /* Re-enable interrupt for VF */ 5131 ixgbevf_intr_enable(dev); 5132 5133 /* 5134 * Update link status right before return, because it may 5135 * start link configuration process in a separate thread. 5136 */ 5137 ixgbevf_dev_link_update(dev, 0); 5138 5139 return 0; 5140 } 5141 5142 static void 5143 ixgbevf_dev_stop(struct rte_eth_dev *dev) 5144 { 5145 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5146 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5147 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5148 5149 PMD_INIT_FUNC_TRACE(); 5150 5151 rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); 5152 5153 ixgbevf_intr_disable(dev); 5154 5155 hw->adapter_stopped = 1; 5156 ixgbe_stop_adapter(hw); 5157 5158 /* 5159 * Clear what we set, but we still keep shadow_vfta to 5160 * restore after device starts 5161 */ 5162 ixgbevf_set_vfta_all(dev, 0); 5163 5164 /* Clear stored conf */ 5165 dev->data->scattered_rx = 0; 5166 5167 ixgbe_dev_clear_queues(dev); 5168 5169 /* Clean datapath event and queue/vec mapping */ 5170 rte_intr_efd_disable(intr_handle); 5171 if (intr_handle->intr_vec != NULL) { 5172 rte_free(intr_handle->intr_vec); 5173 intr_handle->intr_vec = NULL; 5174 } 5175 } 5176 5177 static void 5178 ixgbevf_dev_close(struct rte_eth_dev *dev) 5179 { 5180 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5181 5182 PMD_INIT_FUNC_TRACE(); 5183 5184 ixgbe_reset_hw(hw); 5185 5186 ixgbevf_dev_stop(dev); 5187 5188 ixgbe_dev_free_queues(dev); 5189 5190 /** 5191 * Remove the VF MAC address ro ensure 5192 * that the VF traffic goes to the PF 5193 * after stop, close and detach of the VF 5194 **/ 5195 ixgbevf_remove_mac_addr(dev, 0); 5196 } 5197 5198 /* 5199 * Reset VF device 5200 */ 5201 static int 5202 ixgbevf_dev_reset(struct rte_eth_dev *dev) 5203 { 5204 int ret; 5205 5206 ret = eth_ixgbevf_dev_uninit(dev); 5207 if (ret) 5208 return ret; 5209 5210 ret = eth_ixgbevf_dev_init(dev); 5211 5212 return ret; 5213 } 5214 5215 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) 5216 { 5217 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5218 struct ixgbe_vfta *shadow_vfta = 5219 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5220 int i = 0, j = 0, vfta = 0, mask = 1; 5221 5222 for (i = 0; i < IXGBE_VFTA_SIZE; i++) { 5223 vfta = shadow_vfta->vfta[i]; 5224 if (vfta) { 5225 mask = 1; 5226 for (j = 0; j < 32; j++) { 5227 if (vfta & mask) 5228 ixgbe_set_vfta(hw, (i<<5)+j, 0, 5229 on, false); 5230 mask <<= 1; 5231 } 5232 } 5233 } 5234 5235 } 5236 5237 static int 5238 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 5239 { 5240 struct ixgbe_hw *hw = 5241 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5242 struct ixgbe_vfta *shadow_vfta = 5243 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private); 5244 uint32_t vid_idx = 0; 5245 uint32_t vid_bit = 0; 5246 int ret = 0; 5247 5248 PMD_INIT_FUNC_TRACE(); 5249 5250 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */ 5251 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false); 5252 if (ret) { 5253 PMD_INIT_LOG(ERR, "Unable to set VF vlan"); 5254 return ret; 5255 } 5256 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F); 5257 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F)); 5258 5259 /* Save what we set and retore it after device reset */ 5260 if (on) 5261 shadow_vfta->vfta[vid_idx] |= vid_bit; 5262 else 5263 shadow_vfta->vfta[vid_idx] &= ~vid_bit; 5264 5265 return 0; 5266 } 5267 5268 static void 5269 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on) 5270 { 5271 struct ixgbe_hw *hw = 5272 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5273 uint32_t ctrl; 5274 5275 PMD_INIT_FUNC_TRACE(); 5276 5277 if (queue >= hw->mac.max_rx_queues) 5278 return; 5279 5280 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue)); 5281 if (on) 5282 ctrl |= IXGBE_RXDCTL_VME; 5283 else 5284 ctrl &= ~IXGBE_RXDCTL_VME; 5285 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl); 5286 5287 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on); 5288 } 5289 5290 static int 5291 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask) 5292 { 5293 struct ixgbe_rx_queue *rxq; 5294 uint16_t i; 5295 int on = 0; 5296 5297 /* VF function only support hw strip feature, others are not support */ 5298 if (mask & ETH_VLAN_STRIP_MASK) { 5299 for (i = 0; i < dev->data->nb_rx_queues; i++) { 5300 rxq = dev->data->rx_queues[i]; 5301 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP); 5302 ixgbevf_vlan_strip_queue_set(dev, i, on); 5303 } 5304 } 5305 5306 return 0; 5307 } 5308 5309 static int 5310 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask) 5311 { 5312 ixgbe_config_vlan_strip_on_all_queues(dev, mask); 5313 5314 ixgbevf_vlan_offload_config(dev, mask); 5315 5316 return 0; 5317 } 5318 5319 int 5320 ixgbe_vt_check(struct ixgbe_hw *hw) 5321 { 5322 uint32_t reg_val; 5323 5324 /* if Virtualization Technology is enabled */ 5325 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 5326 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) { 5327 PMD_INIT_LOG(ERR, "VT must be enabled for this setting"); 5328 return -1; 5329 } 5330 5331 return 0; 5332 } 5333 5334 static uint32_t 5335 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr) 5336 { 5337 uint32_t vector = 0; 5338 5339 switch (hw->mac.mc_filter_type) { 5340 case 0: /* use bits [47:36] of the address */ 5341 vector = ((uc_addr->addr_bytes[4] >> 4) | 5342 (((uint16_t)uc_addr->addr_bytes[5]) << 4)); 5343 break; 5344 case 1: /* use bits [46:35] of the address */ 5345 vector = ((uc_addr->addr_bytes[4] >> 3) | 5346 (((uint16_t)uc_addr->addr_bytes[5]) << 5)); 5347 break; 5348 case 2: /* use bits [45:34] of the address */ 5349 vector = ((uc_addr->addr_bytes[4] >> 2) | 5350 (((uint16_t)uc_addr->addr_bytes[5]) << 6)); 5351 break; 5352 case 3: /* use bits [43:32] of the address */ 5353 vector = ((uc_addr->addr_bytes[4]) | 5354 (((uint16_t)uc_addr->addr_bytes[5]) << 8)); 5355 break; 5356 default: /* Invalid mc_filter_type */ 5357 break; 5358 } 5359 5360 /* vector can only be 12-bits or boundary will be exceeded */ 5361 vector &= 0xFFF; 5362 return vector; 5363 } 5364 5365 static int 5366 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 5367 uint8_t on) 5368 { 5369 uint32_t vector; 5370 uint32_t uta_idx; 5371 uint32_t reg_val; 5372 uint32_t uta_shift; 5373 uint32_t rc; 5374 const uint32_t ixgbe_uta_idx_mask = 0x7F; 5375 const uint32_t ixgbe_uta_bit_shift = 5; 5376 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1; 5377 const uint32_t bit1 = 0x1; 5378 5379 struct ixgbe_hw *hw = 5380 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5381 struct ixgbe_uta_info *uta_info = 5382 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5383 5384 /* The UTA table only exists on 82599 hardware and newer */ 5385 if (hw->mac.type < ixgbe_mac_82599EB) 5386 return -ENOTSUP; 5387 5388 vector = ixgbe_uta_vector(hw, mac_addr); 5389 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask; 5390 uta_shift = vector & ixgbe_uta_bit_mask; 5391 5392 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0); 5393 if (rc == on) 5394 return 0; 5395 5396 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx)); 5397 if (on) { 5398 uta_info->uta_in_use++; 5399 reg_val |= (bit1 << uta_shift); 5400 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift); 5401 } else { 5402 uta_info->uta_in_use--; 5403 reg_val &= ~(bit1 << uta_shift); 5404 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift); 5405 } 5406 5407 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val); 5408 5409 if (uta_info->uta_in_use > 0) 5410 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 5411 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 5412 else 5413 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 5414 5415 return 0; 5416 } 5417 5418 static int 5419 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) 5420 { 5421 int i; 5422 struct ixgbe_hw *hw = 5423 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5424 struct ixgbe_uta_info *uta_info = 5425 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private); 5426 5427 /* The UTA table only exists on 82599 hardware and newer */ 5428 if (hw->mac.type < ixgbe_mac_82599EB) 5429 return -ENOTSUP; 5430 5431 if (on) { 5432 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5433 uta_info->uta_shadow[i] = ~0; 5434 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); 5435 } 5436 } else { 5437 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) { 5438 uta_info->uta_shadow[i] = 0; 5439 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 5440 } 5441 } 5442 return 0; 5443 5444 } 5445 5446 uint32_t 5447 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val) 5448 { 5449 uint32_t new_val = orig_val; 5450 5451 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG) 5452 new_val |= IXGBE_VMOLR_AUPE; 5453 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC) 5454 new_val |= IXGBE_VMOLR_ROMPE; 5455 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC) 5456 new_val |= IXGBE_VMOLR_ROPE; 5457 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST) 5458 new_val |= IXGBE_VMOLR_BAM; 5459 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST) 5460 new_val |= IXGBE_VMOLR_MPE; 5461 5462 return new_val; 5463 } 5464 5465 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */ 5466 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */ 5467 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */ 5468 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */ 5469 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \ 5470 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \ 5471 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN)) 5472 5473 static int 5474 ixgbe_mirror_rule_set(struct rte_eth_dev *dev, 5475 struct rte_eth_mirror_conf *mirror_conf, 5476 uint8_t rule_id, uint8_t on) 5477 { 5478 uint32_t mr_ctl, vlvf; 5479 uint32_t mp_lsb = 0; 5480 uint32_t mv_msb = 0; 5481 uint32_t mv_lsb = 0; 5482 uint32_t mp_msb = 0; 5483 uint8_t i = 0; 5484 int reg_index = 0; 5485 uint64_t vlan_mask = 0; 5486 5487 const uint8_t pool_mask_offset = 32; 5488 const uint8_t vlan_mask_offset = 32; 5489 const uint8_t dst_pool_offset = 8; 5490 const uint8_t rule_mr_offset = 4; 5491 const uint8_t mirror_rule_mask = 0x0F; 5492 5493 struct ixgbe_mirror_info *mr_info = 5494 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5495 struct ixgbe_hw *hw = 5496 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5497 uint8_t mirror_type = 0; 5498 5499 if (ixgbe_vt_check(hw) < 0) 5500 return -ENOTSUP; 5501 5502 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5503 return -EINVAL; 5504 5505 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) { 5506 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.", 5507 mirror_conf->rule_type); 5508 return -EINVAL; 5509 } 5510 5511 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5512 mirror_type |= IXGBE_MRCTL_VLME; 5513 /* Check if vlan id is valid and find conresponding VLAN ID 5514 * index in VLVF 5515 */ 5516 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) { 5517 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) { 5518 /* search vlan id related pool vlan filter 5519 * index 5520 */ 5521 reg_index = ixgbe_find_vlvf_slot( 5522 hw, 5523 mirror_conf->vlan.vlan_id[i], 5524 false); 5525 if (reg_index < 0) 5526 return -EINVAL; 5527 vlvf = IXGBE_READ_REG(hw, 5528 IXGBE_VLVF(reg_index)); 5529 if ((vlvf & IXGBE_VLVF_VIEN) && 5530 ((vlvf & IXGBE_VLVF_VLANID_MASK) == 5531 mirror_conf->vlan.vlan_id[i])) 5532 vlan_mask |= (1ULL << reg_index); 5533 else 5534 return -EINVAL; 5535 } 5536 } 5537 5538 if (on) { 5539 mv_lsb = vlan_mask & 0xFFFFFFFF; 5540 mv_msb = vlan_mask >> vlan_mask_offset; 5541 5542 mr_info->mr_conf[rule_id].vlan.vlan_mask = 5543 mirror_conf->vlan.vlan_mask; 5544 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) { 5545 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) 5546 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 5547 mirror_conf->vlan.vlan_id[i]; 5548 } 5549 } else { 5550 mv_lsb = 0; 5551 mv_msb = 0; 5552 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0; 5553 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) 5554 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0; 5555 } 5556 } 5557 5558 /** 5559 * if enable pool mirror, write related pool mask register,if disable 5560 * pool mirror, clear PFMRVM register 5561 */ 5562 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5563 mirror_type |= IXGBE_MRCTL_VPME; 5564 if (on) { 5565 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF; 5566 mp_msb = mirror_conf->pool_mask >> pool_mask_offset; 5567 mr_info->mr_conf[rule_id].pool_mask = 5568 mirror_conf->pool_mask; 5569 5570 } else { 5571 mp_lsb = 0; 5572 mp_msb = 0; 5573 mr_info->mr_conf[rule_id].pool_mask = 0; 5574 } 5575 } 5576 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT) 5577 mirror_type |= IXGBE_MRCTL_UPME; 5578 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT) 5579 mirror_type |= IXGBE_MRCTL_DPME; 5580 5581 /* read mirror control register and recalculate it */ 5582 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id)); 5583 5584 if (on) { 5585 mr_ctl |= mirror_type; 5586 mr_ctl &= mirror_rule_mask; 5587 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset; 5588 } else { 5589 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask); 5590 } 5591 5592 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type; 5593 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool; 5594 5595 /* write mirrror control register */ 5596 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5597 5598 /* write pool mirrror control register */ 5599 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) { 5600 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb); 5601 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), 5602 mp_msb); 5603 } 5604 /* write VLAN mirrror control register */ 5605 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) { 5606 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb); 5607 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), 5608 mv_msb); 5609 } 5610 5611 return 0; 5612 } 5613 5614 static int 5615 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id) 5616 { 5617 int mr_ctl = 0; 5618 uint32_t lsb_val = 0; 5619 uint32_t msb_val = 0; 5620 const uint8_t rule_mr_offset = 4; 5621 5622 struct ixgbe_hw *hw = 5623 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5624 struct ixgbe_mirror_info *mr_info = 5625 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private)); 5626 5627 if (ixgbe_vt_check(hw) < 0) 5628 return -ENOTSUP; 5629 5630 if (rule_id >= IXGBE_MAX_MIRROR_RULES) 5631 return -EINVAL; 5632 5633 memset(&mr_info->mr_conf[rule_id], 0, 5634 sizeof(struct rte_eth_mirror_conf)); 5635 5636 /* clear PFVMCTL register */ 5637 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl); 5638 5639 /* clear pool mask register */ 5640 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val); 5641 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val); 5642 5643 /* clear vlan mask register */ 5644 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val); 5645 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val); 5646 5647 return 0; 5648 } 5649 5650 static int 5651 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5652 { 5653 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5654 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5655 struct ixgbe_interrupt *intr = 5656 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5657 struct ixgbe_hw *hw = 5658 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5659 uint32_t vec = IXGBE_MISC_VEC_ID; 5660 5661 if (rte_intr_allow_others(intr_handle)) 5662 vec = IXGBE_RX_VEC_START; 5663 intr->mask |= (1 << vec); 5664 RTE_SET_USED(queue_id); 5665 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5666 5667 rte_intr_enable(intr_handle); 5668 5669 return 0; 5670 } 5671 5672 static int 5673 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5674 { 5675 struct ixgbe_interrupt *intr = 5676 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5677 struct ixgbe_hw *hw = 5678 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5679 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5680 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5681 uint32_t vec = IXGBE_MISC_VEC_ID; 5682 5683 if (rte_intr_allow_others(intr_handle)) 5684 vec = IXGBE_RX_VEC_START; 5685 intr->mask &= ~(1 << vec); 5686 RTE_SET_USED(queue_id); 5687 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); 5688 5689 return 0; 5690 } 5691 5692 static int 5693 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) 5694 { 5695 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5696 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5697 uint32_t mask; 5698 struct ixgbe_hw *hw = 5699 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5700 struct ixgbe_interrupt *intr = 5701 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5702 5703 if (queue_id < 16) { 5704 ixgbe_disable_intr(hw); 5705 intr->mask |= (1 << queue_id); 5706 ixgbe_enable_intr(dev); 5707 } else if (queue_id < 32) { 5708 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5709 mask &= (1 << queue_id); 5710 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5711 } else if (queue_id < 64) { 5712 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5713 mask &= (1 << (queue_id - 32)); 5714 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5715 } 5716 rte_intr_enable(intr_handle); 5717 5718 return 0; 5719 } 5720 5721 static int 5722 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) 5723 { 5724 uint32_t mask; 5725 struct ixgbe_hw *hw = 5726 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5727 struct ixgbe_interrupt *intr = 5728 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 5729 5730 if (queue_id < 16) { 5731 ixgbe_disable_intr(hw); 5732 intr->mask &= ~(1 << queue_id); 5733 ixgbe_enable_intr(dev); 5734 } else if (queue_id < 32) { 5735 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0)); 5736 mask &= ~(1 << queue_id); 5737 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); 5738 } else if (queue_id < 64) { 5739 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1)); 5740 mask &= ~(1 << (queue_id - 32)); 5741 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); 5742 } 5743 5744 return 0; 5745 } 5746 5747 static void 5748 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5749 uint8_t queue, uint8_t msix_vector) 5750 { 5751 uint32_t tmp, idx; 5752 5753 if (direction == -1) { 5754 /* other causes */ 5755 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5756 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC); 5757 tmp &= ~0xFF; 5758 tmp |= msix_vector; 5759 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp); 5760 } else { 5761 /* rx or tx cause */ 5762 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5763 idx = ((16 * (queue & 1)) + (8 * direction)); 5764 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1)); 5765 tmp &= ~(0xFF << idx); 5766 tmp |= (msix_vector << idx); 5767 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp); 5768 } 5769 } 5770 5771 /** 5772 * set the IVAR registers, mapping interrupt causes to vectors 5773 * @param hw 5774 * pointer to ixgbe_hw struct 5775 * @direction 5776 * 0 for Rx, 1 for Tx, -1 for other causes 5777 * @queue 5778 * queue to map the corresponding interrupt to 5779 * @msix_vector 5780 * the vector to map to the corresponding queue 5781 */ 5782 static void 5783 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction, 5784 uint8_t queue, uint8_t msix_vector) 5785 { 5786 uint32_t tmp, idx; 5787 5788 msix_vector |= IXGBE_IVAR_ALLOC_VAL; 5789 if (hw->mac.type == ixgbe_mac_82598EB) { 5790 if (direction == -1) 5791 direction = 0; 5792 idx = (((direction * 64) + queue) >> 2) & 0x1F; 5793 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx)); 5794 tmp &= ~(0xFF << (8 * (queue & 0x3))); 5795 tmp |= (msix_vector << (8 * (queue & 0x3))); 5796 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp); 5797 } else if ((hw->mac.type == ixgbe_mac_82599EB) || 5798 (hw->mac.type == ixgbe_mac_X540) || 5799 (hw->mac.type == ixgbe_mac_X550)) { 5800 if (direction == -1) { 5801 /* other causes */ 5802 idx = ((queue & 1) * 8); 5803 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC); 5804 tmp &= ~(0xFF << idx); 5805 tmp |= (msix_vector << idx); 5806 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp); 5807 } else { 5808 /* rx or tx causes */ 5809 idx = ((16 * (queue & 1)) + (8 * direction)); 5810 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); 5811 tmp &= ~(0xFF << idx); 5812 tmp |= (msix_vector << idx); 5813 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp); 5814 } 5815 } 5816 } 5817 5818 static void 5819 ixgbevf_configure_msix(struct rte_eth_dev *dev) 5820 { 5821 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5822 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5823 struct ixgbe_hw *hw = 5824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5825 uint32_t q_idx; 5826 uint32_t vector_idx = IXGBE_MISC_VEC_ID; 5827 uint32_t base = IXGBE_MISC_VEC_ID; 5828 5829 /* Configure VF other cause ivar */ 5830 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx); 5831 5832 /* won't configure msix register if no mapping is done 5833 * between intr vector and event fd. 5834 */ 5835 if (!rte_intr_dp_is_en(intr_handle)) 5836 return; 5837 5838 if (rte_intr_allow_others(intr_handle)) { 5839 base = IXGBE_RX_VEC_START; 5840 vector_idx = IXGBE_RX_VEC_START; 5841 } 5842 5843 /* Configure all RX queues of VF */ 5844 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) { 5845 /* Force all queue use vector 0, 5846 * as IXGBE_VF_MAXMSIVECOTR = 1 5847 */ 5848 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx); 5849 intr_handle->intr_vec[q_idx] = vector_idx; 5850 if (vector_idx < base + intr_handle->nb_efd - 1) 5851 vector_idx++; 5852 } 5853 5854 /* As RX queue setting above show, all queues use the vector 0. 5855 * Set only the ITR value of IXGBE_MISC_VEC_ID. 5856 */ 5857 IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID), 5858 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5859 | IXGBE_EITR_CNT_WDIS); 5860 } 5861 5862 /** 5863 * Sets up the hardware to properly generate MSI-X interrupts 5864 * @hw 5865 * board private structure 5866 */ 5867 static void 5868 ixgbe_configure_msix(struct rte_eth_dev *dev) 5869 { 5870 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 5871 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 5872 struct ixgbe_hw *hw = 5873 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5874 uint32_t queue_id, base = IXGBE_MISC_VEC_ID; 5875 uint32_t vec = IXGBE_MISC_VEC_ID; 5876 uint32_t mask; 5877 uint32_t gpie; 5878 5879 /* won't configure msix register if no mapping is done 5880 * between intr vector and event fd 5881 * but if misx has been enabled already, need to configure 5882 * auto clean, auto mask and throttling. 5883 */ 5884 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5885 if (!rte_intr_dp_is_en(intr_handle) && 5886 !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT))) 5887 return; 5888 5889 if (rte_intr_allow_others(intr_handle)) 5890 vec = base = IXGBE_RX_VEC_START; 5891 5892 /* setup GPIE for MSI-x mode */ 5893 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); 5894 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | 5895 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME; 5896 /* auto clearing and auto setting corresponding bits in EIMS 5897 * when MSI-X interrupt is triggered 5898 */ 5899 if (hw->mac.type == ixgbe_mac_82598EB) { 5900 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); 5901 } else { 5902 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); 5903 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); 5904 } 5905 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); 5906 5907 /* Populate the IVAR table and set the ITR values to the 5908 * corresponding register. 5909 */ 5910 if (rte_intr_dp_is_en(intr_handle)) { 5911 for (queue_id = 0; queue_id < dev->data->nb_rx_queues; 5912 queue_id++) { 5913 /* by default, 1:1 mapping */ 5914 ixgbe_set_ivar_map(hw, 0, queue_id, vec); 5915 intr_handle->intr_vec[queue_id] = vec; 5916 if (vec < base + intr_handle->nb_efd - 1) 5917 vec++; 5918 } 5919 5920 switch (hw->mac.type) { 5921 case ixgbe_mac_82598EB: 5922 ixgbe_set_ivar_map(hw, -1, 5923 IXGBE_IVAR_OTHER_CAUSES_INDEX, 5924 IXGBE_MISC_VEC_ID); 5925 break; 5926 case ixgbe_mac_82599EB: 5927 case ixgbe_mac_X540: 5928 case ixgbe_mac_X550: 5929 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID); 5930 break; 5931 default: 5932 break; 5933 } 5934 } 5935 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID), 5936 IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT) 5937 | IXGBE_EITR_CNT_WDIS); 5938 5939 /* set up to autoclear timer, and the vectors */ 5940 mask = IXGBE_EIMS_ENABLE_MASK; 5941 mask &= ~(IXGBE_EIMS_OTHER | 5942 IXGBE_EIMS_MAILBOX | 5943 IXGBE_EIMS_LSC); 5944 5945 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask); 5946 } 5947 5948 int 5949 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, 5950 uint16_t queue_idx, uint16_t tx_rate) 5951 { 5952 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 5953 struct rte_eth_rxmode *rxmode; 5954 uint32_t rf_dec, rf_int; 5955 uint32_t bcnrc_val; 5956 uint16_t link_speed = dev->data->dev_link.link_speed; 5957 5958 if (queue_idx >= hw->mac.max_tx_queues) 5959 return -EINVAL; 5960 5961 if (tx_rate != 0) { 5962 /* Calculate the rate factor values to set */ 5963 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate; 5964 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate; 5965 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate; 5966 5967 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA; 5968 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) & 5969 IXGBE_RTTBCNRC_RF_INT_MASK_M); 5970 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK); 5971 } else { 5972 bcnrc_val = 0; 5973 } 5974 5975 rxmode = &dev->data->dev_conf.rxmode; 5976 /* 5977 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 5978 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise 5979 * set as 0x4. 5980 */ 5981 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) && 5982 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE)) 5983 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 5984 IXGBE_MMW_SIZE_JUMBO_FRAME); 5985 else 5986 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM, 5987 IXGBE_MMW_SIZE_DEFAULT); 5988 5989 /* Set RTTBCNRC of queue X */ 5990 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx); 5991 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); 5992 IXGBE_WRITE_FLUSH(hw); 5993 5994 return 0; 5995 } 5996 5997 static int 5998 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr, 5999 __attribute__((unused)) uint32_t index, 6000 __attribute__((unused)) uint32_t pool) 6001 { 6002 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6003 int diag; 6004 6005 /* 6006 * On a 82599 VF, adding again the same MAC addr is not an idempotent 6007 * operation. Trap this case to avoid exhausting the [very limited] 6008 * set of PF resources used to store VF MAC addresses. 6009 */ 6010 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0) 6011 return -1; 6012 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6013 if (diag != 0) 6014 PMD_DRV_LOG(ERR, "Unable to add MAC address " 6015 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d", 6016 mac_addr->addr_bytes[0], 6017 mac_addr->addr_bytes[1], 6018 mac_addr->addr_bytes[2], 6019 mac_addr->addr_bytes[3], 6020 mac_addr->addr_bytes[4], 6021 mac_addr->addr_bytes[5], 6022 diag); 6023 return diag; 6024 } 6025 6026 static void 6027 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index) 6028 { 6029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6030 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr; 6031 struct ether_addr *mac_addr; 6032 uint32_t i; 6033 int diag; 6034 6035 /* 6036 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does 6037 * not support the deletion of a given MAC address. 6038 * Instead, it imposes to delete all MAC addresses, then to add again 6039 * all MAC addresses with the exception of the one to be deleted. 6040 */ 6041 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL); 6042 6043 /* 6044 * Add again all MAC addresses, with the exception of the deleted one 6045 * and of the permanent MAC address. 6046 */ 6047 for (i = 0, mac_addr = dev->data->mac_addrs; 6048 i < hw->mac.num_rar_entries; i++, mac_addr++) { 6049 /* Skip the deleted MAC address */ 6050 if (i == index) 6051 continue; 6052 /* Skip NULL MAC addresses */ 6053 if (is_zero_ether_addr(mac_addr)) 6054 continue; 6055 /* Skip the permanent MAC address */ 6056 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0) 6057 continue; 6058 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes); 6059 if (diag != 0) 6060 PMD_DRV_LOG(ERR, 6061 "Adding again MAC address " 6062 "%02x:%02x:%02x:%02x:%02x:%02x failed " 6063 "diag=%d", 6064 mac_addr->addr_bytes[0], 6065 mac_addr->addr_bytes[1], 6066 mac_addr->addr_bytes[2], 6067 mac_addr->addr_bytes[3], 6068 mac_addr->addr_bytes[4], 6069 mac_addr->addr_bytes[5], 6070 diag); 6071 } 6072 } 6073 6074 static int 6075 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr) 6076 { 6077 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6078 6079 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0); 6080 6081 return 0; 6082 } 6083 6084 int 6085 ixgbe_syn_filter_set(struct rte_eth_dev *dev, 6086 struct rte_eth_syn_filter *filter, 6087 bool add) 6088 { 6089 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6090 struct ixgbe_filter_info *filter_info = 6091 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6092 uint32_t syn_info; 6093 uint32_t synqf; 6094 6095 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6096 return -EINVAL; 6097 6098 syn_info = filter_info->syn_info; 6099 6100 if (add) { 6101 if (syn_info & IXGBE_SYN_FILTER_ENABLE) 6102 return -EINVAL; 6103 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) & 6104 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE); 6105 6106 if (filter->hig_pri) 6107 synqf |= IXGBE_SYN_FILTER_SYNQFP; 6108 else 6109 synqf &= ~IXGBE_SYN_FILTER_SYNQFP; 6110 } else { 6111 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6112 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE)) 6113 return -ENOENT; 6114 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE); 6115 } 6116 6117 filter_info->syn_info = synqf; 6118 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 6119 IXGBE_WRITE_FLUSH(hw); 6120 return 0; 6121 } 6122 6123 static int 6124 ixgbe_syn_filter_get(struct rte_eth_dev *dev, 6125 struct rte_eth_syn_filter *filter) 6126 { 6127 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6128 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF); 6129 6130 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 6131 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0; 6132 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1); 6133 return 0; 6134 } 6135 return -ENOENT; 6136 } 6137 6138 static int 6139 ixgbe_syn_filter_handle(struct rte_eth_dev *dev, 6140 enum rte_filter_op filter_op, 6141 void *arg) 6142 { 6143 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6144 int ret; 6145 6146 MAC_TYPE_FILTER_SUP(hw->mac.type); 6147 6148 if (filter_op == RTE_ETH_FILTER_NOP) 6149 return 0; 6150 6151 if (arg == NULL) { 6152 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u", 6153 filter_op); 6154 return -EINVAL; 6155 } 6156 6157 switch (filter_op) { 6158 case RTE_ETH_FILTER_ADD: 6159 ret = ixgbe_syn_filter_set(dev, 6160 (struct rte_eth_syn_filter *)arg, 6161 TRUE); 6162 break; 6163 case RTE_ETH_FILTER_DELETE: 6164 ret = ixgbe_syn_filter_set(dev, 6165 (struct rte_eth_syn_filter *)arg, 6166 FALSE); 6167 break; 6168 case RTE_ETH_FILTER_GET: 6169 ret = ixgbe_syn_filter_get(dev, 6170 (struct rte_eth_syn_filter *)arg); 6171 break; 6172 default: 6173 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op); 6174 ret = -EINVAL; 6175 break; 6176 } 6177 6178 return ret; 6179 } 6180 6181 6182 static inline enum ixgbe_5tuple_protocol 6183 convert_protocol_type(uint8_t protocol_value) 6184 { 6185 if (protocol_value == IPPROTO_TCP) 6186 return IXGBE_FILTER_PROTOCOL_TCP; 6187 else if (protocol_value == IPPROTO_UDP) 6188 return IXGBE_FILTER_PROTOCOL_UDP; 6189 else if (protocol_value == IPPROTO_SCTP) 6190 return IXGBE_FILTER_PROTOCOL_SCTP; 6191 else 6192 return IXGBE_FILTER_PROTOCOL_NONE; 6193 } 6194 6195 /* inject a 5-tuple filter to HW */ 6196 static inline void 6197 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev, 6198 struct ixgbe_5tuple_filter *filter) 6199 { 6200 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6201 int i; 6202 uint32_t ftqf, sdpqf; 6203 uint32_t l34timir = 0; 6204 uint8_t mask = 0xff; 6205 6206 i = filter->index; 6207 6208 sdpqf = (uint32_t)(filter->filter_info.dst_port << 6209 IXGBE_SDPQF_DSTPORT_SHIFT); 6210 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT); 6211 6212 ftqf = (uint32_t)(filter->filter_info.proto & 6213 IXGBE_FTQF_PROTOCOL_MASK); 6214 ftqf |= (uint32_t)((filter->filter_info.priority & 6215 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT); 6216 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */ 6217 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK; 6218 if (filter->filter_info.dst_ip_mask == 0) 6219 mask &= IXGBE_FTQF_DEST_ADDR_MASK; 6220 if (filter->filter_info.src_port_mask == 0) 6221 mask &= IXGBE_FTQF_SOURCE_PORT_MASK; 6222 if (filter->filter_info.dst_port_mask == 0) 6223 mask &= IXGBE_FTQF_DEST_PORT_MASK; 6224 if (filter->filter_info.proto_mask == 0) 6225 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK; 6226 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT; 6227 ftqf |= IXGBE_FTQF_POOL_MASK_EN; 6228 ftqf |= IXGBE_FTQF_QUEUE_ENABLE; 6229 6230 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip); 6231 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip); 6232 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf); 6233 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf); 6234 6235 l34timir |= IXGBE_L34T_IMIR_RESERVE; 6236 l34timir |= (uint32_t)(filter->queue << 6237 IXGBE_L34T_IMIR_QUEUE_SHIFT); 6238 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir); 6239 } 6240 6241 /* 6242 * add a 5tuple filter 6243 * 6244 * @param 6245 * dev: Pointer to struct rte_eth_dev. 6246 * index: the index the filter allocates. 6247 * filter: ponter to the filter that will be added. 6248 * rx_queue: the queue id the filter assigned to. 6249 * 6250 * @return 6251 * - On success, zero. 6252 * - On failure, a negative value. 6253 */ 6254 static int 6255 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, 6256 struct ixgbe_5tuple_filter *filter) 6257 { 6258 struct ixgbe_filter_info *filter_info = 6259 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6260 int i, idx, shift; 6261 6262 /* 6263 * look for an unused 5tuple filter index, 6264 * and insert the filter to list. 6265 */ 6266 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) { 6267 idx = i / (sizeof(uint32_t) * NBBY); 6268 shift = i % (sizeof(uint32_t) * NBBY); 6269 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) { 6270 filter_info->fivetuple_mask[idx] |= 1 << shift; 6271 filter->index = i; 6272 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list, 6273 filter, 6274 entries); 6275 break; 6276 } 6277 } 6278 if (i >= IXGBE_MAX_FTQF_FILTERS) { 6279 PMD_DRV_LOG(ERR, "5tuple filters are full."); 6280 return -ENOSYS; 6281 } 6282 6283 ixgbe_inject_5tuple_filter(dev, filter); 6284 6285 return 0; 6286 } 6287 6288 /* 6289 * remove a 5tuple filter 6290 * 6291 * @param 6292 * dev: Pointer to struct rte_eth_dev. 6293 * filter: the pointer of the filter will be removed. 6294 */ 6295 static void 6296 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev, 6297 struct ixgbe_5tuple_filter *filter) 6298 { 6299 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6300 struct ixgbe_filter_info *filter_info = 6301 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6302 uint16_t index = filter->index; 6303 6304 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &= 6305 ~(1 << (index % (sizeof(uint32_t) * NBBY))); 6306 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries); 6307 rte_free(filter); 6308 6309 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0); 6310 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0); 6311 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0); 6312 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0); 6313 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0); 6314 } 6315 6316 static int 6317 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 6318 { 6319 struct ixgbe_hw *hw; 6320 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 6321 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode; 6322 6323 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6324 6325 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN)) 6326 return -EINVAL; 6327 6328 /* refuse mtu that requires the support of scattered packets when this 6329 * feature has not been enabled before. 6330 */ 6331 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) && 6332 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE > 6333 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) 6334 return -EINVAL; 6335 6336 /* 6337 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU 6338 * request of the version 2.0 of the mailbox API. 6339 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0 6340 * of the mailbox API. 6341 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers 6342 * prior to 3.11.33 which contains the following change: 6343 * "ixgbe: Enable jumbo frames support w/ SR-IOV" 6344 */ 6345 ixgbevf_rlpml_set_vf(hw, max_frame); 6346 6347 /* update max frame size */ 6348 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame; 6349 return 0; 6350 } 6351 6352 static inline struct ixgbe_5tuple_filter * 6353 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list, 6354 struct ixgbe_5tuple_filter_info *key) 6355 { 6356 struct ixgbe_5tuple_filter *it; 6357 6358 TAILQ_FOREACH(it, filter_list, entries) { 6359 if (memcmp(key, &it->filter_info, 6360 sizeof(struct ixgbe_5tuple_filter_info)) == 0) { 6361 return it; 6362 } 6363 } 6364 return NULL; 6365 } 6366 6367 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/ 6368 static inline int 6369 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter, 6370 struct ixgbe_5tuple_filter_info *filter_info) 6371 { 6372 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM || 6373 filter->priority > IXGBE_5TUPLE_MAX_PRI || 6374 filter->priority < IXGBE_5TUPLE_MIN_PRI) 6375 return -EINVAL; 6376 6377 switch (filter->dst_ip_mask) { 6378 case UINT32_MAX: 6379 filter_info->dst_ip_mask = 0; 6380 filter_info->dst_ip = filter->dst_ip; 6381 break; 6382 case 0: 6383 filter_info->dst_ip_mask = 1; 6384 break; 6385 default: 6386 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 6387 return -EINVAL; 6388 } 6389 6390 switch (filter->src_ip_mask) { 6391 case UINT32_MAX: 6392 filter_info->src_ip_mask = 0; 6393 filter_info->src_ip = filter->src_ip; 6394 break; 6395 case 0: 6396 filter_info->src_ip_mask = 1; 6397 break; 6398 default: 6399 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 6400 return -EINVAL; 6401 } 6402 6403 switch (filter->dst_port_mask) { 6404 case UINT16_MAX: 6405 filter_info->dst_port_mask = 0; 6406 filter_info->dst_port = filter->dst_port; 6407 break; 6408 case 0: 6409 filter_info->dst_port_mask = 1; 6410 break; 6411 default: 6412 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 6413 return -EINVAL; 6414 } 6415 6416 switch (filter->src_port_mask) { 6417 case UINT16_MAX: 6418 filter_info->src_port_mask = 0; 6419 filter_info->src_port = filter->src_port; 6420 break; 6421 case 0: 6422 filter_info->src_port_mask = 1; 6423 break; 6424 default: 6425 PMD_DRV_LOG(ERR, "invalid src_port mask."); 6426 return -EINVAL; 6427 } 6428 6429 switch (filter->proto_mask) { 6430 case UINT8_MAX: 6431 filter_info->proto_mask = 0; 6432 filter_info->proto = 6433 convert_protocol_type(filter->proto); 6434 break; 6435 case 0: 6436 filter_info->proto_mask = 1; 6437 break; 6438 default: 6439 PMD_DRV_LOG(ERR, "invalid protocol mask."); 6440 return -EINVAL; 6441 } 6442 6443 filter_info->priority = (uint8_t)filter->priority; 6444 return 0; 6445 } 6446 6447 /* 6448 * add or delete a ntuple filter 6449 * 6450 * @param 6451 * dev: Pointer to struct rte_eth_dev. 6452 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6453 * add: if true, add filter, if false, remove filter 6454 * 6455 * @return 6456 * - On success, zero. 6457 * - On failure, a negative value. 6458 */ 6459 int 6460 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev, 6461 struct rte_eth_ntuple_filter *ntuple_filter, 6462 bool add) 6463 { 6464 struct ixgbe_filter_info *filter_info = 6465 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6466 struct ixgbe_5tuple_filter_info filter_5tuple; 6467 struct ixgbe_5tuple_filter *filter; 6468 int ret; 6469 6470 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6471 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6472 return -EINVAL; 6473 } 6474 6475 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6476 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6477 if (ret < 0) 6478 return ret; 6479 6480 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6481 &filter_5tuple); 6482 if (filter != NULL && add) { 6483 PMD_DRV_LOG(ERR, "filter exists."); 6484 return -EEXIST; 6485 } 6486 if (filter == NULL && !add) { 6487 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6488 return -ENOENT; 6489 } 6490 6491 if (add) { 6492 filter = rte_zmalloc("ixgbe_5tuple_filter", 6493 sizeof(struct ixgbe_5tuple_filter), 0); 6494 if (filter == NULL) 6495 return -ENOMEM; 6496 rte_memcpy(&filter->filter_info, 6497 &filter_5tuple, 6498 sizeof(struct ixgbe_5tuple_filter_info)); 6499 filter->queue = ntuple_filter->queue; 6500 ret = ixgbe_add_5tuple_filter(dev, filter); 6501 if (ret < 0) { 6502 rte_free(filter); 6503 return ret; 6504 } 6505 } else 6506 ixgbe_remove_5tuple_filter(dev, filter); 6507 6508 return 0; 6509 } 6510 6511 /* 6512 * get a ntuple filter 6513 * 6514 * @param 6515 * dev: Pointer to struct rte_eth_dev. 6516 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter 6517 * 6518 * @return 6519 * - On success, zero. 6520 * - On failure, a negative value. 6521 */ 6522 static int 6523 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev, 6524 struct rte_eth_ntuple_filter *ntuple_filter) 6525 { 6526 struct ixgbe_filter_info *filter_info = 6527 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6528 struct ixgbe_5tuple_filter_info filter_5tuple; 6529 struct ixgbe_5tuple_filter *filter; 6530 int ret; 6531 6532 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) { 6533 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 6534 return -EINVAL; 6535 } 6536 6537 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info)); 6538 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple); 6539 if (ret < 0) 6540 return ret; 6541 6542 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list, 6543 &filter_5tuple); 6544 if (filter == NULL) { 6545 PMD_DRV_LOG(ERR, "filter doesn't exist."); 6546 return -ENOENT; 6547 } 6548 ntuple_filter->queue = filter->queue; 6549 return 0; 6550 } 6551 6552 /* 6553 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter. 6554 * @dev: pointer to rte_eth_dev structure 6555 * @filter_op:operation will be taken. 6556 * @arg: a pointer to specific structure corresponding to the filter_op 6557 * 6558 * @return 6559 * - On success, zero. 6560 * - On failure, a negative value. 6561 */ 6562 static int 6563 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev, 6564 enum rte_filter_op filter_op, 6565 void *arg) 6566 { 6567 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6568 int ret; 6569 6570 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type); 6571 6572 if (filter_op == RTE_ETH_FILTER_NOP) 6573 return 0; 6574 6575 if (arg == NULL) { 6576 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6577 filter_op); 6578 return -EINVAL; 6579 } 6580 6581 switch (filter_op) { 6582 case RTE_ETH_FILTER_ADD: 6583 ret = ixgbe_add_del_ntuple_filter(dev, 6584 (struct rte_eth_ntuple_filter *)arg, 6585 TRUE); 6586 break; 6587 case RTE_ETH_FILTER_DELETE: 6588 ret = ixgbe_add_del_ntuple_filter(dev, 6589 (struct rte_eth_ntuple_filter *)arg, 6590 FALSE); 6591 break; 6592 case RTE_ETH_FILTER_GET: 6593 ret = ixgbe_get_ntuple_filter(dev, 6594 (struct rte_eth_ntuple_filter *)arg); 6595 break; 6596 default: 6597 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6598 ret = -EINVAL; 6599 break; 6600 } 6601 return ret; 6602 } 6603 6604 int 6605 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev, 6606 struct rte_eth_ethertype_filter *filter, 6607 bool add) 6608 { 6609 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6610 struct ixgbe_filter_info *filter_info = 6611 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6612 uint32_t etqf = 0; 6613 uint32_t etqs = 0; 6614 int ret; 6615 struct ixgbe_ethertype_filter ethertype_filter; 6616 6617 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM) 6618 return -EINVAL; 6619 6620 if (filter->ether_type == ETHER_TYPE_IPv4 || 6621 filter->ether_type == ETHER_TYPE_IPv6) { 6622 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in" 6623 " ethertype filter.", filter->ether_type); 6624 return -EINVAL; 6625 } 6626 6627 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) { 6628 PMD_DRV_LOG(ERR, "mac compare is unsupported."); 6629 return -EINVAL; 6630 } 6631 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) { 6632 PMD_DRV_LOG(ERR, "drop option is unsupported."); 6633 return -EINVAL; 6634 } 6635 6636 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6637 if (ret >= 0 && add) { 6638 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.", 6639 filter->ether_type); 6640 return -EEXIST; 6641 } 6642 if (ret < 0 && !add) { 6643 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6644 filter->ether_type); 6645 return -ENOENT; 6646 } 6647 6648 if (add) { 6649 etqf = IXGBE_ETQF_FILTER_EN; 6650 etqf |= (uint32_t)filter->ether_type; 6651 etqs |= (uint32_t)((filter->queue << 6652 IXGBE_ETQS_RX_QUEUE_SHIFT) & 6653 IXGBE_ETQS_RX_QUEUE); 6654 etqs |= IXGBE_ETQS_QUEUE_EN; 6655 6656 ethertype_filter.ethertype = filter->ether_type; 6657 ethertype_filter.etqf = etqf; 6658 ethertype_filter.etqs = etqs; 6659 ethertype_filter.conf = FALSE; 6660 ret = ixgbe_ethertype_filter_insert(filter_info, 6661 ðertype_filter); 6662 if (ret < 0) { 6663 PMD_DRV_LOG(ERR, "ethertype filters are full."); 6664 return -ENOSPC; 6665 } 6666 } else { 6667 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret); 6668 if (ret < 0) 6669 return -ENOSYS; 6670 } 6671 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf); 6672 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs); 6673 IXGBE_WRITE_FLUSH(hw); 6674 6675 return 0; 6676 } 6677 6678 static int 6679 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, 6680 struct rte_eth_ethertype_filter *filter) 6681 { 6682 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6683 struct ixgbe_filter_info *filter_info = 6684 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 6685 uint32_t etqf, etqs; 6686 int ret; 6687 6688 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type); 6689 if (ret < 0) { 6690 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.", 6691 filter->ether_type); 6692 return -ENOENT; 6693 } 6694 6695 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret)); 6696 if (etqf & IXGBE_ETQF_FILTER_EN) { 6697 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret)); 6698 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE; 6699 filter->flags = 0; 6700 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> 6701 IXGBE_ETQS_RX_QUEUE_SHIFT; 6702 return 0; 6703 } 6704 return -ENOENT; 6705 } 6706 6707 /* 6708 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter. 6709 * @dev: pointer to rte_eth_dev structure 6710 * @filter_op:operation will be taken. 6711 * @arg: a pointer to specific structure corresponding to the filter_op 6712 */ 6713 static int 6714 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev, 6715 enum rte_filter_op filter_op, 6716 void *arg) 6717 { 6718 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6719 int ret; 6720 6721 MAC_TYPE_FILTER_SUP(hw->mac.type); 6722 6723 if (filter_op == RTE_ETH_FILTER_NOP) 6724 return 0; 6725 6726 if (arg == NULL) { 6727 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 6728 filter_op); 6729 return -EINVAL; 6730 } 6731 6732 switch (filter_op) { 6733 case RTE_ETH_FILTER_ADD: 6734 ret = ixgbe_add_del_ethertype_filter(dev, 6735 (struct rte_eth_ethertype_filter *)arg, 6736 TRUE); 6737 break; 6738 case RTE_ETH_FILTER_DELETE: 6739 ret = ixgbe_add_del_ethertype_filter(dev, 6740 (struct rte_eth_ethertype_filter *)arg, 6741 FALSE); 6742 break; 6743 case RTE_ETH_FILTER_GET: 6744 ret = ixgbe_get_ethertype_filter(dev, 6745 (struct rte_eth_ethertype_filter *)arg); 6746 break; 6747 default: 6748 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 6749 ret = -EINVAL; 6750 break; 6751 } 6752 return ret; 6753 } 6754 6755 static int 6756 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 6757 enum rte_filter_type filter_type, 6758 enum rte_filter_op filter_op, 6759 void *arg) 6760 { 6761 int ret = 0; 6762 6763 switch (filter_type) { 6764 case RTE_ETH_FILTER_NTUPLE: 6765 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg); 6766 break; 6767 case RTE_ETH_FILTER_ETHERTYPE: 6768 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg); 6769 break; 6770 case RTE_ETH_FILTER_SYN: 6771 ret = ixgbe_syn_filter_handle(dev, filter_op, arg); 6772 break; 6773 case RTE_ETH_FILTER_FDIR: 6774 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg); 6775 break; 6776 case RTE_ETH_FILTER_L2_TUNNEL: 6777 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg); 6778 break; 6779 case RTE_ETH_FILTER_GENERIC: 6780 if (filter_op != RTE_ETH_FILTER_GET) 6781 return -EINVAL; 6782 *(const void **)arg = &ixgbe_flow_ops; 6783 break; 6784 default: 6785 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported", 6786 filter_type); 6787 ret = -EINVAL; 6788 break; 6789 } 6790 6791 return ret; 6792 } 6793 6794 static u8 * 6795 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw, 6796 u8 **mc_addr_ptr, u32 *vmdq) 6797 { 6798 u8 *mc_addr; 6799 6800 *vmdq = 0; 6801 mc_addr = *mc_addr_ptr; 6802 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr)); 6803 return mc_addr; 6804 } 6805 6806 static int 6807 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 6808 struct ether_addr *mc_addr_set, 6809 uint32_t nb_mc_addr) 6810 { 6811 struct ixgbe_hw *hw; 6812 u8 *mc_addr_list; 6813 6814 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6815 mc_addr_list = (u8 *)mc_addr_set; 6816 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr, 6817 ixgbe_dev_addr_list_itr, TRUE); 6818 } 6819 6820 static uint64_t 6821 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev) 6822 { 6823 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6824 uint64_t systime_cycles; 6825 6826 switch (hw->mac.type) { 6827 case ixgbe_mac_X550: 6828 case ixgbe_mac_X550EM_x: 6829 case ixgbe_mac_X550EM_a: 6830 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */ 6831 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6832 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6833 * NSEC_PER_SEC; 6834 break; 6835 default: 6836 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 6837 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) 6838 << 32; 6839 } 6840 6841 return systime_cycles; 6842 } 6843 6844 static uint64_t 6845 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6846 { 6847 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6848 uint64_t rx_tstamp_cycles; 6849 6850 switch (hw->mac.type) { 6851 case ixgbe_mac_X550: 6852 case ixgbe_mac_X550EM_x: 6853 case ixgbe_mac_X550EM_a: 6854 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6855 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6856 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6857 * NSEC_PER_SEC; 6858 break; 6859 default: 6860 /* RXSTMPL stores ns and RXSTMPH stores seconds. */ 6861 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 6862 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) 6863 << 32; 6864 } 6865 6866 return rx_tstamp_cycles; 6867 } 6868 6869 static uint64_t 6870 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev) 6871 { 6872 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6873 uint64_t tx_tstamp_cycles; 6874 6875 switch (hw->mac.type) { 6876 case ixgbe_mac_X550: 6877 case ixgbe_mac_X550EM_x: 6878 case ixgbe_mac_X550EM_a: 6879 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6880 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6881 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6882 * NSEC_PER_SEC; 6883 break; 6884 default: 6885 /* TXSTMPL stores ns and TXSTMPH stores seconds. */ 6886 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 6887 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) 6888 << 32; 6889 } 6890 6891 return tx_tstamp_cycles; 6892 } 6893 6894 static void 6895 ixgbe_start_timecounters(struct rte_eth_dev *dev) 6896 { 6897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 6898 struct ixgbe_adapter *adapter = 6899 (struct ixgbe_adapter *)dev->data->dev_private; 6900 struct rte_eth_link link; 6901 uint32_t incval = 0; 6902 uint32_t shift = 0; 6903 6904 /* Get current link speed. */ 6905 ixgbe_dev_link_update(dev, 1); 6906 rte_eth_linkstatus_get(dev, &link); 6907 6908 switch (link.link_speed) { 6909 case ETH_SPEED_NUM_100M: 6910 incval = IXGBE_INCVAL_100; 6911 shift = IXGBE_INCVAL_SHIFT_100; 6912 break; 6913 case ETH_SPEED_NUM_1G: 6914 incval = IXGBE_INCVAL_1GB; 6915 shift = IXGBE_INCVAL_SHIFT_1GB; 6916 break; 6917 case ETH_SPEED_NUM_10G: 6918 default: 6919 incval = IXGBE_INCVAL_10GB; 6920 shift = IXGBE_INCVAL_SHIFT_10GB; 6921 break; 6922 } 6923 6924 switch (hw->mac.type) { 6925 case ixgbe_mac_X550: 6926 case ixgbe_mac_X550EM_x: 6927 case ixgbe_mac_X550EM_a: 6928 /* Independent of link speed. */ 6929 incval = 1; 6930 /* Cycles read will be interpreted as ns. */ 6931 shift = 0; 6932 /* Fall-through */ 6933 case ixgbe_mac_X540: 6934 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 6935 break; 6936 case ixgbe_mac_82599EB: 6937 incval >>= IXGBE_INCVAL_SHIFT_82599; 6938 shift -= IXGBE_INCVAL_SHIFT_82599; 6939 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 6940 (1 << IXGBE_INCPER_SHIFT_82599) | incval); 6941 break; 6942 default: 6943 /* Not supported. */ 6944 return; 6945 } 6946 6947 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter)); 6948 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6949 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 6950 6951 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6952 adapter->systime_tc.cc_shift = shift; 6953 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1; 6954 6955 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6956 adapter->rx_tstamp_tc.cc_shift = shift; 6957 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6958 6959 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK; 6960 adapter->tx_tstamp_tc.cc_shift = shift; 6961 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 6962 } 6963 6964 static int 6965 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 6966 { 6967 struct ixgbe_adapter *adapter = 6968 (struct ixgbe_adapter *)dev->data->dev_private; 6969 6970 adapter->systime_tc.nsec += delta; 6971 adapter->rx_tstamp_tc.nsec += delta; 6972 adapter->tx_tstamp_tc.nsec += delta; 6973 6974 return 0; 6975 } 6976 6977 static int 6978 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 6979 { 6980 uint64_t ns; 6981 struct ixgbe_adapter *adapter = 6982 (struct ixgbe_adapter *)dev->data->dev_private; 6983 6984 ns = rte_timespec_to_ns(ts); 6985 /* Set the timecounters to a new value. */ 6986 adapter->systime_tc.nsec = ns; 6987 adapter->rx_tstamp_tc.nsec = ns; 6988 adapter->tx_tstamp_tc.nsec = ns; 6989 6990 return 0; 6991 } 6992 6993 static int 6994 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 6995 { 6996 uint64_t ns, systime_cycles; 6997 struct ixgbe_adapter *adapter = 6998 (struct ixgbe_adapter *)dev->data->dev_private; 6999 7000 systime_cycles = ixgbe_read_systime_cyclecounter(dev); 7001 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles); 7002 *ts = rte_ns_to_timespec(ns); 7003 7004 return 0; 7005 } 7006 7007 static int 7008 ixgbe_timesync_enable(struct rte_eth_dev *dev) 7009 { 7010 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7011 uint32_t tsync_ctl; 7012 uint32_t tsauxc; 7013 7014 /* Stop the timesync system time. */ 7015 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0); 7016 /* Reset the timesync system time value. */ 7017 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0); 7018 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0); 7019 7020 /* Enable system time for platforms where it isn't on by default. */ 7021 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 7022 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME; 7023 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 7024 7025 ixgbe_start_timecounters(dev); 7026 7027 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7028 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 7029 (ETHER_TYPE_1588 | 7030 IXGBE_ETQF_FILTER_EN | 7031 IXGBE_ETQF_1588)); 7032 7033 /* Enable timestamping of received PTP packets. */ 7034 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7035 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED; 7036 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7037 7038 /* Enable timestamping of transmitted PTP packets. */ 7039 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7040 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED; 7041 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7042 7043 IXGBE_WRITE_FLUSH(hw); 7044 7045 return 0; 7046 } 7047 7048 static int 7049 ixgbe_timesync_disable(struct rte_eth_dev *dev) 7050 { 7051 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7052 uint32_t tsync_ctl; 7053 7054 /* Disable timestamping of transmitted PTP packets. */ 7055 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7056 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED; 7057 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl); 7058 7059 /* Disable timestamping of received PTP packets. */ 7060 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7061 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED; 7062 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl); 7063 7064 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */ 7065 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 7066 7067 /* Stop incrementating the System Time registers. */ 7068 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0); 7069 7070 return 0; 7071 } 7072 7073 static int 7074 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 7075 struct timespec *timestamp, 7076 uint32_t flags __rte_unused) 7077 { 7078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7079 struct ixgbe_adapter *adapter = 7080 (struct ixgbe_adapter *)dev->data->dev_private; 7081 uint32_t tsync_rxctl; 7082 uint64_t rx_tstamp_cycles; 7083 uint64_t ns; 7084 7085 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 7086 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0) 7087 return -EINVAL; 7088 7089 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev); 7090 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles); 7091 *timestamp = rte_ns_to_timespec(ns); 7092 7093 return 0; 7094 } 7095 7096 static int 7097 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 7098 struct timespec *timestamp) 7099 { 7100 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7101 struct ixgbe_adapter *adapter = 7102 (struct ixgbe_adapter *)dev->data->dev_private; 7103 uint32_t tsync_txctl; 7104 uint64_t tx_tstamp_cycles; 7105 uint64_t ns; 7106 7107 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 7108 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0) 7109 return -EINVAL; 7110 7111 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev); 7112 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles); 7113 *timestamp = rte_ns_to_timespec(ns); 7114 7115 return 0; 7116 } 7117 7118 static int 7119 ixgbe_get_reg_length(struct rte_eth_dev *dev) 7120 { 7121 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7122 int count = 0; 7123 int g_ind = 0; 7124 const struct reg_info *reg_group; 7125 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7126 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7127 7128 while ((reg_group = reg_set[g_ind++])) 7129 count += ixgbe_regs_group_count(reg_group); 7130 7131 return count; 7132 } 7133 7134 static int 7135 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused) 7136 { 7137 int count = 0; 7138 int g_ind = 0; 7139 const struct reg_info *reg_group; 7140 7141 while ((reg_group = ixgbevf_regs[g_ind++])) 7142 count += ixgbe_regs_group_count(reg_group); 7143 7144 return count; 7145 } 7146 7147 static int 7148 ixgbe_get_regs(struct rte_eth_dev *dev, 7149 struct rte_dev_reg_info *regs) 7150 { 7151 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7152 uint32_t *data = regs->data; 7153 int g_ind = 0; 7154 int count = 0; 7155 const struct reg_info *reg_group; 7156 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ? 7157 ixgbe_regs_mac_82598EB : ixgbe_regs_others; 7158 7159 if (data == NULL) { 7160 regs->length = ixgbe_get_reg_length(dev); 7161 regs->width = sizeof(uint32_t); 7162 return 0; 7163 } 7164 7165 /* Support only full register dump */ 7166 if ((regs->length == 0) || 7167 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) { 7168 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7169 hw->device_id; 7170 while ((reg_group = reg_set[g_ind++])) 7171 count += ixgbe_read_regs_group(dev, &data[count], 7172 reg_group); 7173 return 0; 7174 } 7175 7176 return -ENOTSUP; 7177 } 7178 7179 static int 7180 ixgbevf_get_regs(struct rte_eth_dev *dev, 7181 struct rte_dev_reg_info *regs) 7182 { 7183 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7184 uint32_t *data = regs->data; 7185 int g_ind = 0; 7186 int count = 0; 7187 const struct reg_info *reg_group; 7188 7189 if (data == NULL) { 7190 regs->length = ixgbevf_get_reg_length(dev); 7191 regs->width = sizeof(uint32_t); 7192 return 0; 7193 } 7194 7195 /* Support only full register dump */ 7196 if ((regs->length == 0) || 7197 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) { 7198 regs->version = hw->mac.type << 24 | hw->revision_id << 16 | 7199 hw->device_id; 7200 while ((reg_group = ixgbevf_regs[g_ind++])) 7201 count += ixgbe_read_regs_group(dev, &data[count], 7202 reg_group); 7203 return 0; 7204 } 7205 7206 return -ENOTSUP; 7207 } 7208 7209 static int 7210 ixgbe_get_eeprom_length(struct rte_eth_dev *dev) 7211 { 7212 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7213 7214 /* Return unit is byte count */ 7215 return hw->eeprom.word_size * 2; 7216 } 7217 7218 static int 7219 ixgbe_get_eeprom(struct rte_eth_dev *dev, 7220 struct rte_dev_eeprom_info *in_eeprom) 7221 { 7222 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7223 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7224 uint16_t *data = in_eeprom->data; 7225 int first, length; 7226 7227 first = in_eeprom->offset >> 1; 7228 length = in_eeprom->length >> 1; 7229 if ((first > hw->eeprom.word_size) || 7230 ((first + length) > hw->eeprom.word_size)) 7231 return -EINVAL; 7232 7233 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7234 7235 return eeprom->ops.read_buffer(hw, first, length, data); 7236 } 7237 7238 static int 7239 ixgbe_set_eeprom(struct rte_eth_dev *dev, 7240 struct rte_dev_eeprom_info *in_eeprom) 7241 { 7242 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7243 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 7244 uint16_t *data = in_eeprom->data; 7245 int first, length; 7246 7247 first = in_eeprom->offset >> 1; 7248 length = in_eeprom->length >> 1; 7249 if ((first > hw->eeprom.word_size) || 7250 ((first + length) > hw->eeprom.word_size)) 7251 return -EINVAL; 7252 7253 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16); 7254 7255 return eeprom->ops.write_buffer(hw, first, length, data); 7256 } 7257 7258 static int 7259 ixgbe_get_module_info(struct rte_eth_dev *dev, 7260 struct rte_eth_dev_module_info *modinfo) 7261 { 7262 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7263 uint32_t status; 7264 uint8_t sff8472_rev, addr_mode; 7265 bool page_swap = false; 7266 7267 /* Check whether we support SFF-8472 or not */ 7268 status = hw->phy.ops.read_i2c_eeprom(hw, 7269 IXGBE_SFF_SFF_8472_COMP, 7270 &sff8472_rev); 7271 if (status != 0) 7272 return -EIO; 7273 7274 /* addressing mode is not supported */ 7275 status = hw->phy.ops.read_i2c_eeprom(hw, 7276 IXGBE_SFF_SFF_8472_SWAP, 7277 &addr_mode); 7278 if (status != 0) 7279 return -EIO; 7280 7281 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) { 7282 PMD_DRV_LOG(ERR, 7283 "Address change required to access page 0xA2, " 7284 "but not supported. Please report the module " 7285 "type to the driver maintainers."); 7286 page_swap = true; 7287 } 7288 7289 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) { 7290 /* We have a SFP, but it does not support SFF-8472 */ 7291 modinfo->type = RTE_ETH_MODULE_SFF_8079; 7292 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN; 7293 } else { 7294 /* We have a SFP which supports a revision of SFF-8472. */ 7295 modinfo->type = RTE_ETH_MODULE_SFF_8472; 7296 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 7297 } 7298 7299 return 0; 7300 } 7301 7302 static int 7303 ixgbe_get_module_eeprom(struct rte_eth_dev *dev, 7304 struct rte_dev_eeprom_info *info) 7305 { 7306 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7307 uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID; 7308 uint8_t databyte = 0xFF; 7309 uint8_t *data = info->data; 7310 uint32_t i = 0; 7311 7312 if (info->length == 0) 7313 return -EINVAL; 7314 7315 for (i = info->offset; i < info->offset + info->length; i++) { 7316 if (i < RTE_ETH_MODULE_SFF_8079_LEN) 7317 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte); 7318 else 7319 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte); 7320 7321 if (status != 0) 7322 return -EIO; 7323 7324 data[i - info->offset] = databyte; 7325 } 7326 7327 return 0; 7328 } 7329 7330 uint16_t 7331 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) { 7332 switch (mac_type) { 7333 case ixgbe_mac_X550: 7334 case ixgbe_mac_X550EM_x: 7335 case ixgbe_mac_X550EM_a: 7336 return ETH_RSS_RETA_SIZE_512; 7337 case ixgbe_mac_X550_vf: 7338 case ixgbe_mac_X550EM_x_vf: 7339 case ixgbe_mac_X550EM_a_vf: 7340 return ETH_RSS_RETA_SIZE_64; 7341 default: 7342 return ETH_RSS_RETA_SIZE_128; 7343 } 7344 } 7345 7346 uint32_t 7347 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) { 7348 switch (mac_type) { 7349 case ixgbe_mac_X550: 7350 case ixgbe_mac_X550EM_x: 7351 case ixgbe_mac_X550EM_a: 7352 if (reta_idx < ETH_RSS_RETA_SIZE_128) 7353 return IXGBE_RETA(reta_idx >> 2); 7354 else 7355 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2); 7356 case ixgbe_mac_X550_vf: 7357 case ixgbe_mac_X550EM_x_vf: 7358 case ixgbe_mac_X550EM_a_vf: 7359 return IXGBE_VFRETA(reta_idx >> 2); 7360 default: 7361 return IXGBE_RETA(reta_idx >> 2); 7362 } 7363 } 7364 7365 uint32_t 7366 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) { 7367 switch (mac_type) { 7368 case ixgbe_mac_X550_vf: 7369 case ixgbe_mac_X550EM_x_vf: 7370 case ixgbe_mac_X550EM_a_vf: 7371 return IXGBE_VFMRQC; 7372 default: 7373 return IXGBE_MRQC; 7374 } 7375 } 7376 7377 uint32_t 7378 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) { 7379 switch (mac_type) { 7380 case ixgbe_mac_X550_vf: 7381 case ixgbe_mac_X550EM_x_vf: 7382 case ixgbe_mac_X550EM_a_vf: 7383 return IXGBE_VFRSSRK(i); 7384 default: 7385 return IXGBE_RSSRK(i); 7386 } 7387 } 7388 7389 bool 7390 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) { 7391 switch (mac_type) { 7392 case ixgbe_mac_82599_vf: 7393 case ixgbe_mac_X540_vf: 7394 return 0; 7395 default: 7396 return 1; 7397 } 7398 } 7399 7400 static int 7401 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev, 7402 struct rte_eth_dcb_info *dcb_info) 7403 { 7404 struct ixgbe_dcb_config *dcb_config = 7405 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private); 7406 struct ixgbe_dcb_tc_config *tc; 7407 struct rte_eth_dcb_tc_queue_mapping *tc_queue; 7408 uint8_t nb_tcs; 7409 uint8_t i, j; 7410 7411 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG) 7412 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs; 7413 else 7414 dcb_info->nb_tcs = 1; 7415 7416 tc_queue = &dcb_info->tc_queue; 7417 nb_tcs = dcb_info->nb_tcs; 7418 7419 if (dcb_config->vt_mode) { /* vt is enabled*/ 7420 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf = 7421 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf; 7422 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7423 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i]; 7424 if (RTE_ETH_DEV_SRIOV(dev).active > 0) { 7425 for (j = 0; j < nb_tcs; j++) { 7426 tc_queue->tc_rxq[0][j].base = j; 7427 tc_queue->tc_rxq[0][j].nb_queue = 1; 7428 tc_queue->tc_txq[0][j].base = j; 7429 tc_queue->tc_txq[0][j].nb_queue = 1; 7430 } 7431 } else { 7432 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) { 7433 for (j = 0; j < nb_tcs; j++) { 7434 tc_queue->tc_rxq[i][j].base = 7435 i * nb_tcs + j; 7436 tc_queue->tc_rxq[i][j].nb_queue = 1; 7437 tc_queue->tc_txq[i][j].base = 7438 i * nb_tcs + j; 7439 tc_queue->tc_txq[i][j].nb_queue = 1; 7440 } 7441 } 7442 } 7443 } else { /* vt is disabled*/ 7444 struct rte_eth_dcb_rx_conf *rx_conf = 7445 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf; 7446 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) 7447 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i]; 7448 if (dcb_info->nb_tcs == ETH_4_TCS) { 7449 for (i = 0; i < dcb_info->nb_tcs; i++) { 7450 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32; 7451 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7452 } 7453 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7454 dcb_info->tc_queue.tc_txq[0][1].base = 64; 7455 dcb_info->tc_queue.tc_txq[0][2].base = 96; 7456 dcb_info->tc_queue.tc_txq[0][3].base = 112; 7457 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64; 7458 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7459 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7460 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7461 } else if (dcb_info->nb_tcs == ETH_8_TCS) { 7462 for (i = 0; i < dcb_info->nb_tcs; i++) { 7463 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16; 7464 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16; 7465 } 7466 dcb_info->tc_queue.tc_txq[0][0].base = 0; 7467 dcb_info->tc_queue.tc_txq[0][1].base = 32; 7468 dcb_info->tc_queue.tc_txq[0][2].base = 64; 7469 dcb_info->tc_queue.tc_txq[0][3].base = 80; 7470 dcb_info->tc_queue.tc_txq[0][4].base = 96; 7471 dcb_info->tc_queue.tc_txq[0][5].base = 104; 7472 dcb_info->tc_queue.tc_txq[0][6].base = 112; 7473 dcb_info->tc_queue.tc_txq[0][7].base = 120; 7474 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32; 7475 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32; 7476 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16; 7477 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16; 7478 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8; 7479 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8; 7480 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8; 7481 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8; 7482 } 7483 } 7484 for (i = 0; i < dcb_info->nb_tcs; i++) { 7485 tc = &dcb_config->tc_config[i]; 7486 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent; 7487 } 7488 return 0; 7489 } 7490 7491 /* Update e-tag ether type */ 7492 static int 7493 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw, 7494 uint16_t ether_type) 7495 { 7496 uint32_t etag_etype; 7497 7498 if (hw->mac.type != ixgbe_mac_X550 && 7499 hw->mac.type != ixgbe_mac_X550EM_x && 7500 hw->mac.type != ixgbe_mac_X550EM_a) { 7501 return -ENOTSUP; 7502 } 7503 7504 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7505 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK; 7506 etag_etype |= ether_type; 7507 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7508 IXGBE_WRITE_FLUSH(hw); 7509 7510 return 0; 7511 } 7512 7513 /* Config l2 tunnel ether type */ 7514 static int 7515 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev, 7516 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7517 { 7518 int ret = 0; 7519 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7520 struct ixgbe_l2_tn_info *l2_tn_info = 7521 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7522 7523 if (l2_tunnel == NULL) 7524 return -EINVAL; 7525 7526 switch (l2_tunnel->l2_tunnel_type) { 7527 case RTE_L2_TUNNEL_TYPE_E_TAG: 7528 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type; 7529 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type); 7530 break; 7531 default: 7532 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7533 ret = -EINVAL; 7534 break; 7535 } 7536 7537 return ret; 7538 } 7539 7540 /* Enable e-tag tunnel */ 7541 static int 7542 ixgbe_e_tag_enable(struct ixgbe_hw *hw) 7543 { 7544 uint32_t etag_etype; 7545 7546 if (hw->mac.type != ixgbe_mac_X550 && 7547 hw->mac.type != ixgbe_mac_X550EM_x && 7548 hw->mac.type != ixgbe_mac_X550EM_a) { 7549 return -ENOTSUP; 7550 } 7551 7552 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7553 etag_etype |= IXGBE_ETAG_ETYPE_VALID; 7554 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7555 IXGBE_WRITE_FLUSH(hw); 7556 7557 return 0; 7558 } 7559 7560 /* Enable l2 tunnel */ 7561 static int 7562 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev, 7563 enum rte_eth_tunnel_type l2_tunnel_type) 7564 { 7565 int ret = 0; 7566 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7567 struct ixgbe_l2_tn_info *l2_tn_info = 7568 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7569 7570 switch (l2_tunnel_type) { 7571 case RTE_L2_TUNNEL_TYPE_E_TAG: 7572 l2_tn_info->e_tag_en = TRUE; 7573 ret = ixgbe_e_tag_enable(hw); 7574 break; 7575 default: 7576 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7577 ret = -EINVAL; 7578 break; 7579 } 7580 7581 return ret; 7582 } 7583 7584 /* Disable e-tag tunnel */ 7585 static int 7586 ixgbe_e_tag_disable(struct ixgbe_hw *hw) 7587 { 7588 uint32_t etag_etype; 7589 7590 if (hw->mac.type != ixgbe_mac_X550 && 7591 hw->mac.type != ixgbe_mac_X550EM_x && 7592 hw->mac.type != ixgbe_mac_X550EM_a) { 7593 return -ENOTSUP; 7594 } 7595 7596 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE); 7597 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID; 7598 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype); 7599 IXGBE_WRITE_FLUSH(hw); 7600 7601 return 0; 7602 } 7603 7604 /* Disable l2 tunnel */ 7605 static int 7606 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev, 7607 enum rte_eth_tunnel_type l2_tunnel_type) 7608 { 7609 int ret = 0; 7610 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7611 struct ixgbe_l2_tn_info *l2_tn_info = 7612 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7613 7614 switch (l2_tunnel_type) { 7615 case RTE_L2_TUNNEL_TYPE_E_TAG: 7616 l2_tn_info->e_tag_en = FALSE; 7617 ret = ixgbe_e_tag_disable(hw); 7618 break; 7619 default: 7620 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7621 ret = -EINVAL; 7622 break; 7623 } 7624 7625 return ret; 7626 } 7627 7628 static int 7629 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev, 7630 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7631 { 7632 int ret = 0; 7633 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7634 uint32_t i, rar_entries; 7635 uint32_t rar_low, rar_high; 7636 7637 if (hw->mac.type != ixgbe_mac_X550 && 7638 hw->mac.type != ixgbe_mac_X550EM_x && 7639 hw->mac.type != ixgbe_mac_X550EM_a) { 7640 return -ENOTSUP; 7641 } 7642 7643 rar_entries = ixgbe_get_num_rx_addrs(hw); 7644 7645 for (i = 1; i < rar_entries; i++) { 7646 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7647 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i)); 7648 if ((rar_high & IXGBE_RAH_AV) && 7649 (rar_high & IXGBE_RAH_ADTYPE) && 7650 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) == 7651 l2_tunnel->tunnel_id)) { 7652 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 7653 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 7654 7655 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL); 7656 7657 return ret; 7658 } 7659 } 7660 7661 return ret; 7662 } 7663 7664 static int 7665 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev, 7666 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7667 { 7668 int ret = 0; 7669 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7670 uint32_t i, rar_entries; 7671 uint32_t rar_low, rar_high; 7672 7673 if (hw->mac.type != ixgbe_mac_X550 && 7674 hw->mac.type != ixgbe_mac_X550EM_x && 7675 hw->mac.type != ixgbe_mac_X550EM_a) { 7676 return -ENOTSUP; 7677 } 7678 7679 /* One entry for one tunnel. Try to remove potential existing entry. */ 7680 ixgbe_e_tag_filter_del(dev, l2_tunnel); 7681 7682 rar_entries = ixgbe_get_num_rx_addrs(hw); 7683 7684 for (i = 1; i < rar_entries; i++) { 7685 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i)); 7686 if (rar_high & IXGBE_RAH_AV) { 7687 continue; 7688 } else { 7689 ixgbe_set_vmdq(hw, i, l2_tunnel->pool); 7690 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE; 7691 rar_low = l2_tunnel->tunnel_id; 7692 7693 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low); 7694 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high); 7695 7696 return ret; 7697 } 7698 } 7699 7700 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full." 7701 " Please remove a rule before adding a new one."); 7702 return -EINVAL; 7703 } 7704 7705 static inline struct ixgbe_l2_tn_filter * 7706 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info, 7707 struct ixgbe_l2_tn_key *key) 7708 { 7709 int ret; 7710 7711 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key); 7712 if (ret < 0) 7713 return NULL; 7714 7715 return l2_tn_info->hash_map[ret]; 7716 } 7717 7718 static inline int 7719 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7720 struct ixgbe_l2_tn_filter *l2_tn_filter) 7721 { 7722 int ret; 7723 7724 ret = rte_hash_add_key(l2_tn_info->hash_handle, 7725 &l2_tn_filter->key); 7726 7727 if (ret < 0) { 7728 PMD_DRV_LOG(ERR, 7729 "Failed to insert L2 tunnel filter" 7730 " to hash table %d!", 7731 ret); 7732 return ret; 7733 } 7734 7735 l2_tn_info->hash_map[ret] = l2_tn_filter; 7736 7737 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7738 7739 return 0; 7740 } 7741 7742 static inline int 7743 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info, 7744 struct ixgbe_l2_tn_key *key) 7745 { 7746 int ret; 7747 struct ixgbe_l2_tn_filter *l2_tn_filter; 7748 7749 ret = rte_hash_del_key(l2_tn_info->hash_handle, key); 7750 7751 if (ret < 0) { 7752 PMD_DRV_LOG(ERR, 7753 "No such L2 tunnel filter to delete %d!", 7754 ret); 7755 return ret; 7756 } 7757 7758 l2_tn_filter = l2_tn_info->hash_map[ret]; 7759 l2_tn_info->hash_map[ret] = NULL; 7760 7761 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries); 7762 rte_free(l2_tn_filter); 7763 7764 return 0; 7765 } 7766 7767 /* Add l2 tunnel filter */ 7768 int 7769 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev, 7770 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7771 bool restore) 7772 { 7773 int ret; 7774 struct ixgbe_l2_tn_info *l2_tn_info = 7775 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7776 struct ixgbe_l2_tn_key key; 7777 struct ixgbe_l2_tn_filter *node; 7778 7779 if (!restore) { 7780 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7781 key.tn_id = l2_tunnel->tunnel_id; 7782 7783 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key); 7784 7785 if (node) { 7786 PMD_DRV_LOG(ERR, 7787 "The L2 tunnel filter already exists!"); 7788 return -EINVAL; 7789 } 7790 7791 node = rte_zmalloc("ixgbe_l2_tn", 7792 sizeof(struct ixgbe_l2_tn_filter), 7793 0); 7794 if (!node) 7795 return -ENOMEM; 7796 7797 rte_memcpy(&node->key, 7798 &key, 7799 sizeof(struct ixgbe_l2_tn_key)); 7800 node->pool = l2_tunnel->pool; 7801 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node); 7802 if (ret < 0) { 7803 rte_free(node); 7804 return ret; 7805 } 7806 } 7807 7808 switch (l2_tunnel->l2_tunnel_type) { 7809 case RTE_L2_TUNNEL_TYPE_E_TAG: 7810 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel); 7811 break; 7812 default: 7813 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7814 ret = -EINVAL; 7815 break; 7816 } 7817 7818 if ((!restore) && (ret < 0)) 7819 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7820 7821 return ret; 7822 } 7823 7824 /* Delete l2 tunnel filter */ 7825 int 7826 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev, 7827 struct rte_eth_l2_tunnel_conf *l2_tunnel) 7828 { 7829 int ret; 7830 struct ixgbe_l2_tn_info *l2_tn_info = 7831 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7832 struct ixgbe_l2_tn_key key; 7833 7834 key.l2_tn_type = l2_tunnel->l2_tunnel_type; 7835 key.tn_id = l2_tunnel->tunnel_id; 7836 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key); 7837 if (ret < 0) 7838 return ret; 7839 7840 switch (l2_tunnel->l2_tunnel_type) { 7841 case RTE_L2_TUNNEL_TYPE_E_TAG: 7842 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel); 7843 break; 7844 default: 7845 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7846 ret = -EINVAL; 7847 break; 7848 } 7849 7850 return ret; 7851 } 7852 7853 /** 7854 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter. 7855 * @dev: pointer to rte_eth_dev structure 7856 * @filter_op:operation will be taken. 7857 * @arg: a pointer to specific structure corresponding to the filter_op 7858 */ 7859 static int 7860 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev, 7861 enum rte_filter_op filter_op, 7862 void *arg) 7863 { 7864 int ret; 7865 7866 if (filter_op == RTE_ETH_FILTER_NOP) 7867 return 0; 7868 7869 if (arg == NULL) { 7870 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 7871 filter_op); 7872 return -EINVAL; 7873 } 7874 7875 switch (filter_op) { 7876 case RTE_ETH_FILTER_ADD: 7877 ret = ixgbe_dev_l2_tunnel_filter_add 7878 (dev, 7879 (struct rte_eth_l2_tunnel_conf *)arg, 7880 FALSE); 7881 break; 7882 case RTE_ETH_FILTER_DELETE: 7883 ret = ixgbe_dev_l2_tunnel_filter_del 7884 (dev, 7885 (struct rte_eth_l2_tunnel_conf *)arg); 7886 break; 7887 default: 7888 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 7889 ret = -EINVAL; 7890 break; 7891 } 7892 return ret; 7893 } 7894 7895 static int 7896 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en) 7897 { 7898 int ret = 0; 7899 uint32_t ctrl; 7900 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7901 7902 if (hw->mac.type != ixgbe_mac_X550 && 7903 hw->mac.type != ixgbe_mac_X550EM_x && 7904 hw->mac.type != ixgbe_mac_X550EM_a) { 7905 return -ENOTSUP; 7906 } 7907 7908 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 7909 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK; 7910 if (en) 7911 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG; 7912 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl); 7913 7914 return ret; 7915 } 7916 7917 /* Enable l2 tunnel forwarding */ 7918 static int 7919 ixgbe_dev_l2_tunnel_forwarding_enable 7920 (struct rte_eth_dev *dev, 7921 enum rte_eth_tunnel_type l2_tunnel_type) 7922 { 7923 struct ixgbe_l2_tn_info *l2_tn_info = 7924 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7925 int ret = 0; 7926 7927 switch (l2_tunnel_type) { 7928 case RTE_L2_TUNNEL_TYPE_E_TAG: 7929 l2_tn_info->e_tag_fwd_en = TRUE; 7930 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1); 7931 break; 7932 default: 7933 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7934 ret = -EINVAL; 7935 break; 7936 } 7937 7938 return ret; 7939 } 7940 7941 /* Disable l2 tunnel forwarding */ 7942 static int 7943 ixgbe_dev_l2_tunnel_forwarding_disable 7944 (struct rte_eth_dev *dev, 7945 enum rte_eth_tunnel_type l2_tunnel_type) 7946 { 7947 struct ixgbe_l2_tn_info *l2_tn_info = 7948 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 7949 int ret = 0; 7950 7951 switch (l2_tunnel_type) { 7952 case RTE_L2_TUNNEL_TYPE_E_TAG: 7953 l2_tn_info->e_tag_fwd_en = FALSE; 7954 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0); 7955 break; 7956 default: 7957 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 7958 ret = -EINVAL; 7959 break; 7960 } 7961 7962 return ret; 7963 } 7964 7965 static int 7966 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev, 7967 struct rte_eth_l2_tunnel_conf *l2_tunnel, 7968 bool en) 7969 { 7970 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 7971 int ret = 0; 7972 uint32_t vmtir, vmvir; 7973 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 7974 7975 if (l2_tunnel->vf_id >= pci_dev->max_vfs) { 7976 PMD_DRV_LOG(ERR, 7977 "VF id %u should be less than %u", 7978 l2_tunnel->vf_id, 7979 pci_dev->max_vfs); 7980 return -EINVAL; 7981 } 7982 7983 if (hw->mac.type != ixgbe_mac_X550 && 7984 hw->mac.type != ixgbe_mac_X550EM_x && 7985 hw->mac.type != ixgbe_mac_X550EM_a) { 7986 return -ENOTSUP; 7987 } 7988 7989 if (en) 7990 vmtir = l2_tunnel->tunnel_id; 7991 else 7992 vmtir = 0; 7993 7994 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir); 7995 7996 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id)); 7997 vmvir &= ~IXGBE_VMVIR_TAGA_MASK; 7998 if (en) 7999 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT; 8000 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir); 8001 8002 return ret; 8003 } 8004 8005 /* Enable l2 tunnel tag insertion */ 8006 static int 8007 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev, 8008 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8009 { 8010 int ret = 0; 8011 8012 switch (l2_tunnel->l2_tunnel_type) { 8013 case RTE_L2_TUNNEL_TYPE_E_TAG: 8014 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1); 8015 break; 8016 default: 8017 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8018 ret = -EINVAL; 8019 break; 8020 } 8021 8022 return ret; 8023 } 8024 8025 /* Disable l2 tunnel tag insertion */ 8026 static int 8027 ixgbe_dev_l2_tunnel_insertion_disable 8028 (struct rte_eth_dev *dev, 8029 struct rte_eth_l2_tunnel_conf *l2_tunnel) 8030 { 8031 int ret = 0; 8032 8033 switch (l2_tunnel->l2_tunnel_type) { 8034 case RTE_L2_TUNNEL_TYPE_E_TAG: 8035 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0); 8036 break; 8037 default: 8038 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8039 ret = -EINVAL; 8040 break; 8041 } 8042 8043 return ret; 8044 } 8045 8046 static int 8047 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev, 8048 bool en) 8049 { 8050 int ret = 0; 8051 uint32_t qde; 8052 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8053 8054 if (hw->mac.type != ixgbe_mac_X550 && 8055 hw->mac.type != ixgbe_mac_X550EM_x && 8056 hw->mac.type != ixgbe_mac_X550EM_a) { 8057 return -ENOTSUP; 8058 } 8059 8060 qde = IXGBE_READ_REG(hw, IXGBE_QDE); 8061 if (en) 8062 qde |= IXGBE_QDE_STRIP_TAG; 8063 else 8064 qde &= ~IXGBE_QDE_STRIP_TAG; 8065 qde &= ~IXGBE_QDE_READ; 8066 qde |= IXGBE_QDE_WRITE; 8067 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde); 8068 8069 return ret; 8070 } 8071 8072 /* Enable l2 tunnel tag stripping */ 8073 static int 8074 ixgbe_dev_l2_tunnel_stripping_enable 8075 (struct rte_eth_dev *dev, 8076 enum rte_eth_tunnel_type l2_tunnel_type) 8077 { 8078 int ret = 0; 8079 8080 switch (l2_tunnel_type) { 8081 case RTE_L2_TUNNEL_TYPE_E_TAG: 8082 ret = ixgbe_e_tag_stripping_en_dis(dev, 1); 8083 break; 8084 default: 8085 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8086 ret = -EINVAL; 8087 break; 8088 } 8089 8090 return ret; 8091 } 8092 8093 /* Disable l2 tunnel tag stripping */ 8094 static int 8095 ixgbe_dev_l2_tunnel_stripping_disable 8096 (struct rte_eth_dev *dev, 8097 enum rte_eth_tunnel_type l2_tunnel_type) 8098 { 8099 int ret = 0; 8100 8101 switch (l2_tunnel_type) { 8102 case RTE_L2_TUNNEL_TYPE_E_TAG: 8103 ret = ixgbe_e_tag_stripping_en_dis(dev, 0); 8104 break; 8105 default: 8106 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8107 ret = -EINVAL; 8108 break; 8109 } 8110 8111 return ret; 8112 } 8113 8114 /* Enable/disable l2 tunnel offload functions */ 8115 static int 8116 ixgbe_dev_l2_tunnel_offload_set 8117 (struct rte_eth_dev *dev, 8118 struct rte_eth_l2_tunnel_conf *l2_tunnel, 8119 uint32_t mask, 8120 uint8_t en) 8121 { 8122 int ret = 0; 8123 8124 if (l2_tunnel == NULL) 8125 return -EINVAL; 8126 8127 ret = -EINVAL; 8128 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) { 8129 if (en) 8130 ret = ixgbe_dev_l2_tunnel_enable( 8131 dev, 8132 l2_tunnel->l2_tunnel_type); 8133 else 8134 ret = ixgbe_dev_l2_tunnel_disable( 8135 dev, 8136 l2_tunnel->l2_tunnel_type); 8137 } 8138 8139 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) { 8140 if (en) 8141 ret = ixgbe_dev_l2_tunnel_insertion_enable( 8142 dev, 8143 l2_tunnel); 8144 else 8145 ret = ixgbe_dev_l2_tunnel_insertion_disable( 8146 dev, 8147 l2_tunnel); 8148 } 8149 8150 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) { 8151 if (en) 8152 ret = ixgbe_dev_l2_tunnel_stripping_enable( 8153 dev, 8154 l2_tunnel->l2_tunnel_type); 8155 else 8156 ret = ixgbe_dev_l2_tunnel_stripping_disable( 8157 dev, 8158 l2_tunnel->l2_tunnel_type); 8159 } 8160 8161 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) { 8162 if (en) 8163 ret = ixgbe_dev_l2_tunnel_forwarding_enable( 8164 dev, 8165 l2_tunnel->l2_tunnel_type); 8166 else 8167 ret = ixgbe_dev_l2_tunnel_forwarding_disable( 8168 dev, 8169 l2_tunnel->l2_tunnel_type); 8170 } 8171 8172 return ret; 8173 } 8174 8175 static int 8176 ixgbe_update_vxlan_port(struct ixgbe_hw *hw, 8177 uint16_t port) 8178 { 8179 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port); 8180 IXGBE_WRITE_FLUSH(hw); 8181 8182 return 0; 8183 } 8184 8185 /* There's only one register for VxLAN UDP port. 8186 * So, we cannot add several ports. Will update it. 8187 */ 8188 static int 8189 ixgbe_add_vxlan_port(struct ixgbe_hw *hw, 8190 uint16_t port) 8191 { 8192 if (port == 0) { 8193 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed."); 8194 return -EINVAL; 8195 } 8196 8197 return ixgbe_update_vxlan_port(hw, port); 8198 } 8199 8200 /* We cannot delete the VxLAN port. For there's a register for VxLAN 8201 * UDP port, it must have a value. 8202 * So, will reset it to the original value 0. 8203 */ 8204 static int 8205 ixgbe_del_vxlan_port(struct ixgbe_hw *hw, 8206 uint16_t port) 8207 { 8208 uint16_t cur_port; 8209 8210 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL); 8211 8212 if (cur_port != port) { 8213 PMD_DRV_LOG(ERR, "Port %u does not exist.", port); 8214 return -EINVAL; 8215 } 8216 8217 return ixgbe_update_vxlan_port(hw, 0); 8218 } 8219 8220 /* Add UDP tunneling port */ 8221 static int 8222 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev, 8223 struct rte_eth_udp_tunnel *udp_tunnel) 8224 { 8225 int ret = 0; 8226 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8227 8228 if (hw->mac.type != ixgbe_mac_X550 && 8229 hw->mac.type != ixgbe_mac_X550EM_x && 8230 hw->mac.type != ixgbe_mac_X550EM_a) { 8231 return -ENOTSUP; 8232 } 8233 8234 if (udp_tunnel == NULL) 8235 return -EINVAL; 8236 8237 switch (udp_tunnel->prot_type) { 8238 case RTE_TUNNEL_TYPE_VXLAN: 8239 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port); 8240 break; 8241 8242 case RTE_TUNNEL_TYPE_GENEVE: 8243 case RTE_TUNNEL_TYPE_TEREDO: 8244 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8245 ret = -EINVAL; 8246 break; 8247 8248 default: 8249 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8250 ret = -EINVAL; 8251 break; 8252 } 8253 8254 return ret; 8255 } 8256 8257 /* Remove UDP tunneling port */ 8258 static int 8259 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev, 8260 struct rte_eth_udp_tunnel *udp_tunnel) 8261 { 8262 int ret = 0; 8263 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8264 8265 if (hw->mac.type != ixgbe_mac_X550 && 8266 hw->mac.type != ixgbe_mac_X550EM_x && 8267 hw->mac.type != ixgbe_mac_X550EM_a) { 8268 return -ENOTSUP; 8269 } 8270 8271 if (udp_tunnel == NULL) 8272 return -EINVAL; 8273 8274 switch (udp_tunnel->prot_type) { 8275 case RTE_TUNNEL_TYPE_VXLAN: 8276 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port); 8277 break; 8278 case RTE_TUNNEL_TYPE_GENEVE: 8279 case RTE_TUNNEL_TYPE_TEREDO: 8280 PMD_DRV_LOG(ERR, "Tunnel type is not supported now."); 8281 ret = -EINVAL; 8282 break; 8283 default: 8284 PMD_DRV_LOG(ERR, "Invalid tunnel type"); 8285 ret = -EINVAL; 8286 break; 8287 } 8288 8289 return ret; 8290 } 8291 8292 static void 8293 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev) 8294 { 8295 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8296 8297 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI); 8298 } 8299 8300 static void 8301 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev) 8302 { 8303 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8304 8305 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI); 8306 } 8307 8308 static void ixgbevf_mbx_process(struct rte_eth_dev *dev) 8309 { 8310 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8311 u32 in_msg = 0; 8312 8313 /* peek the message first */ 8314 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM); 8315 8316 /* PF reset VF event */ 8317 if (in_msg == IXGBE_PF_CONTROL_MSG) { 8318 /* dummy mbx read to ack pf */ 8319 if (ixgbe_read_mbx(hw, &in_msg, 1, 0)) 8320 return; 8321 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 8322 NULL); 8323 } 8324 } 8325 8326 static int 8327 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev) 8328 { 8329 uint32_t eicr; 8330 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8331 struct ixgbe_interrupt *intr = 8332 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8333 ixgbevf_intr_disable(dev); 8334 8335 /* read-on-clear nic registers here */ 8336 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); 8337 intr->flags = 0; 8338 8339 /* only one misc vector supported - mailbox */ 8340 eicr &= IXGBE_VTEICR_MASK; 8341 if (eicr == IXGBE_MISC_VEC_ID) 8342 intr->flags |= IXGBE_FLAG_MAILBOX; 8343 8344 return 0; 8345 } 8346 8347 static int 8348 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) 8349 { 8350 struct ixgbe_interrupt *intr = 8351 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); 8352 8353 if (intr->flags & IXGBE_FLAG_MAILBOX) { 8354 ixgbevf_mbx_process(dev); 8355 intr->flags &= ~IXGBE_FLAG_MAILBOX; 8356 } 8357 8358 ixgbevf_intr_enable(dev); 8359 8360 return 0; 8361 } 8362 8363 static void 8364 ixgbevf_dev_interrupt_handler(void *param) 8365 { 8366 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 8367 8368 ixgbevf_dev_interrupt_get_status(dev); 8369 ixgbevf_dev_interrupt_action(dev); 8370 } 8371 8372 /** 8373 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path 8374 * @hw: pointer to hardware structure 8375 * 8376 * Stops the transmit data path and waits for the HW to internally empty 8377 * the Tx security block 8378 **/ 8379 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw) 8380 { 8381 #define IXGBE_MAX_SECTX_POLL 40 8382 8383 int i; 8384 int sectxreg; 8385 8386 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8387 sectxreg |= IXGBE_SECTXCTRL_TX_DIS; 8388 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8389 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) { 8390 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT); 8391 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY) 8392 break; 8393 /* Use interrupt-safe sleep just in case */ 8394 usec_delay(1000); 8395 } 8396 8397 /* For informational purposes only */ 8398 if (i >= IXGBE_MAX_SECTX_POLL) 8399 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security " 8400 "path fully disabled. Continuing with init."); 8401 8402 return IXGBE_SUCCESS; 8403 } 8404 8405 /** 8406 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path 8407 * @hw: pointer to hardware structure 8408 * 8409 * Enables the transmit data path. 8410 **/ 8411 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw) 8412 { 8413 uint32_t sectxreg; 8414 8415 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); 8416 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS; 8417 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg); 8418 IXGBE_WRITE_FLUSH(hw); 8419 8420 return IXGBE_SUCCESS; 8421 } 8422 8423 /* restore n-tuple filter */ 8424 static inline void 8425 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev) 8426 { 8427 struct ixgbe_filter_info *filter_info = 8428 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8429 struct ixgbe_5tuple_filter *node; 8430 8431 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) { 8432 ixgbe_inject_5tuple_filter(dev, node); 8433 } 8434 } 8435 8436 /* restore ethernet type filter */ 8437 static inline void 8438 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev) 8439 { 8440 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8441 struct ixgbe_filter_info *filter_info = 8442 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8443 int i; 8444 8445 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8446 if (filter_info->ethertype_mask & (1 << i)) { 8447 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 8448 filter_info->ethertype_filters[i].etqf); 8449 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 8450 filter_info->ethertype_filters[i].etqs); 8451 IXGBE_WRITE_FLUSH(hw); 8452 } 8453 } 8454 } 8455 8456 /* restore SYN filter */ 8457 static inline void 8458 ixgbe_syn_filter_restore(struct rte_eth_dev *dev) 8459 { 8460 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8461 struct ixgbe_filter_info *filter_info = 8462 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8463 uint32_t synqf; 8464 8465 synqf = filter_info->syn_info; 8466 8467 if (synqf & IXGBE_SYN_FILTER_ENABLE) { 8468 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf); 8469 IXGBE_WRITE_FLUSH(hw); 8470 } 8471 } 8472 8473 /* restore L2 tunnel filter */ 8474 static inline void 8475 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev) 8476 { 8477 struct ixgbe_l2_tn_info *l2_tn_info = 8478 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8479 struct ixgbe_l2_tn_filter *node; 8480 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8481 8482 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) { 8483 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type; 8484 l2_tn_conf.tunnel_id = node->key.tn_id; 8485 l2_tn_conf.pool = node->pool; 8486 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE); 8487 } 8488 } 8489 8490 /* restore rss filter */ 8491 static inline void 8492 ixgbe_rss_filter_restore(struct rte_eth_dev *dev) 8493 { 8494 struct ixgbe_filter_info *filter_info = 8495 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8496 8497 if (filter_info->rss_info.conf.queue_num) 8498 ixgbe_config_rss_filter(dev, 8499 &filter_info->rss_info, TRUE); 8500 } 8501 8502 static int 8503 ixgbe_filter_restore(struct rte_eth_dev *dev) 8504 { 8505 ixgbe_ntuple_filter_restore(dev); 8506 ixgbe_ethertype_filter_restore(dev); 8507 ixgbe_syn_filter_restore(dev); 8508 ixgbe_fdir_filter_restore(dev); 8509 ixgbe_l2_tn_filter_restore(dev); 8510 ixgbe_rss_filter_restore(dev); 8511 8512 return 0; 8513 } 8514 8515 static void 8516 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev) 8517 { 8518 struct ixgbe_l2_tn_info *l2_tn_info = 8519 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8520 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8521 8522 if (l2_tn_info->e_tag_en) 8523 (void)ixgbe_e_tag_enable(hw); 8524 8525 if (l2_tn_info->e_tag_fwd_en) 8526 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1); 8527 8528 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type); 8529 } 8530 8531 /* remove all the n-tuple filters */ 8532 void 8533 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev) 8534 { 8535 struct ixgbe_filter_info *filter_info = 8536 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8537 struct ixgbe_5tuple_filter *p_5tuple; 8538 8539 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) 8540 ixgbe_remove_5tuple_filter(dev, p_5tuple); 8541 } 8542 8543 /* remove all the ether type filters */ 8544 void 8545 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev) 8546 { 8547 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8548 struct ixgbe_filter_info *filter_info = 8549 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8550 int i; 8551 8552 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) { 8553 if (filter_info->ethertype_mask & (1 << i) && 8554 !filter_info->ethertype_filters[i].conf) { 8555 (void)ixgbe_ethertype_filter_remove(filter_info, 8556 (uint8_t)i); 8557 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0); 8558 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0); 8559 IXGBE_WRITE_FLUSH(hw); 8560 } 8561 } 8562 } 8563 8564 /* remove the SYN filter */ 8565 void 8566 ixgbe_clear_syn_filter(struct rte_eth_dev *dev) 8567 { 8568 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); 8569 struct ixgbe_filter_info *filter_info = 8570 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private); 8571 8572 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) { 8573 filter_info->syn_info = 0; 8574 8575 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0); 8576 IXGBE_WRITE_FLUSH(hw); 8577 } 8578 } 8579 8580 /* remove all the L2 tunnel filters */ 8581 int 8582 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev) 8583 { 8584 struct ixgbe_l2_tn_info *l2_tn_info = 8585 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private); 8586 struct ixgbe_l2_tn_filter *l2_tn_filter; 8587 struct rte_eth_l2_tunnel_conf l2_tn_conf; 8588 int ret = 0; 8589 8590 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) { 8591 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type; 8592 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id; 8593 l2_tn_conf.pool = l2_tn_filter->pool; 8594 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf); 8595 if (ret < 0) 8596 return ret; 8597 } 8598 8599 return 0; 8600 } 8601 8602 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); 8603 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); 8604 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 8605 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd); 8606 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map); 8607 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci"); 8608 8609 RTE_INIT(ixgbe_init_log) 8610 { 8611 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init"); 8612 if (ixgbe_logtype_init >= 0) 8613 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE); 8614 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver"); 8615 if (ixgbe_logtype_driver >= 0) 8616 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE); 8617 } 8618