1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2001-2018 3 */ 4 5 6 #include "ixgbe_api.h" 7 #include "ixgbe_type.h" 8 #include "ixgbe_vf.h" 9 10 #ifndef IXGBE_VFWRITE_REG 11 #define IXGBE_VFWRITE_REG IXGBE_WRITE_REG 12 #endif 13 #ifndef IXGBE_VFREAD_REG 14 #define IXGBE_VFREAD_REG IXGBE_READ_REG 15 #endif 16 17 /** 18 * ixgbe_init_ops_vf - Initialize the pointers for vf 19 * @hw: pointer to hardware structure 20 * 21 * This will assign function pointers, adapter-specific functions can 22 * override the assignment of generic function pointers by assigning 23 * their own adapter-specific function pointers. 24 * Does not touch the hardware. 25 **/ 26 s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw) 27 { 28 /* MAC */ 29 hw->mac.ops.init_hw = ixgbe_init_hw_vf; 30 hw->mac.ops.reset_hw = ixgbe_reset_hw_vf; 31 hw->mac.ops.start_hw = ixgbe_start_hw_vf; 32 /* Cannot clear stats on VF */ 33 hw->mac.ops.clear_hw_cntrs = NULL; 34 hw->mac.ops.get_media_type = NULL; 35 hw->mac.ops.get_mac_addr = ixgbe_get_mac_addr_vf; 36 hw->mac.ops.stop_adapter = ixgbe_stop_adapter_vf; 37 hw->mac.ops.get_bus_info = NULL; 38 hw->mac.ops.negotiate_api_version = ixgbevf_negotiate_api_version; 39 40 /* Link */ 41 hw->mac.ops.setup_link = ixgbe_setup_mac_link_vf; 42 hw->mac.ops.check_link = ixgbe_check_mac_link_vf; 43 hw->mac.ops.get_link_capabilities = NULL; 44 45 /* RAR, Multicast, VLAN */ 46 hw->mac.ops.set_rar = ixgbe_set_rar_vf; 47 hw->mac.ops.set_uc_addr = ixgbevf_set_uc_addr_vf; 48 hw->mac.ops.init_rx_addrs = NULL; 49 hw->mac.ops.update_mc_addr_list = ixgbe_update_mc_addr_list_vf; 50 hw->mac.ops.update_xcast_mode = ixgbevf_update_xcast_mode; 51 hw->mac.ops.enable_mc = NULL; 52 hw->mac.ops.disable_mc = NULL; 53 hw->mac.ops.clear_vfta = NULL; 54 hw->mac.ops.set_vfta = ixgbe_set_vfta_vf; 55 hw->mac.ops.set_rlpml = ixgbevf_rlpml_set_vf; 56 57 hw->mac.max_tx_queues = 1; 58 hw->mac.max_rx_queues = 1; 59 60 hw->mbx.ops.init_params = ixgbe_init_mbx_params_vf; 61 62 return IXGBE_SUCCESS; 63 } 64 65 /* ixgbe_virt_clr_reg - Set register to default (power on) state. 66 * @hw: pointer to hardware structure 67 */ 68 static void ixgbe_virt_clr_reg(struct ixgbe_hw *hw) 69 { 70 int i; 71 u32 vfsrrctl; 72 u32 vfdca_rxctrl; 73 u32 vfdca_txctrl; 74 75 /* VRSRRCTL default values (BSIZEPACKET = 2048, BSIZEHEADER = 256) */ 76 vfsrrctl = 0x100 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; 77 vfsrrctl |= 0x800 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; 78 79 /* DCA_RXCTRL default value */ 80 vfdca_rxctrl = IXGBE_DCA_RXCTRL_DESC_RRO_EN | 81 IXGBE_DCA_RXCTRL_DATA_WRO_EN | 82 IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 83 84 /* DCA_TXCTRL default value */ 85 vfdca_txctrl = IXGBE_DCA_TXCTRL_DESC_RRO_EN | 86 IXGBE_DCA_TXCTRL_DESC_WRO_EN | 87 IXGBE_DCA_TXCTRL_DATA_RRO_EN; 88 89 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0); 90 91 for (i = 0; i < 7; i++) { 92 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0); 93 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0); 94 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), 0); 95 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), vfsrrctl); 96 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0); 97 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0); 98 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), 0); 99 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(i), 0); 100 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(i), 0); 101 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(i), vfdca_rxctrl); 102 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i), vfdca_txctrl); 103 } 104 105 IXGBE_WRITE_FLUSH(hw); 106 } 107 108 /** 109 * ixgbe_start_hw_vf - Prepare hardware for Tx/Rx 110 * @hw: pointer to hardware structure 111 * 112 * Starts the hardware by filling the bus info structure and media type, clears 113 * all on chip counters, initializes receive address registers, multicast 114 * table, VLAN filter table, calls routine to set up link and flow control 115 * settings, and leaves transmit and receive units disabled and uninitialized 116 **/ 117 s32 ixgbe_start_hw_vf(struct ixgbe_hw *hw) 118 { 119 /* Clear adapter stopped flag */ 120 hw->adapter_stopped = false; 121 122 return IXGBE_SUCCESS; 123 } 124 125 /** 126 * ixgbe_init_hw_vf - virtual function hardware initialization 127 * @hw: pointer to hardware structure 128 * 129 * Initialize the hardware by resetting the hardware and then starting 130 * the hardware 131 **/ 132 s32 ixgbe_init_hw_vf(struct ixgbe_hw *hw) 133 { 134 s32 status = hw->mac.ops.start_hw(hw); 135 136 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 137 138 return status; 139 } 140 141 /** 142 * ixgbe_reset_hw_vf - Performs hardware reset 143 * @hw: pointer to hardware structure 144 * 145 * Resets the hardware by reseting the transmit and receive units, masks and 146 * clears all interrupts. 147 **/ 148 s32 ixgbe_reset_hw_vf(struct ixgbe_hw *hw) 149 { 150 struct ixgbe_mbx_info *mbx = &hw->mbx; 151 u32 timeout = IXGBE_VF_INIT_TIMEOUT; 152 s32 ret_val = IXGBE_ERR_INVALID_MAC_ADDR; 153 u32 msgbuf[IXGBE_VF_PERMADDR_MSG_LEN]; 154 u8 *addr = (u8 *)(&msgbuf[1]); 155 156 DEBUGFUNC("ixgbevf_reset_hw_vf"); 157 158 /* Call adapter stop to disable tx/rx and clear interrupts */ 159 hw->mac.ops.stop_adapter(hw); 160 161 /* reset the api version */ 162 hw->api_version = ixgbe_mbox_api_10; 163 164 DEBUGOUT("Issuing a function level reset to MAC\n"); 165 166 IXGBE_VFWRITE_REG(hw, IXGBE_VFCTRL, IXGBE_CTRL_RST); 167 IXGBE_WRITE_FLUSH(hw); 168 169 msec_delay(50); 170 171 /* we cannot reset while the RSTI / RSTD bits are asserted */ 172 while (!mbx->ops.check_for_rst(hw, 0) && timeout) { 173 timeout--; 174 usec_delay(5); 175 } 176 177 if (!timeout) 178 return IXGBE_ERR_RESET_FAILED; 179 180 /* Reset VF registers to initial values */ 181 ixgbe_virt_clr_reg(hw); 182 183 /* mailbox timeout can now become active */ 184 mbx->timeout = IXGBE_VF_MBX_INIT_TIMEOUT; 185 186 msgbuf[0] = IXGBE_VF_RESET; 187 mbx->ops.write_posted(hw, msgbuf, 1, 0); 188 189 msec_delay(10); 190 191 /* 192 * set our "perm_addr" based on info provided by PF 193 * also set up the mc_filter_type which is piggy backed 194 * on the mac address in word 3 195 */ 196 ret_val = mbx->ops.read_posted(hw, msgbuf, 197 IXGBE_VF_PERMADDR_MSG_LEN, 0); 198 if (ret_val) 199 return ret_val; 200 201 if (msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK) && 202 msgbuf[0] != (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_NACK)) 203 return IXGBE_ERR_INVALID_MAC_ADDR; 204 205 if (msgbuf[0] == (IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK)) 206 memcpy(hw->mac.perm_addr, addr, IXGBE_ETH_LENGTH_OF_ADDRESS); 207 208 hw->mac.mc_filter_type = msgbuf[IXGBE_VF_MC_TYPE_WORD]; 209 210 return ret_val; 211 } 212 213 /** 214 * ixgbe_stop_adapter_vf - Generic stop Tx/Rx units 215 * @hw: pointer to hardware structure 216 * 217 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 218 * disables transmit and receive units. The adapter_stopped flag is used by 219 * the shared code and drivers to determine if the adapter is in a stopped 220 * state and should not touch the hardware. 221 **/ 222 s32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw) 223 { 224 u32 reg_val; 225 u16 i; 226 227 /* 228 * Set the adapter_stopped flag so other driver functions stop touching 229 * the hardware 230 */ 231 hw->adapter_stopped = true; 232 233 /* Clear interrupt mask to stop from interrupts being generated */ 234 IXGBE_VFWRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); 235 236 /* Clear any pending interrupts, flush previous writes */ 237 IXGBE_VFREAD_REG(hw, IXGBE_VTEICR); 238 239 /* Disable the transmit unit. Each queue must be disabled. */ 240 for (i = 0; i < hw->mac.max_tx_queues; i++) 241 IXGBE_VFWRITE_REG(hw, IXGBE_VFTXDCTL(i), IXGBE_TXDCTL_SWFLSH); 242 243 /* Disable the receive unit by stopping each queue */ 244 for (i = 0; i < hw->mac.max_rx_queues; i++) { 245 reg_val = IXGBE_VFREAD_REG(hw, IXGBE_VFRXDCTL(i)); 246 reg_val &= ~IXGBE_RXDCTL_ENABLE; 247 IXGBE_VFWRITE_REG(hw, IXGBE_VFRXDCTL(i), reg_val); 248 } 249 /* Clear packet split and pool config */ 250 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, 0); 251 252 /* flush all queues disables */ 253 IXGBE_WRITE_FLUSH(hw); 254 msec_delay(2); 255 256 return IXGBE_SUCCESS; 257 } 258 259 /** 260 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 261 * @hw: pointer to hardware structure 262 * @mc_addr: the multicast address 263 * 264 * Extracts the 12 bits, from a multicast address, to determine which 265 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 266 * incoming rx multicast addresses, to determine the bit-vector to check in 267 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 268 * by the MO field of the MCSTCTRL. The MO field is set during initialization 269 * to mc_filter_type. 270 **/ 271 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 272 { 273 u32 vector = 0; 274 275 switch (hw->mac.mc_filter_type) { 276 case 0: /* use bits [47:36] of the address */ 277 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 278 break; 279 case 1: /* use bits [46:35] of the address */ 280 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 281 break; 282 case 2: /* use bits [45:34] of the address */ 283 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 284 break; 285 case 3: /* use bits [43:32] of the address */ 286 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 287 break; 288 default: /* Invalid mc_filter_type */ 289 DEBUGOUT("MC filter type param set incorrectly\n"); 290 ASSERT(0); 291 break; 292 } 293 294 /* vector can only be 12-bits or boundary will be exceeded */ 295 vector &= 0xFFF; 296 return vector; 297 } 298 299 STATIC s32 ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw, u32 *msg, 300 u32 *retmsg, u16 size) 301 { 302 struct ixgbe_mbx_info *mbx = &hw->mbx; 303 s32 retval = mbx->ops.write_posted(hw, msg, size, 0); 304 305 if (retval) 306 return retval; 307 308 return mbx->ops.read_posted(hw, retmsg, size, 0); 309 } 310 311 /** 312 * ixgbe_set_rar_vf - set device MAC address 313 * @hw: pointer to hardware structure 314 * @index: Receive address register to write 315 * @addr: Address to put into receive address register 316 * @vmdq: VMDq "set" or "pool" index 317 * @enable_addr: set flag that address is active 318 **/ 319 s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 320 u32 enable_addr) 321 { 322 u32 msgbuf[3]; 323 u8 *msg_addr = (u8 *)(&msgbuf[1]); 324 s32 ret_val; 325 UNREFERENCED_3PARAMETER(vmdq, enable_addr, index); 326 327 memset(msgbuf, 0, 12); 328 msgbuf[0] = IXGBE_VF_SET_MAC_ADDR; 329 memcpy(msg_addr, addr, 6); 330 ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 3); 331 332 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS; 333 334 /* if nacked the address was rejected, use "perm_addr" */ 335 if (!ret_val && 336 (msgbuf[0] == (IXGBE_VF_SET_MAC_ADDR | IXGBE_VT_MSGTYPE_NACK))) { 337 ixgbe_get_mac_addr_vf(hw, hw->mac.addr); 338 return IXGBE_ERR_MBX; 339 } 340 341 return ret_val; 342 } 343 344 /** 345 * ixgbe_update_mc_addr_list_vf - Update Multicast addresses 346 * @hw: pointer to the HW structure 347 * @mc_addr_list: array of multicast addresses to program 348 * @mc_addr_count: number of multicast addresses to program 349 * @next: caller supplied function to return next address in list 350 * @clear: unused 351 * 352 * Updates the Multicast Table Array. 353 **/ 354 s32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list, 355 u32 mc_addr_count, ixgbe_mc_addr_itr next, 356 bool clear) 357 { 358 struct ixgbe_mbx_info *mbx = &hw->mbx; 359 u32 msgbuf[IXGBE_VFMAILBOX_SIZE]; 360 u16 *vector_list = (u16 *)&msgbuf[1]; 361 u32 vector; 362 u32 cnt, i; 363 u32 vmdq; 364 365 UNREFERENCED_1PARAMETER(clear); 366 367 DEBUGFUNC("ixgbe_update_mc_addr_list_vf"); 368 369 /* Each entry in the list uses 1 16 bit word. We have 30 370 * 16 bit words available in our HW msg buffer (minus 1 for the 371 * msg type). That's 30 hash values if we pack 'em right. If 372 * there are more than 30 MC addresses to add then punt the 373 * extras for now and then add code to handle more than 30 later. 374 * It would be unusual for a server to request that many multi-cast 375 * addresses except for in large enterprise network environments. 376 */ 377 378 DEBUGOUT1("MC Addr Count = %d\n", mc_addr_count); 379 380 cnt = (mc_addr_count > 30) ? 30 : mc_addr_count; 381 msgbuf[0] = IXGBE_VF_SET_MULTICAST; 382 msgbuf[0] |= cnt << IXGBE_VT_MSGINFO_SHIFT; 383 384 for (i = 0; i < cnt; i++) { 385 vector = ixgbe_mta_vector(hw, next(hw, &mc_addr_list, &vmdq)); 386 DEBUGOUT1("Hash value = 0x%03X\n", vector); 387 vector_list[i] = (u16)vector; 388 } 389 390 return mbx->ops.write_posted(hw, msgbuf, IXGBE_VFMAILBOX_SIZE, 0); 391 } 392 393 /** 394 * ixgbevf_update_xcast_mode - Update Multicast mode 395 * @hw: pointer to the HW structure 396 * @xcast_mode: new multicast mode 397 * 398 * Updates the Multicast Mode of VF. 399 **/ 400 s32 ixgbevf_update_xcast_mode(struct ixgbe_hw *hw, int xcast_mode) 401 { 402 u32 msgbuf[2]; 403 s32 err; 404 405 switch (hw->api_version) { 406 case ixgbe_mbox_api_12: 407 /* New modes were introduced in 1.3 version */ 408 if (xcast_mode > IXGBEVF_XCAST_MODE_ALLMULTI) 409 return IXGBE_ERR_FEATURE_NOT_SUPPORTED; 410 /* Fall through */ 411 case ixgbe_mbox_api_13: 412 break; 413 default: 414 return IXGBE_ERR_FEATURE_NOT_SUPPORTED; 415 } 416 417 msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE; 418 msgbuf[1] = xcast_mode; 419 420 err = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2); 421 if (err) 422 return err; 423 424 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS; 425 if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK)) 426 return IXGBE_ERR_FEATURE_NOT_SUPPORTED; 427 return IXGBE_SUCCESS; 428 } 429 430 /** 431 * ixgbe_set_vfta_vf - Set/Unset vlan filter table address 432 * @hw: pointer to the HW structure 433 * @vlan: 12 bit VLAN ID 434 * @vind: unused by VF drivers 435 * @vlan_on: if true then set bit, else clear bit 436 * @vlvf_bypass: boolean flag indicating updating default pool is okay 437 * 438 * Turn on/off specified VLAN in the VLAN filter table. 439 **/ 440 s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, 441 bool vlan_on, bool vlvf_bypass) 442 { 443 u32 msgbuf[2]; 444 s32 ret_val; 445 UNREFERENCED_2PARAMETER(vind, vlvf_bypass); 446 447 msgbuf[0] = IXGBE_VF_SET_VLAN; 448 msgbuf[1] = vlan; 449 /* Setting the 8 bit field MSG INFO to TRUE indicates "add" */ 450 msgbuf[0] |= vlan_on << IXGBE_VT_MSGINFO_SHIFT; 451 452 ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2); 453 if (!ret_val && (msgbuf[0] & IXGBE_VT_MSGTYPE_ACK)) 454 return IXGBE_SUCCESS; 455 456 return ret_val | (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK); 457 } 458 459 /** 460 * ixgbe_get_num_of_tx_queues_vf - Get number of TX queues 461 * @hw: pointer to hardware structure 462 * 463 * Returns the number of transmit queues for the given adapter. 464 **/ 465 u32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw) 466 { 467 UNREFERENCED_1PARAMETER(hw); 468 return IXGBE_VF_MAX_TX_QUEUES; 469 } 470 471 /** 472 * ixgbe_get_num_of_rx_queues_vf - Get number of RX queues 473 * @hw: pointer to hardware structure 474 * 475 * Returns the number of receive queues for the given adapter. 476 **/ 477 u32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw) 478 { 479 UNREFERENCED_1PARAMETER(hw); 480 return IXGBE_VF_MAX_RX_QUEUES; 481 } 482 483 /** 484 * ixgbe_get_mac_addr_vf - Read device MAC address 485 * @hw: pointer to the HW structure 486 * @mac_addr: the MAC address 487 **/ 488 s32 ixgbe_get_mac_addr_vf(struct ixgbe_hw *hw, u8 *mac_addr) 489 { 490 int i; 491 492 for (i = 0; i < IXGBE_ETH_LENGTH_OF_ADDRESS; i++) 493 mac_addr[i] = hw->mac.perm_addr[i]; 494 495 return IXGBE_SUCCESS; 496 } 497 498 s32 ixgbevf_set_uc_addr_vf(struct ixgbe_hw *hw, u32 index, u8 *addr) 499 { 500 u32 msgbuf[3], msgbuf_chk; 501 u8 *msg_addr = (u8 *)(&msgbuf[1]); 502 s32 ret_val; 503 504 memset(msgbuf, 0, sizeof(msgbuf)); 505 /* 506 * If index is one then this is the start of a new list and needs 507 * indication to the PF so it can do it's own list management. 508 * If it is zero then that tells the PF to just clear all of 509 * this VF's macvlans and there is no new list. 510 */ 511 msgbuf[0] |= index << IXGBE_VT_MSGINFO_SHIFT; 512 msgbuf[0] |= IXGBE_VF_SET_MACVLAN; 513 msgbuf_chk = msgbuf[0]; 514 if (addr) 515 memcpy(msg_addr, addr, 6); 516 517 ret_val = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 3); 518 if (!ret_val) { 519 msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS; 520 521 if (msgbuf[0] == (msgbuf_chk | IXGBE_VT_MSGTYPE_NACK)) 522 return IXGBE_ERR_OUT_OF_MEM; 523 } 524 525 return ret_val; 526 } 527 528 /** 529 * ixgbe_setup_mac_link_vf - Setup MAC link settings 530 * @hw: pointer to hardware structure 531 * @speed: new link speed 532 * @autoneg_wait_to_complete: true when waiting for completion is needed 533 * 534 * Set the link speed in the AUTOC register and restarts link. 535 **/ 536 s32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed speed, 537 bool autoneg_wait_to_complete) 538 { 539 UNREFERENCED_3PARAMETER(hw, speed, autoneg_wait_to_complete); 540 return IXGBE_SUCCESS; 541 } 542 543 /** 544 * ixgbe_check_mac_link_vf - Get link/speed status 545 * @hw: pointer to hardware structure 546 * @speed: pointer to link speed 547 * @link_up: true is link is up, false otherwise 548 * @autoneg_wait_to_complete: true when waiting for completion is needed 549 * 550 * Reads the links register to determine if link is up and the current speed 551 **/ 552 s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 553 bool *link_up, bool autoneg_wait_to_complete) 554 { 555 struct ixgbe_mbx_info *mbx = &hw->mbx; 556 struct ixgbe_mac_info *mac = &hw->mac; 557 s32 ret_val = IXGBE_SUCCESS; 558 u32 links_reg; 559 u32 in_msg = 0; 560 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 561 562 /* If we were hit with a reset drop the link */ 563 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout) 564 mac->get_link_status = true; 565 566 if (!mac->get_link_status) 567 goto out; 568 569 /* if link status is down no point in checking to see if pf is up */ 570 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 571 if (!(links_reg & IXGBE_LINKS_UP)) 572 goto out; 573 574 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs 575 * before the link status is correct 576 */ 577 if (mac->type == ixgbe_mac_82599_vf) { 578 int i; 579 580 for (i = 0; i < 5; i++) { 581 usec_delay(100); 582 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS); 583 584 if (!(links_reg & IXGBE_LINKS_UP)) 585 goto out; 586 } 587 } 588 589 switch (links_reg & IXGBE_LINKS_SPEED_82599) { 590 case IXGBE_LINKS_SPEED_10G_82599: 591 *speed = IXGBE_LINK_SPEED_10GB_FULL; 592 if (hw->mac.type >= ixgbe_mac_X550) { 593 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 594 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 595 } 596 break; 597 case IXGBE_LINKS_SPEED_1G_82599: 598 *speed = IXGBE_LINK_SPEED_1GB_FULL; 599 break; 600 case IXGBE_LINKS_SPEED_100_82599: 601 *speed = IXGBE_LINK_SPEED_100_FULL; 602 if (hw->mac.type == ixgbe_mac_X550) { 603 if (links_reg & IXGBE_LINKS_SPEED_NON_STD) 604 *speed = IXGBE_LINK_SPEED_5GB_FULL; 605 } 606 break; 607 case IXGBE_LINKS_SPEED_10_X550EM_A: 608 *speed = IXGBE_LINK_SPEED_UNKNOWN; 609 /* Since Reserved in older MAC's */ 610 if (hw->mac.type >= ixgbe_mac_X550) 611 *speed = IXGBE_LINK_SPEED_10_FULL; 612 break; 613 default: 614 *speed = IXGBE_LINK_SPEED_UNKNOWN; 615 } 616 617 /* if the read failed it could just be a mailbox collision, best wait 618 * until we are called again and don't report an error 619 */ 620 if (mbx->ops.read(hw, &in_msg, 1, 0)) 621 goto out; 622 623 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) { 624 /* msg is not CTS and is NACK we must have lost CTS status */ 625 if (in_msg & IXGBE_VT_MSGTYPE_NACK) 626 ret_val = -1; 627 goto out; 628 } 629 630 /* the pf is talking, if we timed out in the past we reinit */ 631 if (!mbx->timeout) { 632 ret_val = -1; 633 goto out; 634 } 635 636 /* if we passed all the tests above then the link is up and we no 637 * longer need to check for link 638 */ 639 mac->get_link_status = false; 640 641 out: 642 *link_up = !mac->get_link_status; 643 return ret_val; 644 } 645 646 /** 647 * ixgbevf_rlpml_set_vf - Set the maximum receive packet length 648 * @hw: pointer to the HW structure 649 * @max_size: value to assign to max frame size 650 **/ 651 s32 ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size) 652 { 653 u32 msgbuf[2]; 654 s32 retval; 655 656 msgbuf[0] = IXGBE_VF_SET_LPE; 657 msgbuf[1] = max_size; 658 659 retval = ixgbevf_write_msg_read_ack(hw, msgbuf, msgbuf, 2); 660 if (retval) 661 return retval; 662 if ((msgbuf[0] & IXGBE_VF_SET_LPE) && 663 (msgbuf[0] & IXGBE_VT_MSGTYPE_NACK)) 664 return IXGBE_ERR_MBX; 665 666 return 0; 667 } 668 669 /** 670 * ixgbevf_negotiate_api_version - Negotiate supported API version 671 * @hw: pointer to the HW structure 672 * @api: integer containing requested API version 673 **/ 674 int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api) 675 { 676 int err; 677 u32 msg[3]; 678 679 /* Negotiate the mailbox API version */ 680 msg[0] = IXGBE_VF_API_NEGOTIATE; 681 msg[1] = api; 682 msg[2] = 0; 683 684 err = ixgbevf_write_msg_read_ack(hw, msg, msg, 3); 685 if (!err) { 686 msg[0] &= ~IXGBE_VT_MSGTYPE_CTS; 687 688 /* Store value and return 0 on success */ 689 if (msg[0] == (IXGBE_VF_API_NEGOTIATE | IXGBE_VT_MSGTYPE_ACK)) { 690 hw->api_version = api; 691 return 0; 692 } 693 694 err = IXGBE_ERR_INVALID_ARGUMENT; 695 } 696 697 return err; 698 } 699 700 int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs, 701 unsigned int *default_tc) 702 { 703 int err; 704 u32 msg[5]; 705 706 /* do nothing if API doesn't support ixgbevf_get_queues */ 707 switch (hw->api_version) { 708 case ixgbe_mbox_api_11: 709 case ixgbe_mbox_api_12: 710 case ixgbe_mbox_api_13: 711 break; 712 default: 713 return 0; 714 } 715 716 /* Fetch queue configuration from the PF */ 717 msg[0] = IXGBE_VF_GET_QUEUES; 718 msg[1] = msg[2] = msg[3] = msg[4] = 0; 719 720 err = ixgbevf_write_msg_read_ack(hw, msg, msg, 5); 721 if (!err) { 722 msg[0] &= ~IXGBE_VT_MSGTYPE_CTS; 723 724 /* 725 * if we we didn't get an ACK there must have been 726 * some sort of mailbox error so we should treat it 727 * as such 728 */ 729 if (msg[0] != (IXGBE_VF_GET_QUEUES | IXGBE_VT_MSGTYPE_ACK)) 730 return IXGBE_ERR_MBX; 731 732 /* record and validate values from message */ 733 hw->mac.max_tx_queues = msg[IXGBE_VF_TX_QUEUES]; 734 if (hw->mac.max_tx_queues == 0 || 735 hw->mac.max_tx_queues > IXGBE_VF_MAX_TX_QUEUES) 736 hw->mac.max_tx_queues = IXGBE_VF_MAX_TX_QUEUES; 737 738 hw->mac.max_rx_queues = msg[IXGBE_VF_RX_QUEUES]; 739 if (hw->mac.max_rx_queues == 0 || 740 hw->mac.max_rx_queues > IXGBE_VF_MAX_RX_QUEUES) 741 hw->mac.max_rx_queues = IXGBE_VF_MAX_RX_QUEUES; 742 743 *num_tcs = msg[IXGBE_VF_TRANS_VLAN]; 744 /* in case of unknown state assume we cannot tag frames */ 745 if (*num_tcs > hw->mac.max_rx_queues) 746 *num_tcs = 1; 747 748 *default_tc = msg[IXGBE_VF_DEF_QUEUE]; 749 /* default to queue 0 on out-of-bounds queue number */ 750 if (*default_tc >= hw->mac.max_tx_queues) 751 *default_tc = 0; 752 } 753 754 return err; 755 } 756