1 /******************************************************************************* 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 #ifndef _IXGBE_DCB_H_ 35 #define _IXGBE_DCB_H_ 36 37 #include "ixgbe_type.h" 38 39 /* DCB defines */ 40 /* DCB credit calculation defines */ 41 #define IXGBE_DCB_CREDIT_QUANTUM 64 42 #define IXGBE_DCB_MAX_CREDIT_REFILL 200 /* 200 * 64B = 12800B */ 43 #define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/ 44 #define IXGBE_DCB_MAX_CREDIT (2 * IXGBE_DCB_MAX_CREDIT_REFILL) 45 46 /* 513 for 32KB TSO packet */ 47 #define IXGBE_DCB_MIN_TSO_CREDIT \ 48 ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1) 49 50 /* DCB configuration defines */ 51 #define IXGBE_DCB_MAX_USER_PRIORITY 8 52 #define IXGBE_DCB_MAX_BW_GROUP 8 53 #define IXGBE_DCB_BW_PERCENT 100 54 55 #define IXGBE_DCB_TX_CONFIG 0 56 #define IXGBE_DCB_RX_CONFIG 1 57 58 /* DCB capability defines */ 59 #define IXGBE_DCB_PG_SUPPORT 0x00000001 60 #define IXGBE_DCB_PFC_SUPPORT 0x00000002 61 #define IXGBE_DCB_BCN_SUPPORT 0x00000004 62 #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 63 #define IXGBE_DCB_GSP_SUPPORT 0x00000010 64 65 struct ixgbe_dcb_support { 66 u32 capabilities; /* DCB capabilities */ 67 68 /* Each bit represents a number of TCs configurable in the hw. 69 * If 8 traffic classes can be configured, the value is 0x80. */ 70 u8 traffic_classes; 71 u8 pfc_traffic_classes; 72 }; 73 74 enum ixgbe_dcb_tsa { 75 ixgbe_dcb_tsa_ets = 0, 76 ixgbe_dcb_tsa_group_strict_cee, 77 ixgbe_dcb_tsa_strict 78 }; 79 80 /* Traffic class bandwidth allocation per direction */ 81 struct ixgbe_dcb_tc_path { 82 u8 bwg_id; /* Bandwidth Group (BWG) ID */ 83 u8 bwg_percent; /* % of BWG's bandwidth */ 84 u8 link_percent; /* % of link bandwidth */ 85 u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ 86 u16 data_credits_refill; /* Credit refill amount in 64B granularity */ 87 u16 data_credits_max; /* Max credits for a configured packet buffer 88 * in 64B granularity.*/ 89 enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */ 90 }; 91 92 enum ixgbe_dcb_pfc { 93 ixgbe_dcb_pfc_disabled = 0, 94 ixgbe_dcb_pfc_enabled, 95 ixgbe_dcb_pfc_enabled_txonly, 96 ixgbe_dcb_pfc_enabled_rxonly 97 }; 98 99 /* Traffic class configuration */ 100 struct ixgbe_dcb_tc_config { 101 struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */ 102 enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */ 103 104 u16 desc_credits_max; /* For Tx Descriptor arbitration */ 105 u8 tc; /* Traffic class (TC) */ 106 }; 107 108 enum ixgbe_dcb_pba { 109 /* PBA[0-7] each use 64KB FIFO */ 110 ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL, 111 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ 112 ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED 113 }; 114 115 struct ixgbe_dcb_num_tcs { 116 u8 pg_tcs; 117 u8 pfc_tcs; 118 }; 119 120 struct ixgbe_dcb_config { 121 struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 122 struct ixgbe_dcb_support support; 123 struct ixgbe_dcb_num_tcs num_tcs; 124 u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */ 125 bool pfc_mode_enable; 126 bool round_robin_enable; 127 128 enum ixgbe_dcb_pba rx_pba_cfg; 129 130 u32 dcb_cfg_version; /* Not used...OS-specific? */ 131 u32 link_speed; /* For bandwidth allocation validation purpose */ 132 bool vt_mode; 133 }; 134 135 /* DCB driver APIs */ 136 137 /* DCB rule checking */ 138 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *); 139 140 /* DCB credits calculation */ 141 s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int); 142 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *, 143 struct ixgbe_dcb_config *, u32, u8); 144 145 /* DCB PFC */ 146 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *); 147 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 148 149 /* DCB stats */ 150 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *); 151 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 152 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 153 154 /* DCB config arbiters */ 155 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *, 156 struct ixgbe_dcb_config *); 157 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *, 158 struct ixgbe_dcb_config *); 159 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *, 160 struct ixgbe_dcb_config *); 161 162 /* DCB unpack routines */ 163 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *); 164 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *); 165 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *); 166 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *); 167 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *); 168 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *); 169 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8); 170 171 /* DCB initialization */ 172 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *); 173 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 174 #endif /* _IXGBE_DCB_H_ */ 175